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A methodology for hierarchical thermal simulation of ICs from gate-level to architecture design

Thermal simulations for semiconductor chip design at different levels are usually based on simplified models with severe assumptions due to intensive computational effort needed in numerical simulations. This work presents a unique methodology based on proper orthogonal decomposition, together with the concept of building block, that is able to substantially reduce the numerical degree of freedom in thermal simulation of semiconductor IC structure with different spatial resolutions. Such an approach could offer efficient multi-scale hierarchical thermal simulations for cost-effective thermal-aware design of semiconductor chips at different levels.