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SOS : Using Speculation for Memory Error Detection

With the problem of transient errors in integrated circuits becoming very critical in future process technologies, it is important to develop effective techniques for detection and possible recovery from such errors. Dense integration, lower supply voltages and higher frequencies make circuits more susceptible to bit flips due to cosmic-ray strikes. Memory cells, such as SRAMs and DRAMs, typically occupy a large portion of the real-estate and are hence particularly vulnerable to these transient faults. While techniques such as parity and ECC are being used to handle such situations, such safeguards can impose significant storage, performance, and power overheads, especially in highperformance designs. This paper investigates a fresh approach to developing transient-fault detection mechanisms. We show that speculative-execution resources inside the processor can be tailored to provide detection of errors that propagate in from memory. Using detailed experiments with different benchmarks, we demonstrate that the branch-predictor in conjunction with a lightweight value-predictor can catch most of the errors that come in to the processor from the memory system. We also show the microarchitectural extensions required for implementing such error-detectors.