{'fraction_non_alphanumeric': 0.022768670309653915, 'fraction_numerical': 0.0036429872495446266, 'mean_word_length': 5.701219512195122, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Using DG2VHDL to synthesize an FPGA implementation of the 1-D discrete wavelet transform

We introduce DG2VHDL, a design tool which bridges the gap between an abstract graphical description of a DSP algorithm and its concrete hardware description language (HDL) representation. DG2VHDL automatically translates a dependence graph (DG) into a synthesizable, behavioral VHDL entity that can be input to industrial-strength behavioral compilers for producing silicon implementations of the algorithm (FPGA, ASIC). The discrete wavelet transform (DWT) was selected to demonstrate that the tool facilitates the rapid prototyping of modular parallel structures for non-trivial algorithms with non-regular data dependency structure. In addition, the DWT is an important algorithm for data compression and feature extraction, among many other real-time DSP applications. We demonstrate here that the behavioral VHDL code produced automatically by the tool leads, after behavioral synthesis, to an efficient distributed memory and control modular array architecture which can be embedded into a single FPGA.