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A New Power-Gated Hybrid Defect Tolerant Approach Based on Modular Redundancy

This paper presents the design of a new power-efficient hybrid fault-tolerant architecture using power-gated method. The proposed design is capable of giving the system a built-in immunity to any single fault that occurs within the system with a reduction in the power consumption by approximately 50% compared to the prevailing methods. Moreover, the design is based on hybrid redundancy, which is the combination of both dynamic and static redundancy methods, thus availing advantages of the both. Static redundancy method takes care of the reliability of the system by ensuring the capability to encounter all types of faults whereas dynamic redundancy keeps the hardware usage minimal taking care of the power consumption. The proposed design stands on the logic that when there is no fault in the system, instead of activating all of the modules, we activate only two of the modules and when any mismatch is found between these two modules we activate the spare modules. In such a case, when there is no fault, power is consumed only for the two active modules switching off the rest of the system, thus saving the overall power consumption and maintaining the system reliability. Simulation result in Cadence Virtuoso platform also confirms our claim on significant power reduction for the proposed method, when implemented within a system.