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System-Level Behavioral Model of a 12-Bit 1.5-Bit Per Stage Pipelined ADC Based on Verilog®=-AMS

This document presents a system-level behavioral model of a 12-bit 1.5-bit/stage pipelined ADC based on Verilog-AMS that can be used in the CMOS circuit design activities. It was developed with one of the currently most used EDA tools, Cadence Virtuoso, the versatility of this software allowed to create a model that consist of subsystems at circuit level described in Verilog, Verilog-A and SPICE, in others words, Verilog-AMS. The model was tested in time and frequency, the results exhibit a SQNR of 73.7 dB and an ENoB of 11.5 bits when ideal parameters are present.