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A novel digit serial dual basis GF(2m) multiplier

A Novel architecture of low-complexity digit serial GF(2m) multiplier using dual basis representation is proposed in this paper. The architecture of digit serial multiplier is suitable for large word lengths such as those found in cryptographic applications and error correction codes. Digit serial multipliers can give a better trade-off between area and latency in comparison with bit-parallel realization which is costly, and bit-serial realization which is slower. The proposed multiplier is based on an irreducible trinomial and a look-ahead technique that performs the algorithm to calculate the extra elements of the operand represented in the dual basis multiplication process, and is formed by only one cell of tree structure in the MSD (most significant digit) first scheme. Compare to existing architectures, the results reveal that the new multiplier evidently have lower complexity of area and latency.