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A Nanocore/CMOS Hybrid System-on-Package (SoP) Architecture for Future Nanoelectronic Systems

Recent results showed that when the minimum feature size used in semiconductor device fabrication moves to sub nanometre scale, several physical and economic limits jeopardize the device behaviour, binary logic, and the lithography techniques currently used. To surpass this "brick-wall" and continue the Moore's law forever, novel nano-electronic devices are becoming more popular and promising. But, interconnecting nano-devices into complex electronic systems has not yet been demonstrated. In this paper, the authors propose a nanocore/CMOS hybrid system-on-package (SoP) architecture which is suitable for any emerging nanotechnology