{'fraction_non_alphanumeric': 0.034408602150537634, 'fraction_numerical': 0.002150537634408602, 'mean_word_length': 5.465277777777778, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Efficient Reed-Solomon based LDPC decoders

By exploring the specific characteristics of the matrices of Reed-Solomon (RS) based low-density parity-check (LDPC) codes, the authors manage to propose an efficient memory address generation (MAG) method for time-multiplexed (TM) RS-based LDPC code decoder architecture. This unique feature directly results in the MAG scheme which works perfectly with the TM decoders. Furthermore, along with the sum and sign accumulation unit (SSAU), a methodology for designing TM RS-based LDPC code decoder supporting high decoding throughput applications such as a 10GBASE-T system is presented. By developing and evaluating three decoder architectures with different folding factors, this approach proves to be suitable for variable design requirements. In addition, a shuffle network composed of de-multiplexers (deMUX's) and routing blocks is also incorporated to reduce the decoding latency.