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Electrical Masking Improvement with Standard Logic Cell Synthesis Using 45 nm Technology Node

Technology scaling impacts the probability of masking a propagating transient pulse. This paper presents a technique to improve the electrical masking of logic gates when considering the variation in the process, voltage, and temperature (PVT) for a 45-nm technology. The worst cases were exhibited in high temperature and low voltage, which enhanced the transient pulse to traverse to the primary outputs (POs). The vulnerable paths were used to select vulnerable gates for the mitigation approach. Due to worst cases of low voltage and high temperature, the gates at the POs were also selected for mitigation. The approach improved the electrical masking of the circuit by reducing the amplitudes of the transient pulses by 93% and 90% for low voltage and high temperature respectively with 57% area overhead.