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Impact of manufacturing on routing methodology at 32/22 nm

As the IC industry accelerates adoption of the 45 nm and 32 nm process nodes, designers are facing significant new challenges in meeting quality and manufacturability targets. The new challenges of nanometer routing---including very large (1B transistor) designs, complex DRC/DFM, and multiple optimization objectives---are stressing the fundamental ability of digital routing tools to solve the layout topology.
 To ensure that physical designs can be reliably manufactured, foundries are greatly expanding the number and complexity of design rules and DFM requirements at advanced nodes. The number of DRC and DFM rules has roughly doubled between the 90- and 32-nm nodes, depending on the foundry. The rule complexity, which is measured by the number of operations required to verify the rules, has grown even faster.
 DFM checks, which used to be voluntary, are now becoming mandatory just like traditional DRCs---with the type and complexity of checks being foundry dependent. DFM violations can cause issues ranging from chip failure to reduced reliability and decreased performance. If they aren't made carefully, however, changes to improve manufacturability can reduce performance, increase power consumption, or otherwise compromise the design..
 20 nm brings one more aspect from manufacturing side to the routing. It's double patterning (DP) what is completely new term both for process and Place&Route system. Contrary to DRC/DFM which is local effect double pattern violation is global one. Improper geometry on one side of a chip could result in the problem on other side of the chip. Such formulation contradicts to the local Search&Repair approach.
 To fully realize the advantages of moving to a new process node, while also maintaining turn-around-time, designers need a new routing platform that can more accurately model the numerous and complex DRC and DFM rules from the earliest stages of the routing process, natively invoke signoff DRC/DFM models and engines, use timing-driven routing to optimize critical paths, and manage huge design sizes with predictable runtimes.