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A leading zero(es) count algorithm

Floating point operations of addition, subtraction, multiplication and division for normalization require removing the leading zeros. Algorithms to remove the leading zeroes using NOR logic for input bits along with carry, XOR logic on result of floating point operation are proposed in literature. This paper proposes leading zero count algorithm using NAND logic for adjacent bits of result of floating point operation for normalization. The proposed method is simulated for floating point addition algorithm using one's complement notation for add/subtract operation with Quartus2 software Cyclone II family processor. An improvement in area by 43%, with increased performance of 52% with no change in power consumption is observed when compared with two's complement addition operation using XOR operation for counting leading zeroes.