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Design and Simulation of a Low Power Bluetooth Transceiver

This technical report demonstrates a fully integrated 2.4 GHz Bluetooth Transceiver in 0.18 m CMOS Technology. A Low IF (3Mhz) receiver architecture and direct modulation architecture is chosen for the transmitter to minimize the chip area and power consumption. To reduce the power consumption, the whole transceiver is designed to operate at 1.5V. The designed transceiver integrates all building blocks on-chip, including a RF switch, low-noise amplifier (LNA) with an input match network, an image rejection Mixer (IRM), gm-C Bandpass filter, The proposed transceiver has been designed and simulated with TSMC 0.18 m Mixed Mode CMOS technology. The receiver achieves a sensitivity of –80 dBm at 0.1% BER. The direct conversion transmitter delivers GFSK modulated waveform at a nominal output power of 4 dBm. This research confirms the integration of whole transceiver in standard CMOS process, which makes it possible to integrate both Analog transceiver and digital baseband parts on single wafer. This would lower the overall system cost.