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Impact of the scaling on the noise performance of deep-submicron Si/SiGe n-channel FETs

We present a simulation study of the thermal noise locally generated in the n-channel of strained-Si MOSFETs and compared the obtained results with those of a state-of-the-art 100 μm gate length bulk MOSFET. Local physical magnitudes governing the noise have been obtained using a commercial 2D device simulator that implements the impedance field method to calculate the overall noise behaviour at the terminals. We focus in the analysis of the ability of the devices to operate in the micro-power regime. The design of the s-Si MOSFET is non-optimal and low-doping regions were introduced between the gate and both the source and drain contacts to accommodate for the current shortcomings in the SiGe FET technology. AC results show excellent performance of s-Si MOSFET as compared to the bulk MOSFET. On the contrary, the noise performance of the bulk MOSFET is better than the one of s-Si MOSFETs. This is attributed to the poor design of the lateral structure of the s-Si MOSFET. A re-design of the structure, particularly, a reduction of the source and drain resistances, should allow for a significant reduction of the NF in these transistors.