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On Feasibility of FPGA Bitstream Compression During Placement and Routing

In this paper we examine the feasibility of a new approach to FPGA design bitstream compression which aims to optimise placement and routing in order to minimise the distribution of configuration data in the device. We present results from a variety of experiments which demonstrate how achievable compression ratio varies with the design size and applied constraints. The approach proves promising for certain designs where compression ratios up to 5 were achieved without compromising design timing.