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A Miniaturized LDPC Encoder: Two-Layer Architecture for CCSDS Near-Earth Standard

Quasi-cyclic low-density parity-check (QC-LDPC) codes, which have been adopted by the Consultative Committee for Space Data Systems (CCSDS), are widely used in Deep-Space (AR4JA) and Near-Earth (C2) communications. A large number of encoder architectures with CCSDS recommended standard have been proposed. But the existing architectures are not efficient enough in high-throughput implementations, many architectures have a lot of logical resources and registers. In this brief, we introduce a novel architecture with low resource utilization. A grouping algorithm is used to extract the common subexpressions (CS) of the encoding algorithm. Similar circuit structures are integrated through a two-layer architecture, which further reduces logical resources. For the special size of the generator’s matrix, we introduce a preprocessing method. In addition, configuration registers are used to replace the control unit. Implemented and verified on FPGA, the proposed architecture achieves a throughput of 4.69 Gbps using only 1658 LUTs and 1038 FFs. Compared with the previous architectures, this architecture achieves lower resource utilization and multi-Gbps throughput.