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Circuit modeling and simulation of CMOS circuits latchup induced by microwave pulse injection

In CMOS integrated circuits, latchup is a traditional inherent destruction phenomenon. This failure may jeopardize the correct function of digital circuits, or even cause chip thermal damage. In this paper, circuit modeling and simulation of latchup induced by microwave pulse injection into CMOS inverter has been investigated. Firstly, based on mutually coupled bipolar junction transistors (BJT) topology, the latchup equivalent circuit modeling triggered by microwave pulse is constructed. Secondly, an electro-thermal coupled model including junction transient self-heating effects in latchup process is presented via analogous between thermal dynamic and electronic circuit topology. Finally, the two parts circuits modeling together with previous works on SPICE modeling of CMOS inverter interference are integrated seamlessly. The model can predict latchup successfully in circuit level and evaluate device transient thermal susceptibility under high power microwave electromagnetic environment. The general latchup features of CMOS inverter for different microwave pulse modulation parameters are discussed.