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Sizing Power/Ground Meshes for Clocking and Computing Circuit Components

This paper presents a new formulation and an efficientsolution of the power and ground mesh sizing problem. Weuse the key observations that (1) the drops in power andground node potentials are due not only to currents drawn bythe computing blocks, but also to those drawn by the clockbuffers, and (2) changes of circuit component delays arelinearly proportional to the power/ground IR-drops. Thisleads to a linear quantification of the timing relationsbetween the clocking and computing components in terms ofthe power/ground IR-drops. Our method removes all IR-droprelated timing violations that occur in about 2% of pathswhen grids are sized using the existing methods that satisfythe maximum IR-drop constraints. In addition, we achievesupply mesh area improvements of the order of 30% whilesimultaneously reducing the power dissipated in the circuitsby about 6.6% compared to traditional grid sizing methods.