{'fraction_non_alphanumeric': 0.034220532319391636, 'fraction_numerical': 0.01394169835234474, 'mean_word_length': 5.475409836065574, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion

A nonlinear adaptive digital calibration technique for multistage analog-to-digital converters (ADCs) is presented. The approach is derived from a replica-path scaling principle inspired by the parallel-ADC equalization architecture. The treatment of residue gain nonlinearities leads to potentially significant power savings for a simple modification of the first ADC stage. The design tradeoffs involved in this technique, particularly a band-limited interpolator employed, are discussed in detail. Computer simulations demonstrate signal-to-noise-plus-distortion-ratio and spurious-free-dynamic-range improvements from 40 to 90 dB and 45 to more than 100 dB, respectively, for a 15-bit pipelined ADC.