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Power Reduction in 4T DRAM Cell Using Low Power Topologies

In today’s world there is a high demand in the development of VLSI circuits. The designers are paying attention to designing a good performance with zero hunger circuits in terms of power. At present, to design a high speed and a low cost device is becoming a major challenge for designers. In order to enlarge the demand of VLSI, CMOS technology plays a fundamental role. Dynamic Random Access Memory is the volatile memory, which is used in wide ranges of electronic based gadget applications. In this paper, the low power techniques like sleep transistor logic and Self Voltage Controllable Logic (SCVL) are implemented. A 4T DRAM cell using these low power logics has been designed and implemented. The power has been analyzed at 90nm technology. The simulation is done using the Tanner 13.1.EDA tool.