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Compact Pipeline Hardware Architecture for Pattern Matching on Real-Time Traffic Signs Detection

This paper describes a novel compact hardware oriented algorithm and its conceptual implementation for real-time traffic signs detection system. The speed limit sign area on a grayscale video frame is detected based on a novel, simple and compact rectangle pattern matching and circle detection modules. The speed limit recognition system is divided into two-pipeline stages. The frame is scanned with multi-scan windows in parallel for each position and each scan windows is also processed in pipeline to increase throughput. It achieves 100% in detection rate.