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Simulation and Optimization of 4H-SiC DMOSFET Power Transistors

Two-dimensional device simulations of 4H-SiC DMOSFET were performed in this study. Two types of P-Well doping profiles are compared. The retrograde profile can have higher breakdown voltage as compared to the box profiles. The P-well concentration is also examined and optimized. The DMOS device can have a better avalanche behavior once the P-Well concentration is higher than 2E18 cm-3. In addition, the interfacial oxide effect on the channel mobility has also been studied. The interfacial charge density should be controlled to lower than 2E11 cm-2 so as to have a higher mobility and lower on-state resistance.