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Interconnect networks for memristor crossbar

As the down-scaling of CMOS technology reaches inherent physical device limits, major challenges arise such as reliability, power consumption, etc. Novel technologies are under investigation as an alternative for next-generation VLSI circuits. Memristor is one of the promising candidates due to its scalability, non-volatility, practically zero leakage, high integration density, etc. Several applications have been proposed for the memristor crossbar architecture; examples are neuromophic, memories and logic circuits. This paper proposes a generic and flexible interconnect network for memristor-based logic circuits within a crossbar architecture. The scheme is based on the use of reserved memristors (within the crossbar) and the execution of copy operations from and/or to the reserved memristors; it can be applied both at intra-tile as well as inter-tile level, where a tile is a basic block performing a simple logic function. To illustrate the potential of the proposed scheme, two intra-tile and one inter-tile case study are evaluated using SPICE simulation, and their incurred costs are analyzed; the case studies consist of interconnect networks for (a) a specific function within a tile (i.e., the matrix transpose), (b) generic logic functions within a tile, and (c) communication between tiles.