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An Adaptive Design of SRAM Memory Cell

SRAM arrays play vital roles as on-chip memories in SOCs. As the dimension of MOS transistors is reduced, variability of MOS transistors becomes large, so that the electrical stability of SRAM memory cell has been deteriorated. Also, gate tunneling leakage and GIDL (Gate Induced Drain Leakage) have become dominant power of the SRAM array.