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P-minus substrate guard ring modeling for the purpose of noise isolation in CMOS substrates

This paper presents a compact model for p-minus substrate guard ring (psub GR) combined with p-plus guard ring (p+ GR) in lightly doped CMOS substrates. The model can be used to predict the noise suppression performance of psub GR in terms of S-parameters, which is useful for substrate noise mitigation in mixed-signal system-on-chips. The efficiency of the model has been validated by full wave electromagnetic simulation and the characteristic of the psub GR has been described.