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Edge effects characterization in gate-all-around SOI MOSFETs

The well-known edge effect due to conduction in the parasitic edge transistor at low gate voltages takes place when the threshold voltage is lowered at the device edges. A bump in the subthreshold characteristic then appears, which is detrimental to circuit performance. Several solutions have been proposed for SOI nMOSFETs, including (a) additional heavy dose boron implant at the edges followed by diffusion, and (b) specially designed SOI transistors such as edgeless devices or H-gate MOSFETs. However, these solutions are not applicable to gate-all-around (GAA) transistors due to their particular structure and fabrication process. In GAA devices, the entire active area is surrounded by the gate oxide and the gate electrode, which renders the use of edgeless structures impossible. Moreover, an oxidation step is performed in order to round the transistor edges, and gate oxide is grown all around the Si island. These steps reduce transistor width and preclude the formation of a heavy boron doped diffusion zone at the edges. This paper presents a process solution which can be applied to GAA transistors in order to suppress the edge leakage problem. Simulated and experimental curves are presented, together with edge effect characterization by both I-V and charge pumping measurements. The charge pumping method requires the use of a body contacted device. Such a device has been realized for the GAA structure. The body contact is achieved through contacting the transistor body through the gate material. This can be realized along either one or both sides of the device.