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An analytical model for current, delay, and power analysis of submicron CMOS logic circuits

An analytical model for computing the supply current, delay, and power of a submicron CMOS inverter is presented. A modified version of the nth power law MOSFET model is proposed and used to relate the terminal voltages to the drain current in submicron transistors. By first computing definable reference points on the output voltage waveform, and then using linear approximations through these points to find the actual points of interest, the desired speed and accuracy of the inverter model are achieved. The most important part of the analysis is a three-step approach for computing the time and output voltage when the short-circuit transistor changes its mode of operation. The time and output voltage when the charging/discharging current reaches its maximum are also calculated and then used to evaluate the propagation delay and characterize the output voltage waveform. The model has been validated for both 0.8 /spl mu/m (5 V) and 0.25 /spl mu/m (2.5 V) CMOS technologies, for a wide range of inverter sizes, input transition times, and capacitive loads. It predicts the delay, peak supply current, and power dissipation to within a few percent of HSPICE or ELDO simulations based on accurate physically based MOSFET models, while offering about two orders of magnitude gain in CPU time based on a MATLAB implementation.