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Design and implementation of an SRAM layout generator

In this paper the design and implementation of an SRAM layout generator is presented. The generated memories are aimed at implementation of system on chips for DSP applications. The purpose with the generator is to increase the design efficiency and reduce the dependency on commercial memories. The generator is implemented in SKILL in order to be easily modified for more advanced processes. The current version use a standard 0.18 μm CMOS process.