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Initial Explorations of Sparse Matrix-Vector Multiplication on EMU’s Migratory Memory Side Processing

Sparse matrices are common place in modern computing and due to the rise of machine learning algorithms it has become apparent that sparse matrix operations play a large role in simulating and modeling systems. Following Amdahl’s and Moore’s Law, it is clear that simply adding more resources to a CPU will no longer result in improved performance. It is now desirable to make improvements at the architecture level of CPUs to be able to continue to scale and improve performance on key application areas. In this paper, we explore a new architecture being developed by EMU Technology that implements a distributed shared memory and the ability to migrate threads to data. We use some of the well-known sparse matrix methods to compress and solve sparse matrix-vector multiplication (SpMV) and compare the performance of the EMU system and that of a modern x86 architecture. Our results are encouraging but further investigation is required to optimize our current implementation(s) and explore other algorithms for representing sparsity.