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A Σ-Δ fractional-N frequency synthesizer in 0.18µM CMOS technology

A Σ-Δ fractional-N frequency synthesizer (FS) for UHF RFID readers is designed in 0.18μm CMOS technology. The complementary cross-coupled topology with a switched capacitor array is adopted in voltage controlled oscillator (VCO) to improve the phase noise performance. The programmable frequency divider is based on a series of divide-by-2/3 cells, in which, integrated AND-latch units are proposed to reduce the power consumption and die area, and also increase speed. A novel automatic frequency calibration (AFC) technique is also put forward, which disable the Σ-Δ modulator at the coarse tuning stage so as to increase the tuning reliability. Simulation results show that both the proposed FS can operate properly and reliably. From a single 1.8V power supply, an I/Q output clock frequency of 860MHz~960MHz, a locking time of less than 40μs, and a power consumption of 25mW are achieved.