{'fraction_non_alphanumeric': 0.02081268582755203, 'fraction_numerical': 0.0, 'mean_word_length': 5.870748299319728, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Optimization issues in combined chip and symbol level equalization for downlink WCDMA receivers

Receiver structures that have been proposed for the WCDMA downlink comprise chip level channel equalizers to restore code orthogonality and symbol level Linear Minimum Mean Square Error (LMMSE) receivers that furthermore exploit subspace structure in the signal due to unused codes. In this paper we focus on receivers for high-speed downlink communications. The combined transmission system, comprising spreading and channel filtering, is time-varying at chip rate in WCDMA systems, which makes LMMSE receivers necessarily highly time-varying. We consider the case of multicode high-rate communications (HSDPA) where interchip and intercode interference dominate. We discuss optimization issues appearing in the advantageous combination of chip-level and iterative symbol-level equalization. Furthermore, iterative symbol-level operations allow for a continuous operation between linear and nonlinear receivers.