{'fraction_non_alphanumeric': 0.021778584392014518, 'fraction_numerical': 0.009074410163339383, 'mean_word_length': 4.872340425531915, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Ultra low voltage design considerations of SOI SRAM memory cells

This paper introduces a systematic design methodology dedicated to partially depleted SOI (PD-SOI) SRAM memory cells. We have adapted the conventional design methods in order to take into account the secondary effects that are related to the PD-SOI floating body transistor. The method has been applied both to a conventional 6-transistor SRAM cell and a 4-transistor self-refresh cell we have developed. Comparisons based on simulations using a 130 nm PD-SOI technology are presented.