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Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning

Power gating is able to counter subthreshold leakage in low-power nanometer technology circuits without sacrificing performance. But mode transitions in power-gated circuits are accompanied by large inrush/discharge currents causing inductive bounce noise on the power supply and ground rails. This issue has been addressed by gradually turning on the sleep transistor; but this introduces a fixed lower bound on the delay overhead irrespective of the duration of the sleep period, and takes no account of the effects of changes in the circuit internal nodes during wake-up on the ground bounce noise. We observed the behavior of internal nodes during the sleep-to-active mode transition and identified three distinct stages. This motivates a three-step turn-on scheme and an associated compact power-gating structure that limits the current flowing through the sleep transistor only while the gated block is metastable, but quickly boosts the power supply rail when there are no short-circuit current paths in the logic. This strongly suppresses power gating noise, and also reduces wake-up time. Simulation results of 16-bit arithmetic logic units in 65-nm CMOS technology show that the proposed technique offers the advantage of a wake-up time that scales with the discharged value (during sleep) of the virtual power rail.