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Toward reliable MIS‐ and MOS‐gate structures for GaN lateral power devices

GaN power switching transistors featuring MIS‐ and MOS‐gate structures are highly preferred over the Schottky‐gate counterpart, because of suppressed gate leakage, enlarged gate swing, and more scalable threshold voltage. Nevertheless, MIS‐/MOS‐gate GaN devices are confronted with stability and reliability challenges, which arise from interface traps at the critical dielectric/III‐nitride interface, as well as bulk traps inside the gate dielectric including border traps near the critical interface. In this work, we present several key techniques toward reliable MIS‐/MOS‐gate GaN power devices, including advanced interface engineering technology, gate structure optimizations for high‐performance/stability normally‐off GaN power transistors, and long‐lifetime gate dielectric technology.