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Statistical variability in 14-nm node SOI FinFETs and its impact on corresponding 6T-SRAM cell design

This paper presents a comprehensive statistical variability study of 14-nm technology node SOI FinFET which is optimized based on extensive exploration of TCAD design space. The variability sources, including random discrete dopants, gate and fin edge roughness, and possible metal gate granularity, are simulated and examined in term of their impacts on device parameters. The impact of intrinsic parameter fluctuations on a high density SOI FinFET 6T-SRAM cell is also investigated.