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Evaluation of Temporal-Spatial Voltage Scaling for Processor- Like Reconfigurable Architectures

Supply voltage reduction leads to quadratic savings on power/energy consumption at the cost of longer execution delays. These days, this fact is largely used to convert the task idle time into power/energy gain on general-purpose and embedded processors. However, such voltage management requires often the use of extra software layers and intelligent algorithms and therefore an additional overhead for the system in terms of power and performance. In this work, we show how spatial-temporal voltage management at the instruction level can be used to optimize power/energy consumption without performance penalty in highly reconfigurable architectures.