{'fraction_non_alphanumeric': 0.019858156028368795, 'fraction_numerical': 0.006382978723404255, 'mean_word_length': 4.953586497890296, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Application of DC transfer characteristics in the elimination of redundant vectors for transient noise characterization of static CMOS circuits

Static noise analysis (SNA) has become the most adopted method for crosstalk noise analysis on multi-million gate designs. Since SNA is vectorless, there exists a need to determine the correct (worst) input vector (the combination of the states of other input pins) for every signal arc in the cell library, to perform noise immunity and noise propagation analysis. In case of tools with transistor level analysis capability, in situ identification of the worst vector is needed. In the case of gate level SNA, library data needs to be modeled appropriately. Noise data characterization amounts to more than 50% of the entire library characterization time, and hence it becomes a bottleneck to on-time library delivery and time to market. Most of the runtime is due to the large number of vectors that need to be characterized for each arc. In this paper, we present a novel method to eliminate redundant vectors and identify the worst vector for noise characterization. For each arc, we use the DC transfer characteristics to identify the worst case vector. The method has been incorporated in the cell library characterization system. From testing on 130nm, 90nm and 65nm libraries, we see that our method reduces the noise characterization effort by three times.