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AREA AND DELAY MINIMIZED PROGRAMMABLE PREFIX ARBITERS FOR ON-CHIP COMMUNICATIONS

Network-on-chip (NoC) is an effective on-chip communication technique; the core function of the crossbar schedulers used in the routers located into an NoC is arbitration which is required as and when a number of input ports of a router requests for a particular output port. The design of the arbiters is of paramount importance as the parameters like delay and area of the arbiters play a vital role in determining the performance of the NoC routers. In this paper, we present a circuit technique for the design of Programmable Prefix Arbiter (PPA) which is described in verilog and Modelsim simulator tool is used to validate the code. The study claims that average area (gate count) is reduced by 7%, propagation delay is decreased by 9% and operating frequency is increased upto 12% at the cost of 2% increase in the energy consumption in the design of PPA compared to that of the state of art Round-Robin Arbiter (RRA).