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Analogue placement using guided enumeration

In this paper a new efficient approach to the placement problem of analogue circuits is presented. In the design of analogue circuits, strong interaction between humans and automatic tools is crucial to obtain good results. Hence there is a strong need for fast algorithms to support an interactive and incremental design style. In the design process, usually many geometric constraints such as symmetry or matching requirements are introduced by the designer to obtain a placement that fulfils all electrical requirements. Most state-of-the-art analogue placement tools employ simulated annealing algorithms and map geometric constraints into the cost function of the annealing algorithm; thus they have to search the whole design space. In our approach an initial global placement is computed establishing neighbourhood relations between all modules. Afterwards the design space is reduced to placements that fulfil these neighbourhood relations and user-specified geometrical constraints. the reduced design space is fully enumerated to find the optimal solution. the implemented tool achieves typical CPU times of a few seconds for designs of about 40 modules, making it an excellent choice for an interactive design process. Two examples are presented: (i) a high-speed CMOS comparator lay-out is compared with lay-outs published in other papers and (ii) a BiCMOS bandpass amplifier lay-out that has to be embedded into a mixed-signal chip is compared with the manual lay-out of a fabricated chip. We achieved the smallest lay-out size published for the comparator while fulfilling all required constraints. For the amplifier the synthesized lay-out is very similar to the manual one and about the same size.