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Alias Table Memory Circuit For Register Renaming Unit

Register renaming unit is commonly used in most of the microprocessor designs in order to increase the average number of Instructions Per Cycle (IPC). The register renaming unit constitutes several tables, wherein Register Alias Table (RAT) streamlines the operations of register renaming principle. The RAT substitutes the logical instruction operands from the physical table or the architecture table. Thus, it provides a larger set of registers than the scope seen by the software logical set. Despite the limited attention on circuit design of register renaming, we detail the principle of register renaming operational architecture within one clock cycle without pipelining, wherein the absolute delay is considered essential in register renaming unit. Additionally, we propose in this scope a circuit architecture realization for RAT that efficiently provides high performance in reading, writing, and matching content. Mathematical circuit analysis gives detail on complete register renaming principle within one cycle and complete circuit architecture for RAT. The proposed RAT constitutes four read ports along with two ports for match content addressable check, and two write ports along with priority encoder. The RAT table cells are based on SRAM 8T-Cell pre-charge structure.