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Evaluating geometric aspects of non-series-parallel cells

Recent works demonstrate constant optimizations in the number of transistors necessary to implement some logic functions by using non-series-parallel arrangements. However, these kind of networks can produce non-dual and non-planar structures, which cannot be fully treated by some of the classical algorithms dedicated to placement. In this paper we present two methodologies to place and route non-series-parallel cells, providing useful methods to estimate area and wirelength. These methods can also be applied in series-parallel topologies. The experiments performed in this paper show an effectively optimization on non-series-parallel layouts.