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Energy recovering pipelines

Power dissipation is a pressing problem for digital semiconductor technology. One promising power-reduction approach, known as energy recovery, is to recycle the charge used to represent each bit of data from one computation to the next. In contrast, conventional approaches dissipate all of the energy required to charge each bit's capacitance upon changing the bit's logical value. 
This thesis explores fundamental energy vs. performance trade-offs by examining novel high-speed energy recovering circuits in the context of sequential computations. Since a key aspect of energy recovery is the design of a “power-clock” generator, that is, a circuit that efficiently aggregates and recycles (by translating voltage levels) the energy used to represent each bit of data, a substantial portion of this work is related to the generation of power-clock and the interaction between the energy recovering circuits and the power-clock generator. 
We propose two different approaches to energy recovery. The first approach targets sequential computations that can be partitioned into a fine-grained linear pipeline, but whose data values exhibit little temporal redundancy. This approach has been validated with a 0.5 micron CMOS test chip that contained a full-custom energy recovering dynamic multiplier along with a balanced power-clock generator. The second approach targets general sequential computations, i.e., those that are better represented by a coarse-grained pipeline, but whose data values exhibit high temporal redundancy. This approach has been validated with a 0.25 micron CMOS test chip that contained a resonant clock generator and a synthesized ASIC core which included a novel standard-cell energy-recovering flip-flop. 
This thesis demonstrates that energy recovery, when carefully matched to the requirements of the desired sequential computation, can substantially reduce power dissipation to a level well below that of conventional voltage-scaled static CMOS implementations of equal throughput. While energy recovery is not as easy to implement as conventional approaches, our work has demonstrated simple and robust solutions to most of the technique's implementation challenges. Our test-chips have validated these ideas, demonstrating correct operation at frequencies over 300MHz with efficiency of energy recovery exceeding 80%.