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Hole Mobility Model With Silicon Inversion Layer Symmetry and Stress-Dependent Piezoconductance Coefficients

A model for stress-induced effective hole mobility enhancement in ¿110¿/(001) bulk pMOSFETs is presented. The model is based on first- and second-order stress-dependent piezoconductance coefficients and considers the symmetry reduction compared to bulk silicon induced by surface scattering at the gate interface. The piezoconductance coefficients are determined by Monte Carlo (MC) device simulation for five particular stress configurations with a maximum stress level of 3 GPa. Finally, comparisons between MC simulations and the new mobility model for general stress configurations show a good agreement thus validating the new approach.