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A New Functional Delay Fau

Embedded cores cannot be tested by traditional ATPG for path delay faults. Therefore, a new ATPG for path delay faults is required in order to test embedded cores whose IPs are protected in SOC environments. We propose a new and efficient functional delay ATPG for path delay faults for embedded cores whose IP is protected. The proposed algorithm uses output Boolean functions of circuits and a pair of justified constraints for a set of paths, one constraint per time frame. Experimental results show that the new ATPG is more efficient than previous approaches for embedded cores.