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Extended Word-Line NAND Flash Memory

A NAND flash memory array having extended word-lines is proposed. Without scarifying areal density, both physical gate length and charge storage node size are increased through the word-line extension process. Simple fabrication flow is delivered and device performances in a viewpoint of the short channel effect are simulated. The effect of gate length variation on the cell threshold voltage (VTH) distribution is addressed. Programming characteristics in the inversion-type source/drain NAND flash memory are also described. Some side effects concerned with the program disturbance and cell-to-cell interference are investigated in comparison with the conventional NAND flash memory.