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A Type-II Dual-Path PLL With Reference-Spur Suppression

To eliminate the unexpected spurs introduced by the charge pump (CP) mismatch in typical dual-path phase-locked loops (DP-PLLs), a fast calibration method incorporated in a prototype type-II PLL is presented. By enlarging the turn-on time and shrinking the charging capacitor, the CP mismatch can be amplified and detected more precisely in one reference period. Synchronously, a detection-quantization-compensation loop (DQCL) is built on the original DP-PLL, and it facilitates the procedure of mismatch calibration. By monitoring and compensating the equivalent mismatch voltage in a successive approximation (SA) pattern, the CP mismatch can be calibrated within five reference periods. Fabricated in 65-nm CMOS process, a 4.9–7-GHz DP-PLL is implemented. The measured output spur is suppressed by 9.11 dB at 5.46-GHz output after the calibration circuits are active. The measured output spur levels are less than −73 dBc throughout the whole output frequency range. The overall integral jitter (10 kHz–20 MHz) is less than 550 fs.