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Simulation and characterization of inter-process interference on multithreaded and multicore architectures

As limitations on design complexity and the twin problems of power and heat limit performance gains in single-context architectures, designers have increasingly turned to multithreaded and multicore designs to achieve higher process throughput. In fact, such designs are virtually ubiquitous in the PC, server, and increasingly even in the low-power and embedded markets. When independent processes run simultaneously on such systems, the performance is dependent on the competition for shared resources. Understanding and measuring this interference has many applications throughout the design process and in optimizing the performance of implemented hardware. Unfortunately, directly measuring each combination of program behaviors is effectively impossible due to the prohibitively large number of possible combinations. Further compounding the problem is that applications rarely exhibit monolithic behavior throughout their execution and there are no limitations on the relative position of co-scheduled processes. 
This work presents a methodology for developing performance models of multithreaded and multicore architectures through a three step process. First, highly efficient and accurate sampled architectural simulation is performed through a technique called Co-Phase Guided, Small-Sample Simulation which can also be applied to single context architectures. Data from simulation is used to characterize a small subset of possible behaviors which is then used to develop mathematical models which are used to predict the behaviors of unmeasured co-phases. Finally, a mathematical model is used to determine the contribution of each possible co-phase across all possible process offsets. Together, these techniques allow extremely fast characterization of multithreaded and multicore systems which is vital during design space exploration and in analyzing real systems.