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Investigation of Comparator Architectures in 32 nm Silicon-On-Insulator(SOI) Technology

In depth analysis of the CMOS latch comparators and Threshold Modified comparators have been done in this manuscript. Comparators have been implemented in BULK and Silicon on Insulator (SOI) technology. Extensive simulations have been done using Silvaco Atlas and Tanner SPICE. The comparator circuits are designed using 32 nm technology with 0.9V supply voltage. Power dissipations and delay have been detailed for the comparator circuits for different supply voltage and the frequency. These analysis would be efficacious for the design and implementation of the ultra low power and low noise analog to digital converter (ADC).