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Analysis of Self Checking and Self Resetting Logic in CLA and CSA Circuits Using Gate Diffusion Input Technique

This paper evaluates the performance of the gate diffusion input technique (GDI) on self-checking and self-resetting logic (SRL) GDI technique of carry select adder (CSA) and carry look-ahead adder (CLA) for different word lengths. In the proposed design adapting level restoration technique eliminates conductance overlap between n-MOS and p-MOS devices. The various self-resetting logic implementations for self-correcting of carry select adder and carry look-ahead adder can detect all single stuck faults in normal operation mode. Besides, two rail encoding technique is used in carry select adder are used for multiple error detection/correction. The SRLGDI setup consists of a pair of full adders, multiplexers, two rail checking, and self-resetting logic. In this technique, the self-checking carry select adder is used for reducing area and self-resetting improves the performance of the adder. The analysis of CSA and CLA with 180nm technology is simulated by using Cadence tools. The delay reduction is 12.836% for 8-bit CLA using SRL GDI, power reduction is 27.55% for 8-bit CSA using SRL-GDI compared to the gate diffusion input technique. This GDI technique implementation saves the average energy consumption up to 31.14% in CSA and 32.83% in CLA making it suitable for power optimization in high speed VLSI systems.