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Low-Power Repeater Insertion for Global Interconnects

Repeater insertion is one of the most widely used techniques to reduce the signal propagation delay on global interconnects. The number of repeaters inserted into interconnects is expected to be enormous due to the ever-increasing chip dimension. The huge number of repeaters can take up significant silicon area and consume a lot of power. Consequently, minimization of power consumption of repeaters with timing closure constraints is a very important problem in future low-power VLSI design. 

In this dissertation, we investigate efficient schemes for low-power repeater insertion on global interconnects. We first analyze key issues on repeater library design by introducing an analytical low-power repeater insertion algorithm for uniform two-pin interconnects. Our study leads to the answer of how to design a compact repeater library for low-power in early design stages. We then discuss several low-power repeater insertion schemes under given timing constraints. These schemes achieve a better trade-off between solution quality and runtime than previously proposed approaches. To handle the signal integrity problem while performing repeater insertion, we next present a novel low-power repeater insertion scheme under both timing and signal slew rate constraints. The proposed scheme is able to capture both delay and slew rate information, resulting in high quality interconnect designs. Besides the repeater insertion algorithms for given interconnects, we also describe a simple yet effective power macromodel for global interconnects with the consideration of low-power repeater insertion. By incorporating the macromodel into a macrocell placement tool, we have achieved simultaneous minimization of timing violations and power dissipation.