{'fraction_non_alphanumeric': 0.02476780185758514, 'fraction_numerical': 0.0, 'mean_word_length': 4.987654320987654, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
SEVA: A Soft-Error- and Variation-Aware Cache Architecture

As SRAM devices are scaled down, the number of variation-induced defective memory cells increases rapidly. Combination of ECC, particularly SECDED, with a redundancy technique can effectively tolerate a high number of defects. While SECDED can repair a defective cell in a block, the block becomes vulnerable to soft errors. This paper proposes SEVA, an original soft-error- and variation-aware cache architecture. SEVA exploits SECDED to tolerate variation-induced defects while preserving high resilience against soft errors. Information about the defectiveness and data dirtiness is maintained for each SECDED block. SEVA allows only the clean data to be stored in defective (but still usable) blocks of a cache. An error occurring in a defective block can be detected and the correct data can be obtained from the lower level of the memory hierarchy. SEVA improves yield and reliability with low overheads