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Novel method for optimizing lithography exposure conditions using full-chip post-OPC simulation

At 65 nm and below, full-chip verification of OPC is done for nominal dose and focus, as well as for process corners representing a two-to-three sigma deviation from the manufacturing setpoints. Such an approach interrogates the intersection of design layout with process variation to elucidate specific locations which will tend to be yield-limiting in manufacturing. With vanishingly small margins between allowable process windows and real in-fab variability, it is of utmost importance to optimize the critical exposure parameters such as projection optic numerical aperture, illumination source mode and sigma, and source polarization. The traditional approach to optimizing these exposure conditions has involved selecting representative feature test patterns (such as 1D lines at multiple pitches, or memory cells), placing simulation cutlines across selected locations, establishing allowable CD tolerances, and calculating overlapping process windows for all cutlines of interest. Such approaches are to first order effective in coarse tuning exposure conditions, but underutilize the rich information content which is available from today's rapid large-area post-OPC simulation engines. We report here on the use of full-chip post-OPC simulation and error checking in conjunction with illumination optimization tooling to provide a more thorough and versatile statistical analysis capability. It is shown that the new method proposed here results in a more robust process window than that which would be obtained by the conditions selected using the traditional optimization method.