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A Dependable and Power-Efficient NoC Architecture

In this paper, we introduce a novel flow control and microarchitecture design to handle soft errors in Networkson-Chip (NoCs). In this approach, the impact of transient failures on the reliability of on-chip interconnects has been examined and an inclusive recovery solution is presented. The importance of this study is to explore both link-level and intra-router errors; it also presents an efficient mechanism to tolerate such errors while keeping power, latency, and area overhead at a minimum. In the proposed scheme, both error correction and retransmission mechanisms are triggered while the run-time scheduling scheme is applied to optimize these issues. Further, the suggested router has been implemented on Xilinx Virtex-5 FPGA family. The experimental results captured by SPLASH-2 benchmark suite reveals that in comparison with the conventional NoC router, the proposed router takes 19% and 39% reduction in latency and energy, respectively besides 5.5% area overhead. Keywords— Network-on-Chip; Reliability; Soft Error Handling; Link level error; Intra-router error