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Computing bounds on dynamic power using fast zero-delay logic simulation

To consider process variation, we model gates with given lower and upper bounds on delays. For given input vectors, we first find logic transitions using zero-delay simulation. Our algorithms then determine the ambiguity (transient) interval, and maximum and minimum numbers for possible transitions. Computing these for all gates requires a linear-time analysis of each vector-pair. Weighting with node capacitances estimates lower and upper bounds on dynamic power. Results compare favorably with power analysis using Monte Carlo simulation, which requires significantly more computing resources. Bounded variations for node capacitances and leakage, not used in this work, are suggested for future investigation.