{'fraction_non_alphanumeric': 0.046762589928057555, 'fraction_numerical': 0.014388489208633094, 'mean_word_length': 5.288135593220339, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A ultra-fast load regulation capacitor-free LDO with advanced capacitive-coupling feedforward compensation

A low-power, capacitor-free low-dropout regulator (LDO) with Pseudo-Input stage feedforward compensation (PISFFC) is proposed in this paper. This novel FFC technique, employing the method of capacitive-coupling to provide large dynamic current for driving power transistor, is highly integrated, widely applicable and can provide ultra-fast load transient response. Compared to conventional slew rate enhancement(SRE) technique, the proposed technique is power-saving and can work at lower supply voltage. Moreover, with an additional left-half plane (LHP) zero generated by PISFFC, frequency compensation can be simpler and the unity-gain-bandwidth (UGB) can be wider. A 50-mA LDO with a 0.2-nF on-chip capacitor employed the proposed PISFFC has been implemented and simulated in a 0.13µm CMOS process. Simulation results show that the LDO got low quiescent current(17µA), low-voltage operation ability(1.5V) and greatly improved transient response(output dips less than 170-mV in 0.1µs Switching time).