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Hardware architecture of an Internet Protocol Version 6 processor

This paper presents the architecture of an Internet Protocol Version 6 processor for FPGA-based data processing and acquisition applications. Design choices and limitations are discussed together with a thorough simulation and verification methodology. The processor is demonstrated to frame and parse UDP over IPv6 traffic at 1Gb/s line-speed on a Virtex 5 FPGA, outperforming a reference soft-processor solution for UDP over IPv4. RTL-simulations show that 10Gb/s operation is attainable with the same architecture.