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Full Version: Data Packing
We are trying to setup data packing for an application and have the following configurations, using firmware version

Setup 1 for data packing (step 1 of motor test/commission window shows Adc0 responding as expected, but Adc1 is fixed at -16711936 which suggests the data is being packed but not interpreted correctly):
PackOutData = 1
PackInData = 2
PhaseCtrl = 1

Setup 2 for data packing (same result as above):
PackOutData = 1
PackInData = 3
PhaseCtrl = 1

Setup for unpacked data (works as expected):
PackOutData = 0
PackInData = 0
PhaseCtrl = 4

We may be able to proceed using unpacked data, however if someone can point out any config settings that may have been missed it would be much appreciated.

If the current feedback registers are "packed", only the high 16 bits of each 32-bit source register are packed into the single 32-bit resulting register.

This is enough to get the current feedback data itself back to the CPU, but many direct PWM drives, including the Power Brick drives, use multiple lower bits as important status information. Trying to pack the data in these drives typically will not work due to the loss of these status bits.
PackInData = 3 will unpack the AdcEnc[k] registers, which may matter if you have a sinusoidal encoder or resolver.
Thinking about this again, the answer is simple.

The whole point of "packing" the two phases of current feedback data is to combine them into a single hardware register so the processor only needs to access one of these registers each cycle. This saves about 100 nanoseconds each cycle.

So the packing operation copies the data from the 2nd phase into the low 16 bits of AdcAmp[0] INSTEAD OF the high bits of AdcAmp[1].

When the software is told to use packed data, the processor reads ONLY the 32-bit data in AdcAmp[0] and splits it into two 16-bit software variables.

The fact that AdcAmp[1] does not contain the data from the 2nd phase is to be expected in this mode, and does not affect operation.