US Patent No. 10,657,303


Patent No. 10,657,303
Issue Date May 19, 2020
Title Circuit Encoding Method And Circuit Structure Recognition Method
Inventorship Yun-Jing Lin, Yilan County (TW)
Meng-Jung Lee, Taoyuan (TW)
Yu-Lan Lo, Hsinchu County (TW)
Shu-Yi Kao, Hsinchu County (TW)
Chien-Nan Liu, Hsinchu County (TW)
Yu-Kang Lou, Taichung (TW)
Ching-Ho Lin, Tainan (TW)

Claim of US Patent No. 10,657,303

1. A circuit structure recognition method, applied to a component connection description file that corresponds to a circuit and records a plurality of connections of a plurality of transistors in the circuit, the method comprising:generating a transistor signature for each transistor, wherein the transistor signature is associated with the connections of each transistor;
dividing the circuit into a plurality of transistor groups according to a plurality of electrical connections of the drains or sources of the transistors;
generating a group signature for each transistor group according to the transistor signatures of the transistors in each transistor group;
comparing the group signatures with a predetermined group signature; and
when a target group signature of the group signatures is the same as the predetermined group signature, recognizing a target transistor group corresponding to the target group signature as a predetermined circuit sub block cell corresponding to the predetermined group signature;
wherein the circuit is coupled to a voltage source and a reference voltage, and the step of generating the transistor signature for each transistor comprises:
adding a first value to a terminal value of a terminal of a target transistor among the transistors when the terminal is electrically connected to one of the voltage source and the reference voltage; and
adding a second value to the terminal value of the terminal of the target transistor when the terminal is electrically connected to a terminal other than the voltage source and the reference voltage;
wherein the transistor signature of the target transistor is a set of a plurality of terminal values of the target transistor.