Arbitrate-and-move primitives for high throughput on-chip interconnection networks

TitleArbitrate-and-move primitives for high throughput on-chip interconnection networks
Publication TypeConference Papers
Year of Publication2004
AuthorsBalkan AO, Qu G, Vishkin U
Conference NameCircuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Date Published2004/05//
Keywords8, arbiter, arbitrate-and-move, architecture;, asynchronous, balanced, binary, circuit, circuit;, circuits;, consumption;, data, explicit, interconnection, interconnections;, leaf, mesh-of-trees, multi-threading;, Multithreading, n-leaf, network;, pipeline, pipelined, power, primitive, processing;, reduced, simulation;, structures;, synchronous, synchrony, system-on-chip;, tree, tree;

An n-leaf pipelined balanced binary tree is used for arbitration of order and movement of data from n input ports to one output port. A novel arbitrate-and-move primitive circuit for every node of the tree, which is based on a concept of reduced synchrony that benefits from attractive features of both asynchronous and synchronous designs, is presented. The design objective of the pipelined binary tree is to provide a key building block in a high-throughput mesh-of-trees interconnection network for Explicit Multi Threading (XMT) architecture, a recently introduced parallel computation framework. The proposed reduced synchrony circuit was compared with asynchronous and synchronous designs of arbitrate-and-move primitives. Simulations with 0.18 mu;m technology show that compared to an asynchronous design, the proposed reduced synchrony implementation achieves a higher throughput, up to 2 Giga-Requests per second on an 8-leaf binary tree. Our circuit also consumes less power than the synchronous design, and requires less silicon area than both the synchronous and asynchronous designs.