8-Bit AVR® General Purpose Registers

The AVR® register file structure is optimized for the AVR Enhanced Reduced Instruction Set Computer (RISC) instruction set. In order to achieve the required performance and flexibility, the following I/O schemes are supported by the register file:

  • One 8-bit output operand and one 8-bit result input.
  • Two 8-bit output operands and one 8-bit result input.
  • Two 8-bit output operands and one 16-bit result input.
  • One 16-bit output operand and one 16-bit result input.

AVR CPU General Purpose Working Registers


Most of the instructions operating on the register file have direct access to all registers and most of them are single cycle instructions. Each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.

The X-register, Y-register, and Z-register

Registers R26 through R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers (X, Y, and Z) are defined as described in the figure.

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