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FPGA Implementation of Mixed Robust Chaos-based Digital Color Image Watermarking

In this article, a hardware implementation of an invisible watermarking system has been proposed using Cyclone IV-E ’EP4CE115F29C7’ FPGA board of ALTERA company. Algorithms have been applied on digital color images using Discrete Wavelet Transform (DWT) for the decomposition and Rössler Chaotic Model (RCM) and Genesio-Tesi Chaotic Model (G-TCM) for the watermark encryption. The security of the implementation has been further increased by comparing image encryption using C-Eclipse software-generated best performing chaotic model outputs with VHDL in Quartus hardware generated Intellectual Property (IP) core ones. The experimental setup includes Video Graphics Array (VGA) monitor for different images display for the experimental validation. Implementation major performances of imperceptibility, robustness, resources consumption, and speed are analyzed and interpreted.