{'fraction_non_alphanumeric': 0.010089020771513354, 'fraction_numerical': 0.002373887240356083, 'mean_word_length': 5.4106463878327, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Experimental validation of a thermal model used to predict the image placement error of a scanned EUVL reticle

Lithographic masks must maintain dimensional stability during exposure in a lithographic tool to minimize subsequent overlay errors. In extreme ultraviolet lithography (EUVL), multilayer coatings are deposited on a mask substrate to make the mask surface reflective at EUV wavelengths. About 40% of the incident EUV light is absorbed by the multilayer coating which leads to a temperature rise. The choice of mask substrate material and absorber affects the magnitude of thermal distortion. Finite element modeling has been used to investigate potential mask materials and to explore the efficiency of various thermal management strategies. An experimental program was conducted to validate the thermal models used to predict the performance of EUV reticles. The experiments closely resembled actual conditions expected within the EUV tool. A reticle instrumented with temperature sensors was mounted on a scanning stage with an electrostatic chuck. An actively cooled isolation plate was mounted in front of the reticle for thermal management. Experimental power levels at the reticle corresponding to production throughput levels were utilized in the experiments. Both silicon and low expansion glass reticles were tested. Temperatures were measured a several locations on the reticle and tracked over time as the illuminated reticle was scanned. The experimental results coupled with the predictive modeling capability validates that the assertion that the use of a low expansion glass will satisfy image placement error requirements down to the 30 nm lithographic node.