{'fraction_non_alphanumeric': 0.02262443438914027, 'fraction_numerical': 0.0009049773755656109, 'mean_word_length': 5.544378698224852, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Accuracy enhancement in imaging-based overlay metrology by optimizing measurement conditions per layer

On product overlay (OPO) challenges continue to be yield limiters for most advanced technology nodes, requiring new and innovative metrology solutions. In this paper we will cover an approach to boost accuracy and robustness to process variation in imaging-based overlay (IBO) metrology by leveraging optimized measurement conditions per alignment layer. Results apply to both DUV and EUV lithography for advanced Logic, DRAM, 3D NAND and emerging memory devices. Such an approach fuses multi-signal information including Color Per Layer (CPL) and focus per layer. This approach with supporting algorithms strives to identify and address sources of measurement inaccuracy to enable tight OPO, improve accuracy stability and reduce overlay (OVL) residual error within the wafer and across lots. In this paper, we will present a theoretical overview, supporting simulations and measured data for multiple technology segments. Lastly, a discussion about next steps and future development will take place.