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Stochastic wire length sampling for cycle time estimation

Cycle time models perform an a-priori calculation of local signal delays by estimating the lengths of wires connecting different levels of synchronously clocked logic elements. Typically, a signal will have to pass through approximately 15-25 layers of logic during a single clock cycle and it is has been assumed that this number is sufficiently large to allow average wire lengths to be used. This paper investigates the accuracy of this mean value assumption by comparing cycle times calculating using average wire lengths with cycle times calculated using wires sampled from an estimate of the wire length distribution in each wiring layer. The sampling algorithm provides a more accurate calculation of the cycle time and also an estimate of its variation due to the inherently stochastic nature of the layout process. Results for a benchmark netlist, implemented in 0.25 μm technology, indicate that for a logic depth of 25 the mean value assumption is satisfactory and that clock rate has a standard deviation of approximately 5% of this mean value due to the inherently stochastic nature of the layout process.