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Re-using Refresh for Self-Testing DRAMs

This paper proposes a Built-In-Self test technique that utilizes refresh circuit to perform functional tests on DRAMs. The refresh re-use technique overcomes the requirement of additional Design-For-Testability hardware as tests are performed via the on-chip refresh circuit. Moreover, to perform test read followed by test write operations on a DRAM, each read operation gets completed within the refresh operation of the DRAM itself, avoiding separate test read cycles. As a result, the entire time between two refresh cycles is allowed for write operation. The increase in write cycle time is utilized in performing power aware test of a number of DRAM cores embedded in SoCs. Analytic predictions indicate that the refresh re-use technique when applied for testing a number of DRAMs, allows parallel write operation on a larger number of DRAMs within a given test power budget as compared to normal BIST approaches. Experimental results for the BIST architecture proposed in the paper indicate real estate benefits in comparison to other reported techniques.