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Processing and storage models for mpeg-2 main level and high level video decoding: a block-level pipeline approach

A novel MPEG-2 video processing model, termed Block-Level-Pipeline (BLP) processing scheme, is introduced. Under BLP control, not only does each processing unit process video data on a block-by-block basis in a video decoder, but also accesses external frame memory for motion compensation on a block-by-block basis. Thus, the data bus width requirement and the associated internal buffer sizes can be minimized because the BLP processing model can evenly distribute data bus traffic in time. Besides providing the compact design of data bus and internal buffers, the BLP scheme also can simplify the architecture design of each processing unit because their computation load can be relieved on this block-by-block basis. The description of the BLP design methodology is complete and precise because it takes processing model, resource management, and process management into account. This methodology can provide valuable estimations for system requirements in the early design stages of MPEG-2 products. 
An efficient interlacing frame memory storage organization and a deterministic fairness-priority bus scheduling scheme are also presented. This simple storing pattern can efficiently lower the probability of occurrence of page-break when accessing the external frame memory. Reducing DRAM access latencies is an important issue in a limited bandwidth system design. Unlike other real-time systems, the bus scheduler can be simplified to a deterministic and fairness-priority approach due to only one block of data being conveyed on the bus at one time. With this short-duration data transfer approach, a complicated bus scheduler to prevent starvation conditions is not needed. 
Based on these work, two designs of MPEG-2 video decoders for DVD and HDTV applications are demonstrated collectively in this dissertation.