{'fraction_non_alphanumeric': 0.009548611111111112, 'fraction_numerical': 0.0, 'mean_word_length': 5.742690058479532, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 1, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Development of a Neuromorphic Circuit in Reconfigurable Technology for the Simulation of Synapses

In last decades, neuromorphic circuits have received widespread attention across various scientific fields. Such circuits mathematically model the behaviour of biological neurons, synapses as well as their interaction. This work implements a neuromorphic synapse on an FPGA board and it improves previously proposed synapses in terms of performance and synchronization to novel neuron implementations. The proposed architecture is designed with the goal of being compatible with neuromorphic neurons based on the mathematical equations of the Izhikevich neuron model. The implementation consists of two computation cores; one core is responsible for computing the update of currents and the second core is computing the exponential decays of currents. Compared to similar neuromorphic synapses, the proposed retains low complexity and can calculate the needed synaptic currents of the connected neurons quickly and reliably. The speed of computation achieved by the parallel execution of instructions indicates that the system can function in real time.