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Advances in process overlay: ATHENA alignment system performance on critical process layers

The continuing reduction of IC device dimensions puts stringent demands on the corresponding overlay performance. As part of the total overlay budget, the effects of the different process parameters need to be characterized and well understood. In a joint development program between IMEC and ASML, the robustness of different alignment strategies to process parameters has been evaluated using the ATHENA alignment system. This paper looks at both Front-end (Shallow Trench Isolation) and Back-end (W-CMP and copper dual damascene) processing. To investigate the effect of STI processing on alignment marks in Front-end processing an extensive evaluation has been performed in which both mark design and process parameters have been varied. The robustness to typical long term process variation at the STI CMP step in a production environment has also been evaluated. To improve the robustness of alignment marks in Back-end processing, new mark designs have been evaluated. These designs have been evaluated for two different processes. The first uses traditional W-CMP and sputtered aluminum. The second uses copper dual damascene, with layer stacks consisting of both conventional and low-k dielectric materials. This knowledge will be used to generate alignment strategies for future technology nodes.