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Redundancy evaluation process of processor components for permanent fault compensation

This paper presents a scalable hardware architecture for permanent fault compensation in arbitrary processor components. The utilization of this architecture is independent from the fault case and is therefore suitable for fault compensation after production as well as in the field. Through the application of this architecture, based on active hardware redundancy, a gain in reliability for a specified mission time is possible, while functionality is not degraded. System modeling in this paper enables efficiency calculations for the presented architecture considering the additional hardware for redundancy and their administrative components. Therefore an efficient selection process for processor components and their amount of redundancy is possible. Consequently, the optimal amount of redundancy for an existing system and an objective in reliability to achieve can be calculated and is furthermore available early in the design process. Beyond describing structure as well as functionality of the architecture this paper shows that the integration in existing design processes with usual methods and tools is possible. The used system model, which realizes the redundancy selection process, is described as well. Finally, an application example is used to exhibit the practicability of the presented approach. The resulting efficiency and the required costs of this approach for the chosen example are discussed.