{'fraction_non_alphanumeric': 0.018556701030927835, 'fraction_numerical': 0.010996563573883162, 'mean_word_length': 4.991769547325103, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Reliable 4 million micro bumps at 7.6-um pitch interconnection technology for 3D stacked 16 million pixel image sensor

Our 3D stacked CMOS image sensor (CIS) has an ideal global shutter function with 16 million pixels and 4 million micro-bump interconnections placed at a 7.6-εm pitch between two silicon substrates, achieving interconnections with very low resistance. We confirmed the reliability of our 3D stacked interconnection technology by conducting reliability tests, which included heat cycle tests and high temperature and high humidity tests. The interconnections in our image sensor are comprised of 4 million micro bumps per chip. No increase in the number of failed interconnections or in micro-bump interconnection resistance was observed. For the heat cycle tests, our CIS is designed to have two test modes to detect failed interconnections by scanning all 4 million micro-bump interconnections in a short period. In the high temperature and high humidity tests, we tested the reliability of the interconnections by using test element group (TEG) chips to monitor the resistance precisely. We evaluated the effects of wafer bonding and the micro bumps on a MOS transistor with the TEGs, comparing two types of structures, one with micro bumps and one without, located under an nMOS transistor, and no difference in Vth among them was observed. These results prove that our 3D technology is reliable enough to be applied to our products.