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Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits

New cost-effective heuristics for the generation of small test sets are introduced, and heuristics proposed previously are enhanced. An improved procedure is also proposed for computing independent fault sets which are used to selecet target faults in test generation. The procedure results in large lower bounds on the minimum test set size. Experimental results of test generation demonstrate the effectiveness of the heuristics.