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Debug methodology for arithmetic circuits on FPGAs

Field programmable gate arrays (FPGAs) have been widely used to realize rapid prototyping for not only control units but also arithmetic circuits. As VLSI design becomes larger and takes up much longer time, verification and debugging of logic design become the dominating part of total design period. FPGA is relatively useful in such case due to its rapid implementation. However, circuit performances are very sensitive to layout designs. Therefore minimal change of circuit structures is important. In this paper, we give a debug methodology targeting arithmetic circuits which modifies circuits locally and speeds up the total time for redesign as a result. To complete debugging, we analyze circuits, extract the erroneous parts, and replace by correct circuits.