{'fraction_non_alphanumeric': 0.015103338632750398, 'fraction_numerical': 0.00397456279809221, 'mean_word_length': 5.626315789473685, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Deep Learning Pulsed-based Convolutional Neuroprocessor Architecture on FPGAs

The biological human brain works with spiking neural networks which computational complexity is simple, compensated by the high density connection between neurons. However, most of our research in artificial neural networks is based on simplified models that need many real values processing elements of complex computing which require too much silicon space, energy and slow learning convergence. Therefore, in this brief article, it is presented a proposal for a fully digital architecture on FPGAs optimized for a highly dense intersynaptic connection on an event-based quantized Sigma-Delta pulse coding for deep Convolutional Neural Networks. This article presents early results of an approach of neuromorphic hardware design for information or pixel luminosity changes coded in time, using Sigma-Delta modulation, the design of a Pulsed Arithmetic-Logic Unit for bitstream operations with quantized weights reducing memory, from 32 bits in floating point representation, down to 1 bit. This 32x memory reduction and binary operation cells in a systolic architectures makes the integration of deep learning models feasible for embedded design like smart cameras using FPGAs.