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Effect of Back-Etching on Residual Stress in Lead Titanate Thin Films on Si Wafer

This paper forcuses on the effect of back-etching on the residual stress in lead titanate (PT) thin film. The PT thin films were deposited by a chemical solution deposition (CSD) on a Pt/Ti/SiO2/Si substrate with different back-etching depth. The part of the Si substrates of 500 µm thickness was etched from back side (back-etching) with a wet etching process. The depth of the back-etching was controlled by changing the etching time in the range from 481.5 µm to 250 µm (residual Si; 18.5–250 µm). The residual stress in PT thin film was calculated from the phonon mode shift of raman scattering. In addition, the intrinsic dielectric constant for PT thin film was also calculated from the lattice mode frequencies. As a result, the residual stress in PT thin films abruptly increased with increasing depth of back-etching at around 300 µm (residual Si; 200 µm) and reached about 1.7 GPa.