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Partition, Packing and Clock Distribution: A New Paradigm of Physical Design

3. TIMING: We introduce a new paradigm of semi-synchronous circuits, where the constraint that every clock shall arrive at the same time to all the registers is relaxed. It is shown that a clock distribution following an appropriate clock schedule can make the period far shorter than the maximum delay between gates, which is the lower bound in conventional synchronous architecture. Ideas for timing-delay based layout are presented. Theoretical background and practical approaches with experiments are addressed.