{'fraction_non_alphanumeric': 0.01793103448275862, 'fraction_numerical': 0.005517241379310344, 'mean_word_length': 5.368421052631579, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
MAD7: a memory architecture simulator targeted at design space exploration

We introduce MAD7, a tool that rapidly simulates many-core memory architectures at a functional level. MAD7 focuses on tracking access patterns and data spatial localities rather than enforcing any precise on-chip arbitration protocols. Although not cycle accurate by nature, it provides useful insights when comparing different memory architectures under real-world workloads. Potential cache access and on-chip network usage bottlenecks can be easily spotted visually thanks to figures generated by our tool. MAD7 simulations are multi-threaded and are typically up to two orders of magnitude faster than those of a fully cycle accurate simulator.