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Improvement of the electrical safe operating area of a DMOS transistor during ESD events

Electrical safe operating area (SOA) of doublediffused vertical MOSFETs (VDMOS) in smart power ICs is investigated by simulation and experiments. The influence of the layout of VDMOS cells is analyzed. DMOS transistors with circular/oval cell layout exhibit higher ESD robustness in comparison with conventional stripe cells. The effect is related to better current distribution of circular/oval cell devices. It is also observed that appropriate source/body engineering can improve electrical SOA of a VDMOS as well.