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The impact of bit-line coupling and ground bounce on CMOS SRAM performance

In this paper, we provide an analytical framework to study the inter-cell and intra-cell bit-line coupling when it is superimposed with the ground bounce effect and show how those noises impair the performance of SRAM. The impact of noises is expressed in term of a coupling noise degradation factor and a ground bounce degradation factor. We have used analytical techniques to reduce the governing nonlinear ordinary differential equations to some manageable form and have derived very simple formulas for those degradation factors. Experiments have shown that the results obtained using the derived simple formulas are in good agreement with HSPICE simulation.