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Efficient code generation for ASIPs with different word sizes

We propose a complete methodology for extending our automatic ASIP (Architecture Specific Instruction set Processor) synthesis framework to a much wider target architecture space. In this new architecture space the width of the integer data word and of any hardware resource data path is user-definable and application specific. This methodology, developed on the basis of a retargetable C compiler (the SUIF compiler), requires the definition of a new intermediate format and a complete set of non-ambiguous rules determining the bit precision of each integer operation depending on the size of its operands. We also assess the implementation requirements and the complexity increases of the scheduler and the hardware template. Examples illustrate the methodology.