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An asymmetric dual-channel reconfigurable receiver for GNSS in 180nm CMOS

A fully integrated dual-channel reconfigurable receiver supporting all the GNSS (GPS, Compass, GLONASS, Galileo) signals in 180nm CMOS is presented. The two channels share the frequency synthesizer and RF front-end circuits, but employ separate IF strips to support simultaneous dual-constellation reception. In order to save the power of digital baseband, one of the two IF strips can be configured to a dual-conversion mode, which lowers the highest signal frequency and thus the sampling rate. The two asymmetric channels are designed with different bandwidths, covering from 2.2MHz to 20MHz for both civil and high precision applications. Besides, I/Q mismatch calibration is introduced into each down-conversion to improve the image rejection ratio (IRR). The highly integrated receiver also integrates on-chip LDOs, crystal oscillator, AFC, AGC and DCOC modules. Thanks to the flexible frequency plan and scalable IF circuits, the typical dual-channel power consumption can be reduced to 45mW. The receiver finally achieves 2.5dB noise figure, 40dB minimum IRR, 55dB dynamic range with 1dB gain steps and -57dBm input referred in-band 1dB compression point. The result of collaboration with digital baseband shows that the chip achieves positioning with >40dB carrier to noise ratio (CNR).