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Development of thin film dielectric embedded 3D stacked package

In this paper, a process for embedding and interconnecting three dimensional (3D) thin chips stacked in multilayer dielectric at wafer level is presented. Chips of different dimensions are thinned to 30 μm thickness using conventional back-grinding and singulated by dicing. Thin chips of different dimensions were then stacked onto a silicon carrier and embedded in multilayer of pre-formed photo-dielectric film using a vacuum lamination process. Photo-lithography process was used to develop the micro-vias in the dielectric film and thin film metallization is used to form interconnection between the vertically stacked chips. Under bump metallization is processed on the fan-out region of the thin film metallization lines for board level connectivity. Finally, the silicon carrier is removed to release the embedded 3D stacked package. The embedded 3D stacked package fabricated has a thickness of 110 μm and electrical measurements shows good electrical connectivity between the 2 chips stacked and the fan-out metallization lines.