{'fraction_non_alphanumeric': 0.020833333333333332, 'fraction_numerical': 0.010416666666666666, 'mean_word_length': 5.1210191082802545, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
The effect of elevated temperature on digital single event transient pulse widths in a bulk CMOS technology

Combinational logic soft errors are expected to be the dominant reliability issue for advanced technologies. One of the major factors affecting the soft-error rates is single-event transient (SET) pulse widths. The SET pulse widths, which are controlled by drift, diffusion, and parasitic bipolar transistor parameters, are a strong function of operating temperature. In this work, heavy-ion induced SET pulse widths are reported at temperatures ranging from 25° to 100° C with an autonomous SET capture circuit. Experimental and simulation results in a 90nm bulk CMOS technology indicate an increase as high as 37% in average SET pulse width with increasing operating temperature, with some pulses almost 2 ns long at higher temperatures. The increase in the SET pulse width can be explained by the dependence of bipolar amplification on temperature.