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A method for efficient NoC test scheduling using deterministic routing

Network-on-Chip (NoC) is an on-chip communication methodology that has been proposed as an alternative to bus-based communication in order to cope with the increased complexity in embedded designs. This paper presents a method for NoCs test scheduling using simulated annealing. The method uses a deterministic routing algorithm that minimizes test time while avoiding blocking. The method is implemented and various benchmarks are attempted.