{'fraction_non_alphanumeric': 0.016886930983847283, 'fraction_numerical': 0.0, 'mean_word_length': 5.459715639810427, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Optimization of reconfigurable multi-core system-on-chips for multi-standard applications

Today there is an increasing need for high performance chips that can provide very low power consumption, yet can operate over a number of application domains. For example chips operating a number of telecommunication standards depending on which country the device is in or playing a video format depending on different player formats, etc. For this reason, there is an urgent need for a design tool which aids design engineers to design such complex system on chip devices rapidly in order to satisfy the fast time to market demand. This paper presents a new framework to enable the design of flexible systems by incorporating different range of reconfigurability in an embedded platform within an SoC design automatically. The SoC design automation involves identifying the best architectural features for the SoC platform, the configuration setting of reconfigurable cores, the type of interconnection schemes, their associated parameters such as data bandwidth, and placement of embedded cores in the communication infrastructures. For this optimization problem, a two-stage multi-objective optimization algorithm is presented. A multi-standard wireless telecommunication protocol is used to demonstrate our optimized designs in terms of area, power and performance.