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A CAD Tool for Generation of Synthesizable and Scalable Square of Binary Numbers

A new method for generating a square of a signed binary number is given. The method is shown to outperform other methods found in literature. Results of comparison with other methods through direct synthesis using FPGA is given. Methods to optimize the architecture in terms of delay, area, power or any combination of these is presented. A C++ program is written that generates VHDL code for any given binary number. A variety of scalable, optimized and portable output is possible by selecting the optimization criteria as delay, power or area.