{'fraction_non_alphanumeric': 0.0297029702970297, 'fraction_numerical': 0.011001100110011002, 'mean_word_length': 4.796178343949045, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs

Low-frequency noise (LFN) has been investigated in tri-gate (TG) Si nanowire (NW) FET. We have carefully measured and analyzed LFN for gate length down to 40 nm and cross-section width down to 10 nm. Drain current noise spectral density has been measured in linear region from weak to strong inversion of transistor operation. In particular, we have shown that the LFN behavior is in good agreement with carrier number fluctuations with correlated mobility fluctuations model in ultra-scaled TGNW FETs. We did not observe large contribution due to surface orientation difference between (100) top and (110) side-wall surfaces of TGNW. Moreover, the extracted oxide trap density is roughly the same for reference wide devices and TGNW FETs without significant impact of channel area downscaling and geometry.