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Toward In-System Monitoring of OpenCL-Based Designs on FPGA

This paper presents a new in-system circuit for monitoring and profiling OpenCL-based designs on FPGA. This circuit opens the door for improved monitoring of OpenCL-based FPGA accelerators. The monitoring approach allows designers to identify unexpected performance bottlenecks such as pipeline stalls and initiation interval in OpenCL loops. The proposed monitor enhances observability into OpenCL-based accelerators by capturing high-level hardware events and timing information at FPGA-clock accuracy. Any event or variable in an OpenCL kernel can be observed by instantiating monitor circuits specified in OpenCL. To our knowledge, it is the first FPGA clock-cycle accurate monitor that can select not only the variables, but also the data inputs to be monitored in such variables. To validate the proposed in-system monitoring circuit, the Arria10 FPGA and Intel SDK were used for the OpenCL tool-chain. The reported results show that the presented monitoring circuit introduces a frequency degradation that remains small for 8 tested monitors instances. These monitors use 2.3 times fewer logic resources than previously reported OpenCL monitors.