{'fraction_non_alphanumeric': 0.01405152224824356, 'fraction_numerical': 0.013466042154566744, 'mean_word_length': 4.495176848874598, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design of lightning acquisition and smart triggering using Kintex-7 FPGA and NI cRIO

In this paper, we present the approach as well as obtained results for high speed data acquisition and real time processing of lightning data on the Lightning Sensor Node. The current paper focuses on the digital implementation details on the Lightning Sensor Node. The data acquisition and processing is carried out on the Kintex-7 FPGA. The setup comprises of a cRIO-9030 chassis along with the I/O modules mounted on it and a Kintex-7 FPGA. The various data acquisition steps and the processing algorithm have been implemented on the Kintex-7 FPGA. The cRio-9030 controller is only used for handling the communication from the Controller to the PC using Ethernet. The data acquisition basically comprises of sampling using ADC at the rate of 1 MS/s using NI 9223 ADC module and GPS time stamping for relevant sample value acquired using the ADC module. The NI 9467 module is used for the GPS time stamping purpose. The sampling at such a high rate results in a lot of unwanted data being buffered and tends to increase the processing overhead. Hence, we have further implemented a smart triggering on the FPGA. The FPGA now sends a limited chunk of data in the form of a frame consisting of 35 data points along with the relevant timestamps in microseconds. The data obtained after applying the Smart Triggering algorithm is now dispatched to the cRIO controller using the FPGA to Real Time DMA FIFO. The DMA FIFO used here initiates a high speed data transfer. The cRIO is now utilized to reconstruct the timestamps and data values obtained from the FPGA and later implement the communication to the PC using Ethernet.