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A functional memory based architecture for running sorting

In real-time applications, software-level implementations of running sorting algorithms may not be able to meet the processing time requirements, particularly when the size of the running window is large. In this paper, we present a hardware running sorter based on a functional memory architecture. The proposed approach accelerates operations thus giving the new hardware the capability of completing the running sorting algorithm in log N+7 CPU cycles. Details of the architecture units are explained, and a functional description of its operation provided.