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Multi-layer masks: manufacturability considerations

Cost control of new product mask sets for the sub-100 nm technology nodes is one of the great challenges of IC manufacturing. Attempts to reduce the mask expenses include placing multiple design layers on one reticle plate (N layers per plate, NLPP). This approach cuts the cost of a full product mask set by up to N times compared to the standard one where each design layer uses a separate mask (one layer per plate, 1LPP), but is often met with resistance from Manufacturing as it limits fab throughput. The throughput reduction is due to the N-times larger number of exposures per wafer and the resulting longer tool (stepper) time. In addition, the multi-layer masks may compromise overlay and degrade alignment yield. This work helps understand manufacturing challenges, cost models, and technical issues related to the NLPP scenarios.