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Improved read voltage margins with alternative topologies for memristor-based crossbar memories

Memories based on hysteretic resistive materials are expected to have superior properties such as nonvolatility, low power consumption, as well as very high capacity. Crossbar arrays are considered very attractive for future ultimately scaled memories. In this paper, the memristor-based passive crossbar geometry is studied and a set of different topological patterns, which introduce insulating junctions within the memory array, is presented. In the worst-case reading scenario the simulations revealed significantly improved sensed voltage margins (up to > 4×) which alleviate the rigorous requirement for large and highperformance CMOS sensing circuits in passive crossbar memory systems.