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A study of hardware techniques that dynamically exploit frequent operands to reduce power consumption in integer function units

We analyze three different techniques, namely, memoing (caching results that can be reused), narrow-width operand exploitation (limiting computation to low order bytes), and byte encoding (computation performed over significant bytes) that dynamically exploit operands to lower power consumption in integer function units. Previously, estimates of power savings based on switching activity were reported. Our implementation of integer function units (CLA, array multiplier, comparator, etc.) at the VLSI level and analysis using standard integer benchmarks from the SPEC CPU2000 suite provide realistic power savings and area and delay overheads.