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A 1.35 GHz CMOS wideband frequency synthesizer for mobile communications

The design and simulation of a 1.35 GHz CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based on a wideband PLL topology with a high frequency reference, giving as result low phase noise, fast switching time, a low divider ratio and a reduction in the chip area. Besides, the use of a novel charge-pump circuit with positive feedback and current reuse allows a further reduction in both, chip area and power consumption, making the structure desirable for high-frequency low-voltage phase-locked loops.