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Design of a multi-style and multi-frequency FPGA

This paper presents an FPGA architecture capable of implementing relative timing based asynchronous designs. Modifications are made to a traditional synchronous FPGA architecture to make it asynchronous capable, while retaining its capability as a fully functional synchronous FPGA. Such a design permits multi-frequency implementations. A test FPGA fabric is developed and evaluated with the implementation of a MIPS processor. The asynchronous MIPS processor implemented on the designed FPGA provides a performance improvement of 1.7× while also providing a power improvement of 2.3× compared to the synchronous version of the MIPS implemented on a counterpart synchronous FPGA.