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An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements

Optical shrink for process migration, manufacturing process variation and dynamic voltage control leads to clock skew as well as path delay variation in a manufactured chip. Since such variations are difficult to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. The buffer delays are tuned to improve maximum operating clock frequency of a design. This however shifts the burden of finding tuning settings for individual clock buffers to the test process. In this paper, we describe a process for using Boolean tester measurements for determining the settings of the tunable buffers. The results show that frequency improvements of 10% or more are possible by appropriate setting of tunable clock buffers.