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Design and Analysis of 8-Bit Stable SRAM for Ultra Low Power Applications

SRAMs (Static Random Access Memory) speed and power consumption are the most important which leads to complex designs with the power consumption of reducing the power during the read and write operations. Exceeding leakage power becomes the major concern in CMOS which has been used for deep micron process. Whenever the supply voltage is lowered it leads to lower oxide thickness and threshold voltage. The objective of this paper is to analyze the existing leakage power techniques, where an SRAM is designed using each technique. These techniques are implemented in tanner tool in which the waveforms are analyzed. By doing so a clear idea has been taken. An array of 8×8 SRAM has been designed. This cell design is able to reduce the static power dissipation and a high reading stability is predicted. To determine schematic solutions Tanner EDA tool is used. The performance of the proposed technique is investigated in terms of area and power. The design techniques have been analyzed. Based on the results obtained, there is a decrease in static power dissipation and the stability of the memory cells also been improved.