{'fraction_non_alphanumeric': 0.02937576499388005, 'fraction_numerical': 0.008567931456548347, 'mean_word_length': 5.492063492063492, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Fully integrated PVT detection and impedance self-calibration system design

The paper presents a fully integrated PVT variation detection and on-die resistance calibration system for high-speed applications. The proposed system separately measures and compensates the MOS device resistance deviation due to process, voltage and temperature variation. Temperature detection is performed in a range of -40°C to 125°C independently from supply voltage variations. Logic block of mixed-signal system automatically starts MOS resistance calibration process when PVT variation is detected. The design is implemented in 28nm CMOS process. The presented compensation method can be used in the I/O circuits of such standards as DDR (Double Data Rate), USB (Universal Serial Bus), PCI (Peripheral Component Interconnect), etc.