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Advanced simulation of statistical variability and reliability in nano CMOS transistors

Increasing CMOS device variability has become one of the most acute problems facing the semiconductor manufacturing and design industries at, and beyond, the 45 nm technology generation. Most problematic of all is the statistical variability introduced by the discreteness of charge and granularity of matter in transistors with features already of molecular dimensions [i]. Two transistors next to each other on the chip with exactly the same geometries and strain distributions may have characteristics from each end of a wide statistical distribution. In conjunction with statistical variability [ii], negative bias temperature instability (NBTI) and/or hot carrier degradation can result in acute statistical reliability problems. It already profoundly affects SRAM design, and in logic circuits causes statistical timing problems and is increasingly leading to hard digital faults. In both cases, statistical variability restricts supply voltage scaling, adding to power dissipation problems [iii]. In this invited paper we describe recent advances in predictive physical simulation of statistical variability using drift diffusion (DD), Monte Carlo (MC) and quantum transport (QT) simulation techniques.