{'fraction_non_alphanumeric': 0.03902439024390244, 'fraction_numerical': 0.0, 'mean_word_length': 5.222222222222222, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Voltage and frequency island optimizations for many-core/networks-on-chip designs

Many-core chips interconnected by networks-on-chip (NoC) are increasingly challenged by the tight power consumption constraints. The concept of voltage and frequency island (VFI) which has been recently introduced for achieving fine-grain core-level power management fits well with an NoC design style. This paper will discuss some recent advancement of VFI optimizations for many-core/NoC designs. We will also discuss other research challenges for low-power many-core/NoC designs from an electronic system level (ESL) perspective.