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Power and Signal Integrity co-simulation via compressed macromodels of high-speed transceivers

This paper presents innovative compressed macro-models of high-speed digital transceivers for system-level Signal and Power Integrity co-simulations. These simulations assume a paramount importance for the design of modern, low-cost and highly integrated systems. An excellent accuracy and an outstanding run-time speed-up are demonstrated by applying the macromodeling methodology to a state-of-the-art I/O buffer for a low-power memory interface. Supply voltage variations and related effects on output transitions are accurately reproduced, enabling precise estimates of critical system-level timing margins.