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Achieving speedups for APL on an SSIMD parallel computer

This paper contains a summary of the results presented in [GS87]. In [GS87] the potential for speeding up APL by using an idealized non-shared memory parallel computer was investigated. APL's dyadic, reduction, and subscript operators were simulated on a 4-connected mesh SIMD parallel computer. The findings support the thesis that parallelism can speedup a majority of "typical" APL programs and not just those programs that are especially suited to parallelization. APL requires no sophisticated compilation techniques like Paraphase and PFC, because the operators in APL are inherently parallel.