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Performance Failure Prediction Using Built-In Delay Sensors in FPGAs

The objective of this paper is to propose a performance failure prediction methodology for FPGA-based designs, based on the use of a novel built-in programmable delay sensor. Digital Clock Managers (DCM) is used to fine tune the unsafe observation interval. The design procedure is described, including the constrained placement of some delay sensors. The proposed technique is particularly useful to monitor parametric Process, supply Voltage and Temperature (PVT) and aging-induced variations. It can be used during product lifetime, as a predictive delay fault detection technique, either to avoid unreliable operation, or to guarantee correct functionality with lower power consumption. The usefulness of the proposed technique is demonstrated with part of the data processor of a complex design for a medical imaging system used in PET-based mammography, configured in a Virtex-4 FPGA device (xc4vfx60-11ff1152).