{'fraction_non_alphanumeric': 0.041589648798521256, 'fraction_numerical': 0.0009242144177449168, 'mean_word_length': 4.82258064516129, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A novel ACS-feedback scheme for generic, sequential Viterbi-decoder macros

For the implementation of large constraint length, sequential Viterbi-Decoders (VD), e.g. for HDSL2 or SDSL, it is necessary to realize the Add-Compare-Select-feedback (ACS-FB) with memories. Using butterfly processor elements (BF-PE) for the ACS computation leads to memory I/O and access conflicts and as a result "ping-pong" architectures are currently implemented, which use twice as much memory than the Viterbi-Algorithm requires. This paper presents a novel path-metric buffering scheme realizing the ACS-FB. It will be proven that this technique is optimal in the sense of routability, area- and power consumption. Memory I/O- and path-metric access conflicts are completely prevented without use of wait-cycles. The introduced architecture always remains the same, regardless to the number of BF-PE and thus simplifies the ACS-unit design for sequential VD macros. Independent from the degree of parallelism only one memory is used and hence the proposed architecture is area- and power efficient.