{'fraction_non_alphanumeric': 0.020889487870619946, 'fraction_numerical': 0.0020215633423180594, 'mean_word_length': 5.239495798319328, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Analysis and implementation of data synchronization in time-interleaved ADCs system

Time-interleaved parallel technology is still the best way to implement a data acquisition system with higher sampling rate. In order to make a system of multiple analog to digital converters (ADCs) achieve an optimal performance, a large number of calibration works should be done on the parameters, such as gain, offset and time error, based on sampled data after ADCs. And it also should get correctly data sequence to store the sampled data and then to do correspondingly post-processing. However, along with the increase of sampling rate, a random reset operation of multiple ADCs system will lead to the uncertainty of data synchronous transmission and the incorrect of sampled data sequence that caused its incorrect digital post-processing. Based on an example of dual-ADC time-interleaved parallel sampling system, this paper analyzes the basic timing of sample data transmission process, and presents a calibration method of data synchronous recognition. And the guiding principles of practical engineering design are also proposed. Finally, these are tested on 20GSa/s high-speed acquisition system composed of four 5GSa/s ADCs. The results indicate that the calibration method of data synchronization and the guiding principles of practical engineering design are effective and reliable, and provide a strong support for structure of more complex high-speed time-interleaved ADCs system.