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Early Prediction of Hardware Complexity in HLL-to-HDL Translation

Early prediction of hardware complexity is essential in driving hardware/software partitioning and the automatic generation of HDL descriptions from high-level code. In fact, early prediction helps estimate the “hardware cost” of a given high-level code segment before the actual synthesis, dramatically reducing the time required for an exhaustive exploration of different design choices. Clearly, this early estimation is inherently influenced by the specific toolchain for HLL-to-HDL translation. As a consequence, suitable early prediction metrics should be studied and carefully selected for each given toolchain. In this paper, we propose a general framework for the systematic study of such metrics. Unlike some previous works, the proposed framework is not specific to a given toolchain as it lets designers plug their own synthesis tool and characterize its behaviour in order to identify the most effective metrics to be used during the design space exploration. The framework is developed on top of the LLVM compiler infrastructure along with the R statistical package used to perform regression analysis. For a specific HLL-to-HDL compiler chosen for tests, we collected extensive experimental results on a large base of benchmarks, which show interesting accuracy improvements over some related work previously presented and confirm the effectiveness of the framework in deriving a characterization of the underlying hardware compiler.