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Power Estimation for IP-Based Modules

In this paper, we propose a power estimation technique for register transfer level model of digital circuits. This technique allows to estimate the power dissipation of intellectual property (IP) components based on the statistical knowledge of their primary inputs/outputs. During power estimation procedure, the sequence of an input stream is generated using input metrics and the macromodel function is used to construct a set of functions that maps the input metrics of a macro-block to its output metrics. Then, a Monte Carlo zero delay simulation is performed and the power dissipation is predicted by a macromodel function. In experiments with IP macro-blocks, the results are effective and highly correlated, with an average error of 1.84%. Our model provides accurate power estimation