{'fraction_non_alphanumeric': 0.01808590806330068, 'fraction_numerical': 0.00452147701582517, 'mean_word_length': 5.541871921182266, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design and performance tradeoff analysis of floating point datapath in LTE downlink control channel receiver

Long Term Evolution (LTE) receiver processing involves decoding of complex valued received symbols from each antenna port to detect the codeword sent by the transmitter. The main objective of this paper is to design and implement the receiver hardware architectures for the control channels, PCFICH (Physical Control Format Indicator Channel) and PHICH (Physical Hybrid ARQ Indicator Channel) using fixed point and IEEE 754 single precision floating point arithmetic units for single input single output (SISO) configuration and validate their performance based on the signal to noise ratio (SNR) and mean square error (MSE) or the decision values for detecting the code words received. Floating point based receiver has an edge over fixed point in terms of reduced developing time, reduced complexity, higher accuracy, higher precision and tolerance to error but at the cost of increased hardware. Floating point based receivers employing folding and superscalar techniques to optimize the architectures through reduction in resource utilization are synthesized and implemented. ModelSim 6.4a is used to simulate the results while the architecture is implemented in Virtex-6 FPGA device using Xilinx-Plan Ahead tool.