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Latency improvement with traffic flow analysis in a 3D NoC under multiple faulty TSVs scenario

The third dimension is becoming an attractive solution to integrate components in a single integrated circuit. Therefore, 3D Networks-on-Chip (NoCs) are usually adopted to provide fast connections between the layers by using Through-Silicon-Vias (TSVs). However, many challenges during the 3D manufacturing phase are making the circuits more vulnerable and prone to failure. This work investigates the impact on latency in 3D NoCs under multiple faulty TSVs and it proposes a technique to ensure the connectivity of the NoC under multiple faults scenario. A fault model was proposed with four different configurations to distribute multiple faulty TSVs in the 3D NoC. Three different fault tolerant scenarios were explored: the first is the original routing algorithm called Elevated-First used to avoid faulty vertical connections. The second and third scenarios are our new designs based on the use of dynamic monitors to observe the flow through the paths, in order to be able to select best alternative paths under multiple faults. Fault injection results show that it is possible to reduce the latency impact from 1x to 10x in the best case configuration by use the proposed solutions.