{'fraction_non_alphanumeric': 0.03276353276353276, 'fraction_numerical': 0.03276353276353276, 'mean_word_length': 4.366412213740458, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Write ability enhancement techniques for L1 cache on next-generation IBM POWERTM processors

In this paper, two write ability enhancement techniques are presented for the L1 data cache on next-generation IBM POWERTM processors. Write ability is improved by 15.1% at 1.2V with VDD lowering technique for a dual-ported 6T bitcell with a beta ratio of 4. Write ability is improved by 21.6% at 1.2V by using a dual-port dual-ended transmission gate bitcell with a beta ratio of 4. These numbers reduce to 11.8% and 17.1% respectively at 0.7V. The enhancement in bitcell write ability is achieved with the inclusion of additional control logic per word, and by trading off bitcell area and leakage currents.