{'fraction_non_alphanumeric': 0.013432835820895522, 'fraction_numerical': 0.016417910447761194, 'mean_word_length': 4.5, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Bit Serial Architecture for the Two-Dimensional DCT

We present an architecture for the calculation of the Two Dimensional Discrete Cosine Transform and its Inverse that admits a high data rate. It is based on the row-column decomposition, the use of a fast algorithm, serial digit arithmetic and redundant coding. The critical path is set by the delay of a multiplexer plus a binary adder with as many digits as the width of the serial digits to be processed. We discuss its implementation for processing 8 bit 8x8 pixel blocks or 12 bit coefficients. Its implementation using standard cell 1 microm CMOS technology presents a 100MHz data rate and a core area of 42mm .