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Compact FPGA implementations of QUAD

QUAD [1] is a stream cipher whose provable security relies on the hardness of solving systems of multivariate quadratic equations. This paper explores FPGA implementations of this stream cipher and, more specifically, small area ones. The smallest of our implementations of QUAD requires only 85 slices (2961 GE) on a Virtex 4 Xilinx FPGA, which makes it not only the smallest provably secure stream cipher, but also a very good competitor among conventional stream ciphers: this implementation of QUAD's underlying PRNG results in a 68% improvement over the smallest known AES implementation on FPGA [4].