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Dual Core System-on-a-Chip Design to Support Inter-Satellite Communications

The next generation of satellites for distributed satellite missions will exploit the latest computing and wireless technologies for intersatellite connectivity. These missions enable opportunities in multiple-point sensing, greater communications capabilities and spacecraft redundancy. Requirements for processing and network capabilities have risen dramatically to meet strict needs of the end user and overcome various space disturbances and perturbations once in orbit. One such problem lies with a 'cluster' of satellites that have been deployed from the same launcher where they will be close together so ad-hoc technologies allow satellite communication. This paper addresses the hardware and software requirements for distributed computing opportunities using intersatellite connectivity. A system-on-a-chip design is proposed; including a general purpose processor core and a dedicated Java processing core to adapt and reconfigure the topology using real-time software Agent applications. This will make the network resilient to various space perturbations and ensure mission longevity. Integration of these two non-heterogeneous cores in a picosatellite technology demonstrator testbed and network topology reconfigurability procedures are also outlined.