{'fraction_non_alphanumeric': 0.01987577639751553, 'fraction_numerical': 0.014906832298136646, 'mean_word_length': 4.9010989010989015, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Direct digital frequency synthesis of low-jitter clocks

The development of communication systems in the past years has increased the necessity to synthesize very accurate clocks. For example, in Digital Television (DTV) an audio data stream must be inserted into a video data stream, which implies that we must synchronize the audio clock with the video clock. According to one digital audio standard, the audio clock frequency is 5,6448 MHz, and with the PAL digital television standard, the video clock frequency is 35.46895 MHz. In this case, the division ratio is 112896/709379. Other division ratios are required with other DTV standards such as NTSC, SECAM or HDTV, and with other digital audio standard frequencies. Direct Digital Synthesis (DDS) is a popular technique that can be used to derive the audio frequency from the video frequency used as clock. A critical component of a DDS is its phase accumulator, which controls the DDS output frequency. The limited number of bits in the phase accumulator reduces its precision and its ability to express divide ratios defined with large integers. This will produce a phase error that accumulates with time to produce a low-band jitter in the output signal, which is particularly harmful when the output clock is used for synchronization purposes. This paper reviews some circuits found in the literature, which could be used to reduce the phase error given by a phase accumulator, and it presents a new phase correction technique which can give better results in terms of jitter, and which simplify design and implementation of practical DDS circuits.