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MOSFET characterisation and its application to process control and VLSI circuit design

As the silicon fabrication industry has rapidly expanded, competition has led to smaller geometry circuits in order to maximise profit and obtain optimum performance. Device operation has to be characterised more rigorously because the tolerances on device operation are reduced and designers are constantly endeavouring to push the limits of the technology. In order to characterise MOSFETs, parameters for the SPICE level 3 model can be extracted. Although SPICE has been around for several years, commercial programs which extract parameters using numerical optimisation have only recently become available. A program, PARAMEX, has been developed to physically extract parameters which accurately simulate device operation. A thorough analysis of parameters for different geometry devices has been carried out and recommendations for, simulating devices of different sizes are provided. Of particular interest to designers is the definition of a 'worst case' parameter set and by extracting parameters from numerous sites on a single wafer. .a method for determining a 'worst case' set is proposed. Ideally if SPICE parameters are to be central to the design of integrated circuits, it would be useful to link them to specific steps in fabrication. Parameters from wafers fabricated using different processes were correlated with the process steps which had been varied and the effects on both first and second order parameters are described. The subthreshold region is of increasing importance in small geometry circuits. As fabrication processes have evolved, more implants have been made in the channel region with only limited regard to the effect on the subthreshold currents. By thoroughly analysing the subthreshold currents in transistors manufactured with different channel profiles, conclusions about the effect of channel implants on subthreshold operation and the consequences for simple circuits are set out.