{'fraction_non_alphanumeric': 0.03172737955346651, 'fraction_numerical': 0.0023501762632197414, 'mean_word_length': 5.0, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A multi-controller architecture for high-performance solid-state drives

A solid-state drive consists of controllers and NAND flash memory chips, and each chip is controlled by one controller. Since each controller is responsible for a fixed number of chips, it can't control other chips that don't belong to it. Therefore, some idle controllers can't access other chips that don't belong to them, and it will reduce system performance. In this paper, we will propose a multi-controller architecture for high-performance solid-state drives. With the design, any chip will not be restricted to any specific controller, and any idle controller can access any chip. The experimental results show that the proposed method can improve system throughput of 25% when compared with traditional solid-state drives, and the incurred overhead is also reasonable.