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Effect of Negative Back Bias on FD-SOI Device Parameters down to Cryogenic Temperature

In this work, we aim to present the effect of negative back bias on various device parameters down to cryogenic temperatures. We have performed wafer-level DC measurements on a RVT (Regular Voltage Threshold) short channel n-type and p-type ultra-thin body ultra-thin buried oxide (UTBB) FD-SOI MOSFETs with different geometries across temperatures ranging from 300K down to 10K. Our analysis shows that while the threshold voltage behavior is aligned with the theoretical expectation, the subthreshold slope behavior with back bias is counter intuitive. With this work, we are trying to address the origin of the same to contribute towards the understanding of cryogenic CMOS behavior.