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BiCMOS gate performance optimization using a unified delay model

A unified delay model is presented that predicts BiCMOS gate delay for both long- and short-channel MOSFETs, in low-level and high-level injection in the bipolar junction transistors (BJTs), for 5 V and reduced supply and over a wide range of circuit parameter variation. The model is applied to devise circuit and device design strategies to optimize gate performance at 5 V and at scaled supply voltage. The model predicts analytical expressions for an optimum BJT emitter length versus MOS gate width for which the delay is a minimum. To minimize performance degradation at reduced supply, an effective circuit strategy is to design with wide MOS devices and small-length BJTs. The crucial BJT parameters are (reduced) junction capacitance, (reduced) transit time and the gain-knee current product. For the MOSFET the saturation current must be maximized and gate length scaling is desirable as long as the saturation current increases