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Simulation support for integrated multiprocessing and memory access scheduling

Rapid advances in microelectronics technology will soon permit integration of logic and memory in billion-transistor chips. One approach is to include several simple processors and a large amount of DRAM memory on the same die. Chip multiprocessing can exploit the inherent thread-level parallelism in important commercial workloads. Furthermore integrating DRAM on the same chip bridges the gap between memory access time and processor speed. Effective scheduling of accesses to multiple DRAM banks exploits the large on-chip memory bandwidth. To study such architectures, a flexible system-level simulator has been implemented. The simulator is built on an existing framework called Quasar (Queen's Architectural Simulation ARchive). In support of this research, Quasar is enhanced to model processors with multiple outstanding memory accesses, a split-transaction bus, and multiple DRAM banks. The overhead incurred for these enhancements is small for tested applications. Our initial experimentation shows the benefit of a straightforward scheduling scheme for two numerical applications.