{'fraction_non_alphanumeric': 0.021632758176667526, 'fraction_numerical': 0.0038629925315477724, 'mean_word_length': 5.254428341384863, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 2, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Germanium MOSFETs for Nanoelectronics

It is believed that continued scaling of the conventional Si CMOS will take the industry down to the 45-nm technology node. It is also well accepted that below the 45-nm node although the conventional Si CMOS can be scaled performance gains will be sharply diminished. There are several technical issues that make proper device scaling increasingly difficult. The drive current is far from that required at the power-supply voltage of the sub-45-nm nodes. Suppressing the short-channel effect and the subthreshold leakage current requires tight control of intricate vertical and lateral channel doping profiles involving heavy doping, very shallow source/drain junctions and ultrathin gate dielectrics. Some of these approaches directly conflict with the goal of obtaining high carrier mobility, low subthreshold swing, low series resistance, and therefore large drive current and low leakage current at low operating voltage. Therefore to continue the scaling of Si CMOS in the sub-45nm regime, innovative device structures and new materials have to be created in order to continue the historic progress in integrated electronics. Ge offers several attractive physical properties over Si. In Ge, the lower electron and hole effective masses are primarily responsible, respectively, for higher electron and hole drift mobility. This property is the most advantageous over Si for deeply scaled MOSFET applications regardless of the higher Si saturation velocity. The more symmetric electron and hole mobility in Ge would not only reduce the area of p-MOSFETs, but would permit more CMOS logic gates as well. Furthermore, its lower melting point reflects a possibility to fabricate Ge MOSFETs with much lower thermal budget processes while relaxing some stringent thermal stability requirements in integrating novel materials like metal gate electrode and high-k dielectric into advanced transistors. Historically, Ge had been one of the most important semiconductors in the past as the first MOSFET and the integrated circuit were fabricated in Ge. The common surface Ge oxides (e.g. GeO and GeO2 etc.) are either water soluble or volatile, and they are easily rinsed off or sublimated during the fabrication process. For Ge to become mainstream, heterogeneous integration of crystalline Ge layers on Si, Ge surface passivation and innovative heterostructure MOSFETs to overcome BTBT leakage must be achieved. We have demonstrated growth of fully-relaxed smooth single crystal Ge layers on Si using a novel multi-step growth and hydrogen anneal process without any graded buffer SiGe layer. Surface passivation of Ge has been achieved with its native oxynitride (GeOxNy) and highpermittivity (high-k) metal oxides of Al, Zr and Hf. High mobility MOSFETs have been demonstrated in bulk Ge with high-k gate dielectrics and metal gates. However, due to their smaller bandgap and higher dielectric constant, most high mobility materials suffer from large Band-To-Band Tunneling (BTBT) leakage currents and worse short channel effects. We present novel, Si and Ge based heterostructure MOSFETs, which can significantly reduce the BTBT leakage currents while retaining high channel mobility, making them suitable for scaling into the sub-15nm regime. Through Full band Monte-Carlo, Poisson-Schrodinger and detailed BTBT simulations we show a dramatic reduction in BTBT and excellent electrostatic control of the channel, while maintaining very high drive currents in these highly scaled heterostructure DGFETs. Heterostructure MOSFETs with varying Strained-Ge or SiGe thickness, Si cap thickness and Ge percentage were fabricated on bulk Si and SOI substrates. The ultra-thin (~2nm) strained-Ge channel heterostructure MOSFETs exhibited >4X mobility enhancements over bulk Si devices and >10X BTBT reduction over surface channel strained SiGe devices.