{'fraction_non_alphanumeric': 0.025362318840579712, 'fraction_numerical': 0.0, 'mean_word_length': 5.90625, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
SdrLift: An Intermediate-Level Framework for Synthesis of Software-Defined Radio Accelerators

In this paper, we present SdrLift, a domain-specific intermediate-level compiler framework for prototyping software-defined radio (SDR) applications on a field-programmable gate array (FPGA). SdrLift facilitates development by automating synthesis of FPGA data-paths from algorithmic-level descriptions and through the integration of pre-defined Intellectual Property (IP) cores. Applications are the composition of actors which exchange data through unidirectional channels in a dataflow network. The behavior of each actor is described in an intermediate-level language that is designed around topological patterns and computational data patterns, resulting in a high-level of design abstraction. We demonstrate the capability of SdrLift by developing a representative SDR application for which SdrLift generated a synthesizable VHDL code. The results show that good performance and design flexibility can be achieved using SdrLift, while also conserving hardware resources in the subsequent implementation.