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A Noc Centric Low Overhead Multi-chip Interconnection Technology

Improving the performance of processors is one of the main tasks of high-performance processor design. It is an effective way to improve the processor's performance through high-speed inter-chip interconnection, which utilizes multiple chips to build one unified computing system with higher performance. The existing multi-chip interconnection technologies, such as CCIX, CXL and NVLink, are faced with the problems of not open protocol, high hardware overhead and difficulty to reuse with existing high-speed peripherals. Considering the limitation of current multi-chip interconnection, we adopt the network centered idea to design FT_Link open architecture, which realizes the interconnection of multiple chips in a low-cost way and enables requests to access other chip spaces transparently. FT_Link system is built on common logic layer and physical layer of the existing high-speed peripherals, making it flexible and versatile. Tests and synthesis results show that FT_ Link technology has the feature of high throughput and low latency with very small hardware overhead. Its performance bottleneck depends on the FIFO depth of the high-speed peripheral logical layer which it adopts.