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Timing and signal integrity analysis in a cell based SOI design

Partially Depleted (PD) SOI CMOS has become increasingly popular due to its performance advantages over bulk CMOS. However signal integrity analysis of SOI designs continues to be a challenging task. One of the major problems is accurate prediction of circuit behavior due to history effect associated with SOI MOS devices. Prior switching effects floating body voltage, which in turn has impact on MOS device threshold and channel current. These effects, if not accounted for can cause huge errors in predicting cell delays and glitch noise. In this paper, we step through our adopted methodology and analysis results to show how the history of possible prior switching is efficiently captured and is used in timing and SI analysis for predicting noise and delay push-out on nets. Finally we will establish that with this automation and, SOI design methodologies are simple to setup, adopt and is as stable as their bulk counterparts.