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Optimization of Hybrid CMOS Designs Using a New Energy Efficient 1 Bit Hybrid Full Adder

In this paper a novel 1 bit energy efficient hybrid adder has been introduced which can optimize performance parameters like power and delay of two CMOS hybrid full adder circuits described in this paper. The first described design is implemented with normal Complementary metal oxide semiconductor (CMOS) and second design is a hybrid model of CMOS and transmission gate logic (CMOS-TGL). The proposed model is hybridized with Complementary metal oxide semiconductor, pass transistor and modified gate diffusion input logics (CMOS-PT-MGDI) together to ensure low power and high speed. The performance parameters such as power, delay and area of 1 bit full adders was analyzed and tabulated. All the circuits were implemented using cadence virtuoso tool in 90nm technology for 1.2V supply.