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A novel design method of digital phase-locked loop applied to three-phase rectifier

The performance of phase-locked loop (PLL) severely affects the system's stability in a three-phase rectifier. Traditional methods tend to adopt the idea of single synchronous coordinate transformation, which implements the phase synchronization through controlling the q-axis voltage to zero. A novel three-phase PLL is proposed in this paper based on this idea. In order to obtain better convergence rate near zero, the input of closed-loop PLL is replaced by the ratio of q-axis voltage and d-axis voltage. The fastness and convergence of the system are further analyzed in principle. Simulation and experiment results show that proposed method can lead to better rapidity, and the phase-locked process is superior to traditional digital PLL methods.