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Just-in-time compilation for FPGA processor cores

Portability benefits have encouraged the trend of distributing applications using processor-independent instructions, a.k.a. bytecode, and executing that bytecode on an emulator running on a target processor. Transparent just-in-time (JIT) compilation of bytecode to native instructions is often used to increase application execution speed without sacrificing portability. Recent work has proposed distributing FPGA circuit applications in a SystemC bytecode to be emulated on a processor with portions possibly dynamically migrated to custom bytecode accelerator circuits or to native circuits on the FPGA. We introduce a novel JIT compiler for bytecode executing on a soft-core FPGA processor. During an iterative process of JIT compiler and emulator architecture codesign, we added JIT-aware resources on a soft-core processor's surrounding FPGA fabric, including a JIT memory, a signal queue, and an emulation memory controller — all unique to JIT compilation for FPGA processors versus traditional processors. Experiments show that regular JIT compilation achieved 3.0× average speedup over emulation, while our JIT-aware FPGA resources yielded an additional 5.2× average speedup, for a total of 15.7× average speedup, at a cost of 21% of a MicroBlaze processor core's slice usage.