{'fraction_non_alphanumeric': 0.02916160388821385, 'fraction_numerical': 0.032806804374240585, 'mean_word_length': 4.6438356164383565, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction

Feature extraction, which is one of the basic tasks for pattern recognition, has often high computational cost and large memory usage. In this work, we propose a pixel-based pipeline hardware architecture for Haar-like feature extraction, implemented in 0.18 μm CMOS technology with 1.76 mm2 core area. Pixel-input speed relies on the working frequency of the image sensor so that features are extracted in real time without on-chip image buffer and complex computational procedures. The fabricated chip consumes 4.78 mW power at 1.8 V supply voltage and 12.5 MHz frequency during 30 fps VGA video input. Furthermore, a processing time of 3.07 ms per VGA frame with power dissipation of 36.25 mW at 100 MHz frequency is possible.