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Physical optimization for FPGAs using post-placement topology rewriting

Due to poor correlations between pre- and post-placement timing analysis, many post-placement optimization strategies have been proposed for the FPGA CAD flow to improve circuit performance. Typically, these methods depend on logic duplication or decomposition methods combine together with incremental placement.
 Circuit rewriting has proven to be a useful optimization strategy, but is typically applied during the technology mapping step of the FPGA CAD flow. While beneficial, rewriting either before or after technology mapping must rely on circuit depth rather than post-placement delays for timing optimization.
 In this paper, we show that circuit rewriting can also be used as a post-placement optimization for FPGAs. We present a post-placement optimization based on circuit rewriting which is guided by post-placement timing analysis. We replace, or rewrite, cones of logic on critical paths to improve the timing performance of a circuit. Our method is integrated with incremental placement to ensure valid placements and to guarantee that our timing analysis remains accurate throughout our proposed rewriting method. The key to our method is the ability to quickly determine if an alternative topology of LUTs is suitable for the replacement of a cone of logic on a critical path.
 We have implemented our proposed method in a commercial FPGA CAD flow. Experimental results demonstrate that the application of our rewriting algorithm can improve the routed timing performance of a design by 3.1% on average and by as much as 37.9% when applied to a set of 136 industrial designs.