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Overcoming bit loss mechanism in self‐amplified multilevel silicon‐oxide‐nitride‐oxide‐silicon memory cell

This work reports on the triple‐level NAND flash cell realized from self‐amplified (SA) double gate (DG) tunneling‐based silicon‐oxide‐nitride‐oxide‐silicon (T‐SONOS) memory device. Through calibrated simulations, we show that capacitive coupling between the front gate and back gate can be used to store eight states (or 3 bits), that is, from “000” to “111,” in a T‐SONOS memory device with the readable difference between each level at lower programming voltages. The performance of the multilevel T‐SONOS cell is compared with the inversion mode SONOS (I‐SONOS) multilevel cell. Results highlight that gate length (Lg) scaling from 100 to 25 nm significantly deteriorates the threshold voltage associated with the lower states in the I‐SONOS multilevel cell. However, highly stable eight states can be achieved in a multi‐level T‐SONOS cell at Lg = 25 nm. The results highlight the potential of SA T‐SONOS cell for designing multilevel memory cell arrays.