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A low power readout circuit for CMOS image sensor

An analog signal processing (ASP) circuit used for CMOS image sensor (CIS) readout is presented. The proposed ASP mainly includes a two-stage programmable gain amplifier (PGA), a sample-and-hold amplifier (SHA) and a digital-analog converter (DAC). Compared with conventional readout architectures, the proposed can provide finer gain, level shifting and offset calibrating function. A 1.5-Mpixel 60-fps CIS with this ASP is fabricated in a 0.13 µm 1P4M CMOS process. The experiment results indicate the sensor can normally capture images without code missing, and the measured maximum gain error of the PGA is 1.6%. Additionally, the measured offset tuning range is ±273 LSB by tuning the DAC input registers.