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Defect levels in monocrystalline and polycrystalline silicon MOS devices: a comparison

Monocrystalline and polycrystalline p-type silicon MOS devices have been fabricated. Defect levels have been investigated using deep level transient spectroscopy (DLTS) and high frequency capacitance-voltage (HFCV) measurements. A peak of the interface state distribution is found at 0.16 eV in monocrystalline, and at 0.12 eV in polycrystalline, MOS devices. In the latter case the peak value of the interface states is higher than in the former, ranging between 2*1012 and 2*1013 eV-1 cm2. A bulk level at 0.58 eV above the valence band is only found in polycrystalline MOS devices. This level seems to be induced during the oxidation processes.