{'fraction_non_alphanumeric': 0.027357811375089993, 'fraction_numerical': 0.0028797696184305254, 'mean_word_length': 5.0964912280701755, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Asymmetric drain underlap dopant-segregated Schottky barrier ultrathin-body SOI MOSFET for low-power mixed-signal circuits

In this paper, asymmetric drain (ASD) underlap channel dopant-segregated Schottky barrier (DSSB) silicon-on-insulator (SOI) MOSFET has been proposed to improve the scalability and high-frequency performance of DSSB SOI MOSFET. The asymmetry of this device lies in the spacer thickness at the drain which creates an underlap channel with the same dopant-segregation length as that of the overlap channel at the source. The presence of overlap at the source and underlap at the drain of this device not only makes it immune to short-channel effects and the gate-induced drain leakage but also improves the analog figures of merit such as transconductance, intrinsic gain and unity-gain frequency of the device. In addition to this, the inverter power dissipation and the ring-oscillator delay in an optimized ASD underlap device are reduced by ∼40% and ∼20%, respectively, over the symmetric source/drain overlap and underlap channel devices. Thus, the significant improvement in both digital and analog figures of merit at nanoscale shows the suitability of the proposed device for low-power mixed-signal circuits. The proposed fabrication flow of this novel device is also similar to the DSSB SOI MOSFET flow and demonstrates the use of conventional CMOS processes.