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Conservative modeling of the contribution of spurious transitions to power dissipation in digital CMOS VLSI circuits

To achieve optimum performance a number of CMOS design choices, such as the choice of logic family, requires a general model of the fraction of logic transitions that arise from spurious transitions (glitches). This fraction can then be used to estimate the additional power dissipation due to spurious transitions. Analysis and simulation of a ripple-carry adder is used to derive a conservative model for static circuits. Across most applications, a good conservative estimate for the fraction is 30 to 40% of the total number of logic transitions.