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Design space exploration for fair resource-allocated NoC architectures

Networks-on-chip are integral parts of modern chips and designers explore the architectural design space to optimize both performance and energy-efficiency. Architectural choices for modern NoCs include: (i) partitioning using multiple sub-networks (P), (ii) concentration (C), and (iii) express physical links (X). Previous efforts do not adequately cover the design space while the range of assumptions vary significantly, rendering direct comparisons between different configurations impossible. This work expands the NoC design space and overcomes previous shortcomings by exploring the impact of architectural choices (P, C, X) separately and combinatorially on a 2D mesh. We generate all possible NoC configurations for large systems (64 and 256 nodes) and compare performance, energy, and area when the configurations utilize equal resources. First, we equalize the bisection wire count and analyze the impact of P, C, and X on NoC buffer space using analytical formulas. Then, we distribute an equal amount of buffer space in each NoC configuration by adjusting the respective router micro-architecture. Our results indicate that, with equal resources, none of the configurations exceeds the performance of the baseline 2D mesh. Moreover, we find that as node count increases to hundreds, the exclusive use of express physical links with an interval of 2 is the best approach in terms of energy and area. Furthermore, we observe that partitioning under equal buffer space and bisection bandwidth results in increased energy and area.