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A novel ACS scheme for area-efficient Viterbi decoders

This paper presents a novel ACS (add-compare-select) scheme that enables high-speeds to be achieved in area-efficient Viterbi decoders without compromising area and power efficiency. This is achieved by introducing multi-level pipelining into the ACS feedback loop. As a proof of concept, a constraint-7 Viterbi decoder using 8 ACS units has been designed with 5 pipeline levels. This design has been implemented successfully on an FPGA device. The results obtained confirm functionality, speed improvements and the expected low resource usage. To quantify these, a state-parallel Viterbi decoder design has also been implemented on the same FPGA device and performance comparisons made.