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A 3.7-mW 2.4-GHz Phase-Tracking GFSK Receiver With BBPLL-Based Demodulation

This paper describes a low-power phase-domain receiver with single-bit phase-to-digital conversion by utilizing a divider-less bang-bang phase-locked loop (BBPLL). The BBPLL performs 1-bit oversampled noise-shaping demodulation as a secondary loop in the receiver, offering a flexible gain control as well as a simple baseband interface. A prototype 2.4-GHz receiver with an auxiliary 50-MHz BBPLL is implemented in 65-nm CMOS. In the RF loop, a dual-path LC voltage-controlled oscillator (VCO) with partitioned coarse tuning is designed to have a low gain constant over temperature variation. In the BBPLL, a dual-input ring VCO provides separate gain control and low-pass filtering for the demodulation path. The receiver performs 100-kb/s Gaussian Frequency Shift Keying (GFSK) demodulation with the sensitivity of −89 dBm and the power consumption of 3.7 mW from a 0.8-V supply in which 0.15 mW is consumed by the BBPLL.