{'fraction_non_alphanumeric': 0.029596412556053813, 'fraction_numerical': 0.008071748878923767, 'mean_word_length': 5.269662921348314, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design and implementation of full subtractor using different adiabatic techniques

CMOS technology is evolving rapidly with the advancement in VLSI design. The gate count on the integrated chip is steadily rising which leads to enhanced power dissipation and heat generation. Therefore, a new paradigm that can circumvent these limitations needs to be devised. Adiabatic logic is one of the novel techniques used to attain high throughput with decreased power utilization in power-aware VLSI circuits. Moreover, low-power arithmetic circuits are crucial these days to design high-end computing devices. The design of full subtractor using ECRL (efficient charge recovery logic), PFAL (positive feedback adiabatic logic), MPFAL (modified positive feedback adiabatic logic), and DC-DB PFAL (direct current diode biased positive feedback adiabatic logic) techniques are presented in this paper. The design and simulation are carried out on cadence virtuoso tool at 180nm node. The proposed full subtractor using DC-DB PFAL has 97%, 64 %, and 65 % improvement in power dissipation over ECRL, PFAL, and MPFAL techniques.