{'fraction_non_alphanumeric': 0.016771488469601678, 'fraction_numerical': 0.0041928721174004195, 'mean_word_length': 5.479638009049774, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 1, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Characterization of Contact Etching Profile for 0.35um Analog Mixed Signal Product Development

An Analog Mixed Signal (AMS) device incorporating polysilicon insulator polysilicon (PIP) capacitor and polyresistor sub-modules has been fabricated using 0.35um CMOS technology. Addition of the analog sub-modules has introduced topography height difference between the PIP capacitor region and the MOS transistor region. The resultant topography had resulted in variation of the pre-metal dielectric (PMD) layer thickness where contact holes will be formed. Topography height difference had also resulted in PMD layer thickness variation between one location to another. The thickest PMD layer was located on the MOS transistor active region, while the thinnest PMD layer was on the polyresistor region. Etching contact holes on such topography along with different etch stop materials is challenging. Hence, contact etching process needs to be optimized to ensure contact holes at all locations are cleared without too much overetching of the underlying layer. Furthermore, the etched profile needs to be slightly tapered to achieve good barrier metal step coverage. A new contact etching process that fulfilled the device requirements with good contact resistance parameters has been developed. The process optimization experiments and the electrical test results of the contact resistance are presented and discussed in this paper.