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MAQO: A Scalable Many-Core Annealer for Quadratic Optimization

The end of Dennard Scaling has led to the increased development of domain-specific hardware for difficult tasks such as combinatorial optimization. This paper proposes a scalable CMOS architecture for solving NP-hard permutation optimization problems through careful design of a custom processing core in combination with a Parallel Tempering scheduler. A 32-core variant of this architecture is implemented on a Stratix 10 FPGA, operating at 220MHz with a peak power draw of 40W, and is shown to perform up to 4 times faster and with 40 times higher efficiency than the same algorithm implemented on a 64-core CPU with SIMD.