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CODA-R: a reconfigurable testbed for real-time parallel computation

Recently the emergence of reconfigurable Field Programmable Gate Arrays (FPGAs) has given rise to a new form of computing engine using a dynamically changing architecture of processing elements. One major benefit of using FPGAs is that different architectural variations can easily be tested and evaluated on real applications. The other benefit is that some functions can be compiled and directly executed by hardware to shorten the total execution time. These benefits can also be applied to a real-time system. We have developed a prototype reconfigurable real-time parallel system CODA-R. Its key feature is that reconfigurable processing elements or units are connected by a priority-based real-time network. In this paper, we provide the technical justification for a reconfigurable real-time parallel architecture and the architecture of CODA-R and discuss them and also present some preliminary evaluation results.