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Power consumption issues in high-speed high-resolution pipelined A/D converters

In this paper, the dependency of the power consumption on the main specifications of a pipelined analog-to-digital converter (ADC), including the effective number of bits (ENOB), the full-scale voltage (VFS), and the speed, is studied. Then, a novel design methodology for low-voltage high-speed high-SNR pipelined A/D converters is presented which simultaneously determines the optimum values of the capacitors and the resolutions of the stages, and the compensation capacitors of the cascode-compensated operational amplifiers.