{'fraction_non_alphanumeric': 0.024361948955916472, 'fraction_numerical': 0.004640371229698376, 'mean_word_length': 5.849206349206349, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Reducing Synchronization Overhead Using Hardware Transactional Memory

Transactional Memory (TM) is a high-level abstraction for synchronizing access to shared data that allows programmers to easily group shared data accesses into atomic blocks. Intel’s latest processor generation, Haswell, provides support for the Transactional Synchronization Extensions (TSX), an extension to the x86 instruction set that provides TM functionality. We modify LevelDB, a write optimized persistent key-value store, to use TSX for synchronization. A comparison of the TSX-augmented LevelDB with the original LevelDB is performed to assess the performance tradeoffs of TSX under various workloads. Our modified LevelDB exhibits increased performance on write-intensive simulated workloads, as well as 25% improvement in write throughput on the standard LevelDB benchmark suite.