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Optimum Repeater Insertion for on-chip Global Interconnects in High Performance Deep Submicron ICs

paper addresses the problem of power dissipation during buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is also used to quantify relative importance of various components of the power dissipation for power-optimal solutions for various technology nodes.