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Ladon : a 24-processor low-power performance-scalable processor module for sensor platforms

Node architectures in wireless sensor networks often have to balance ultra-low-power idling, with an occasional need for high performance, due in part to the sporadic nature of the phenomena they usually monitor. Higher performance processors, with more computing resources, peripherals, and larger on-chip memories, typically also have larger idle power dissipation. Existing node platforms employing off-theshelf microcontrollers target one point in a tradeoff space, and are either resource constrained and low power, or are high performance and less power efficient. Rather than employing a single processor implementation that is limited to one point in the tradeoff space, an alternative approach is the use of multi-microcontroller designs. This is feasible since many sensor network applications have a fair amount of coarse-grained parallelism, ranging from protocol stack pipeline parallelism to event-level concurrency. Motivated by these observations, and by recent attempts in the research literature to develop programming models, language implementations, and system software for platforms consisting of networks of resource-constrained computing elements, a hardware platform, Ladon, was developed. The platform implements a miniature reusable multimicrocontroller module for use in wireless sensor network research. This paper presents the system architecture of the Ladon processor module and evaluates its hardware implementation.