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Efficient Forced Convergence algorithm for low power LDPC decoders

This paper proposes an efficient Forced Convergence (FC) algorithm to reduce the computational complexity of LDPC decoders. To reduce the computational complexity, the proposed algorithm uses only one threshold value and two conditions of variable nodes (VNs) while the existing FC algorithm uses two threshold values and two conditions. The simulation results show that the proposed algorithm achieves the bit error rate (BER) performance close to the typical Min-Sum algorithm. however, it can significantly reduce the computational complexity compared to the existing FC algorithm.