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Real time implementation of the combined SLB/CA-CFAR system with non coherent integration

In this paper, we present a real time DSP implementation of the combined cell averaging- constant false alarm rate (CA-CFAR) detector and sidelobe blanking (SLB) system with non coherent integration. The proposed approach has been implemented using the Texas Instruments TMS320C6713 processor. The designed architecture is fully reconfigurable in terms of the number of reference and guard cells as well as the sampling frequency and the coherent processing interval (number of integrated pulses). The data acquisition system can work under multimode including multi-range and different pulse width. The proposed system scheme and the real time implementation results are given in this paper.