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Design and implementation of a FFT/IFFT soft IP generator for OFDM system

We design an automatic generation environment for a fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) hardware accelerator with various parameters. The target application is the FFT/IFFT core, from 8 to 8192 points, for OFDM systems. With different input parameters and constraints, our FFT/IFFT soft IP generator can automatically generate complete design results including the synthesizable Verilog HDL code, test bench, and synthesis script files. We also produce the on-chip-bus interface circuit, compliant with the AMBA protocol, and associated device driver so that the generated IP is ready for system-on-chip (SOC) integration. Therefore, not only reducing the time-to-market development cost, the proposed design can provide a reuseable and programmable IP core which is suitable for SoC applications.