{'fraction_non_alphanumeric': 0.042997542997543, 'fraction_numerical': 0.019656019656019656, 'mean_word_length': 5.174242424242424, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Analysis and optimization of in-situ error detection techniques in ultra-low-voltage pipeline

In-situ error-detection and correction techniques have a strong potential to eliminate the worst-case margins in ultra-low-voltage (ULV) pipelines while achieving high variation tolerance. Adding the capability of error detection, however, can incur large hardware overhead, especially in ULV due to the larger variability. In this paper, we analyze the hardware overhead of error-detection techniques and propose a technique called sparse insertion of error-detecting registers. The proposed technique, applied on benchmark 3-stage pipeline operating at 0.35V, can reduce the error-detecting register count by 1.3-4.3×, total area by 15-40% and timing violation rate by 19-37×, compared to the conventional techniques.