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A single transistor EEPROM cell and its implementation in a 512K CMOS EEPROM

This paper describes an electrically programmable and erasable nonvolatile memory cell employing a single floating gate transistor (1), and its implementation in a 512K CMOS EEPROM memory chip. The single transistor EEPROM cell is based on an innovative device concept, and utilizes proven process techniques. The cell is programmed to a high Vt state by channel hot electron injection like an EPROM cell, and erased to a low Vt state by Fowler Nordheim tunneling from the floating gate to source diffusion. With the proper choice of gate dielectric and cell layout the cell is programmed to high threshold with less than 5 volts on the drain and less than 15 volts on the control gate. Erasing is achieved with less than 15 volts on the source diffusion. A 25 square micron cell has been implemented in a 512K EEPROM memory chip with a die size of 4.3 mm. by 7 mm.