{'fraction_non_alphanumeric': 0.020369191597708464, 'fraction_numerical': 0.001273074474856779, 'mean_word_length': 5.68936170212766, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Robust alignment mark design for DRAM using a holistic computational approach

In advanced DRAM fabrication, wafer alignment is a key enabler to meet on-product overlay performance requirement. Due to the extreme complexity of patterning and integration process involved, it’s becoming a challenge to design alignment marks that can be patterned robustly through process window, meet process integration constraints, withstand large process variation or changes, and provide accurate alignment measurement, during early development. The unique tilted pattern in DRAM fabrication technology poses special challenges during both design and process phase. In this paper, we present a holistic computational approach to design robust alignment marks with ASML’s integrated Design for Control (D4C) and OPC solutions. With this integrated solution, we design a complex set of alignment marks for the entire full flow process from FEOL through BEOL, tailored by each stack of different lithography layers. In mark design stage, marks’ signal and robustness are optimized by D4C simulation, taking into account the design rule and process constraints, while patterning fidelity and process window of these marks is ensured by OPC, subject to the design rule constraints. We demonstrate that the process window (PW) of the resulting alignment marks, especially for the challenging layers with extreme off-axis illuminations and tight design constraints, are significantly improved, while simultaneously accurate and robust alignment measurements are obtained on full loop wafers.