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Multi-channel clock and data recovery circuit for chip-to-chip optical interconnects

A multi-channel gated-oscillator-based clock and data recovery (CDR) circuit for chip-to-chip optical link applications is proposed and designed. The key components of the proposed CDR are a charge-pump phase-locked loop (CPPLL), gated-oscillators, and decision circuits. The proposed multi-channel CDR has the center frequency of gated oscillator around 2.5 GHz; however, the input data rate of each channel can be up to 3.2 Gbps. It achieves an acquisition time of 1 μs. The power dissipation is 18.27 mW for the CPPLL and 21.21 mW for each channel of the CDR. The chip size of the CPPLL is 800×750 µm2, while that of each channel of the CDR is 200×250 μm2 in a 0.18 μm CMOS technology.