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DDR3 interconnect optimization—Signal integrity and timing analysis perspective

Due to increasing demand for more bandwidth and higher data rates, the design complexity and constraints of high performance digital system have increased rapidly. Apart from the circuit design challenges, high speed interconnects have brought new challenges in signal transmission integrity and timing requirements. It is known that memory play a vital part of high performance digital system and, the feasible data transfer rate from memory is greatly influenced by performance of interconnects between memory and controller. Increase in data transfer rate from memory and decrease in access latency reduce the timing margin available to each component such as memory controller, PHY, memory module and interconnects. Hence, a diligent budgeting of timing requirement for each sub system is essential to achieve better end-to-end performance. In this paper, timing optimization of interconnects on signal integrity and timing analysis perspective is presented. As a case study an 800 Mbps interface between a dual-rank DDR3 memory and Virtex-6 FPGA has been analyzed and validated. The adopted techniques enabled deriving appropriate timing budget for interconnects and ascertain end-to-end data rate is not degraded due to sub-optimal design of interconnects. Further, the analysis also assisted to derive appropriate routing density, trace length matching, and addressing impedance discontinuities, via selection and signal integrity aware routing.