{'fraction_non_alphanumeric': 0.02413793103448276, 'fraction_numerical': 0.0, 'mean_word_length': 5.5, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design recommendations to mitigate memory and cache non-determinisms in multi-core based IMA platform of airborne systems

The adoption of multi-core processors in airborne safety-critical systems has been troublesome to the aeronautic industry. This type of processor inserts new sources of non-determinism on application execution, increasing difficulty to perform safety analysis that relies on Worst-Case Execution Time (WCET). Design recommendations to mitigate non-determinism in airborne multi-core systems are presented in this work. A prototype of platform was constructed in order to demonstrate feasibility of non-determinism mitigation recommendations. We utilized the prototype to experiment with parallel memory access. The recommendations are a sound basis to allow multi-core processors to be used in airborne systems, however, some changes are required.