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Limits and Opportunities for Designing Manycore Processor-to-Memory Networks using Monolithic Silicon Photonics

To sustain the historic performance improvement in VLSI systems, while remaining within the power envelope, the trend has moved towards designing multiple cores on a single die. However, if designed using current and/or projected electrical solutions, these systems would quickly get bandwidth-limited due to bandwith density limitations and power constraints. It is therefore necessary to explore alternate interconnect technologies like silicon photonics that could provide high bandwidth density and energy-efficient data transmission. Here, we summarize the results from our study [1] to determine the limits and opportunities for using silicon photonic technology for designing core-to-memory i.e. off-chip interconnect networks in manycore systems. We focus on the memory bandwidth aspect of the manycore design as this would be the primary bottleneck in extracting maximum performance out of a manycore system. There have been other approaches to designing both core-tomemory networks [2, 5] and core-to-core networks [3, 4, 6] using silicon photonics.