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Practical Design Method to Reduce Crosstalk for Silicon Wafer Integrated Fan-Out Technology (SWIFT®) Packages

The continued growth of smartphones, tablets and other handheld devices in the mobile market requires radical development of advanced application processor (AP) packaging technology. One solution transforms the traditional organic substrate into highly integrated fan-out wafer level packaging (FOWLP) that uses thin redistribution layers (RDLs), reduced dielectric thickness, narrow trace lines, and micro-vias. Since the design scheme used for the organic substrate will not work properly in high density FOWLP, it is imperative that the design rules are redefined based on the new wafer level technology to mitigate crosstalk noise interference. With data rate and operating frequency increasing by adopting Low Power Double Data Rate 5 (LPDDR5) memory and High Bandwidth Memory (HBM) for future products and trace width/space and micro-via size decreasing in wafer-level design, crosstalk noise is becoming a more serious issue. This paper analyzes various test vehicles in the frequency domain for an advanced design technique in the IC packaging industry, and proposes best optimization design methods for crosstalk noise reduction. First, the effect of crosstalk noise decreases with specific ground guard traces separation. Second, crosstalk caused by the microstrip can be managed by avoiding a ground guard open stub. Third, crosstalk noise in the microstrip is related to dielectric thickness and crosstalk noise is reduced by reducing the dielectric thickness. Improved crosstalk results do not occur simply from an advanced silicon package structure, but by implementing an optimized design scheme as well. The analytical crosstalk-less results in this paper can be used for overall design guidelines and the crosstalk effect can be estimated in the pre-manufacturing process for wafer level packages including the newest Silicon Wafer Integrated Fan-out Technology (SWIFT®) packages.