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FPGA based design of area efficient router architecture for Network on Chip (NoC)

FPGA Based design of area efficient router architecture for NoC is proposed in the present work. Design entry of the proposed router is done using Verilog Hardware Description Language (Verilog HDL). In the designed router four channels (east, west, north and south) are present. Each channel consists of first in first out (FIFO) buffers and multiplexers. Buffers are used to store data in binary form and multiplexers are used to control the data inputs and outputs. After designing the channels, crossbar switch has been designed and all the components have been integrated to form the complete router architecture. Modelsim simulator is used to simulate the proposed router and Xilinx ISE 14.1 is used to obtain the RTL view of the proposed design. The synthesis of the proposed design is done by using SPARTAN-6 FPGA. In the proposed work area of the router has been reduced by reducing the number of LUTs. Number of LUTs used in the crossbar switch is obtained by synthesis report. Obtained results show that the proposed router is area efficient.