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Performance evaluation of radiation hardened analog circuits based on Enclosed Layout geometry

This paper presents an investigation on the performance impacts of employing Enclosed Layout Transistor (ELT) to the design of analog building blocks. A common-source (CS) amplifier is considered as case study, to which this layout technique is applied. SPICE simulations are performed, considering two different methodologies to estimate the effective aspect ratio (W/L) of the ELT devices. The extracted equivalent W/L using a commercial design tool is compared with a well-known mathematical model presented in the literature. The simulations were carried out considering three different channel lengths for the CS amplifier. The possibility of setting the transistor drain as the inner or outer terminal of the ELT was also investigated. According to the obtained results, considering a 0.18μm technology, there may be significant performance differences, both in the DC and AC behavior of the amplifier. Additionally, in order to improve the achievable aspect ratio range of square ELTs, we propose to use parallel and series associations of enclosed devices. Depending on the desired W/L, it is also possible to save silicon area with such associations.