{'fraction_non_alphanumeric': 0.01683816651075772, 'fraction_numerical': 0.002806361085126286, 'mean_word_length': 5.407185628742515, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design of CODEC using VLSI architecture for efficient communication

Encoding and Decoding schemes plays a vital role in networking, storage, data communications and radio or wireless communication systems. The hardware architecture of an encoding and decoding blocks becomes an attractive issue in designing. Very large scale integration (VLSI) is one of the trending process of integrating thousands of transistors together in a chip and its architecture provides better performance results. When the VLSI architecture involved in the coder design, the system attains effective results in its parameters such as power consumption, speed and area occupied. In general digital systems the Half Cycle Processing Model (HCPM) is totally different which is already exist for FMO/Manchester Codec. Though this model reduces number of transistor count and achieves 100% Hardware Utilization Rate, it induces one cycle latency between positive and negative half cycles. This paper proposes a new Coder design which is integrated with the previous one to resolve this problem.