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A Fast Logic Mapping Algorithm for Multiple-Type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays

Unlike conventional CMOS circuits, nano-crossbar arrays have considerably high defect rates. Multiple-type defects randomly occur both on crosspoint switches and wires that substantially complicates the design phase of the circuits with an elimination of systematic design choices. In order to overcome this problem, a logic mapping methodology is presented in this paper. A fast heuristic algorithm using pre-mapping logic morphing, defect oriented adaptive sorting, matching with Hadamard multiplication, and backtracking is introduced. The proposed algorithm covers both crosspoint defects including stuck-open and stuck-closed types and wire defects including bridging and broken types. Effects of stuck-closed defects, mostly disregarded in the literature, are studied in depth. In simulations, an industrial benchmark suit is used for obtaining runtime and success rate values of the proposed algorithm in comparison with those of the existing algorithms in the literature. A relative accuracy evaluation is also given in comparison with exact mapping techniques. Finally, the steps of the algorithm that are based on pre-mapping and heuristic matching techniques, are separately justified with experimental results.