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Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection

This paper describes a new dynamic-power aware high level synthesis (HLS) data path approach that considers the close interrelation between clock choice and operations throughput selection whilst attempting to minimize area, power, or a combination thereof. It is shown that the proposed approach with its compound cost function and its novel clock and operations throughput selection algorithm, obtains solutions with lower power and area than using previous relevant work (Raghunathan, 1997), Moreover, different power-area tradeoffs can be explored due to the appropriate choice of clock period and operations throughput using our novel approach.