{'fraction_non_alphanumeric': 0.02235294117647059, 'fraction_numerical': 0.024705882352941175, 'mean_word_length': 4.635761589403973, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design and Benchmark of Iso-Stable High Density 4T SRAM cells for 64MB arrays in 65nm LSTP

Embedded SRAMs enable high performance operation of processor and become an essential block in modern SoCs. Memory instances occupy almost 70% of area of the embedded microprocessors and constitute a large part of power budget. So, designing dense SRAMs with low leakage power is a key focus for SRAM designers. This paper presents design and benchmark of different topologies of 4T SRAM cells and conventional 6T SRAM cell in 65nm Low Standby Power(LSTP) Technology. Our analysis shows that not only iso-stable 4T cells are 10-25% denser than conventional 6T SRAM cell, they also have upto 65% lower leakage. These density and leakage gains are enabled by a 20% loss in speed which is an acceptable trade-off for higher level caches with multi-cycle access.