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Memory conflicts and machine performance

The data transfer capacity of a vector machine is a critical factor influencing the performance of the machine. The capacity is a function of several hardware and software parameters: the bandwidth of the crossing network between processing unit and memory, the number of independent memory modules, memory access configuration, types of vector operations, and the number of access ports in-use. Memory contention occurs in a multiple access port vector machine. When long vector operation performed, the machine efficiency is just the same as the efficiency of data transfer between memory and processing unit. A random bank choice model is proposed to analyze the memory contention and its influence on machine performance. The data obtained by the model are compared with the test results on the Cray X-MP and Y-MP, and the Ardent TITAN graphic minisupercomputers. The comparisons show that the modeling data and the test results match very well. One interesting conclusion from this model is that to preserve a constant level of memory access efficiency the number of independent memory banks should be proportional to the clocks of a memory active cycle as well as to the number of access ports.