{'fraction_non_alphanumeric': 0.031128942999446598, 'fraction_numerical': 0.00774764803541782, 'mean_word_length': 4.687254130605822, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 1, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Models Comparison And Validation With the Experimental Nano- Scale Silicon Substrate Based Annealed Pt/HfO2/Pt Resistive Random Access Memory Cell


 Metal oxide resistive random access memory (RRAM) is a novel device that provides an alternate solution for existing CMOS memory devices. In RRAM, correlate the experimental result with a simulated result by a unique model is a critical task. This work focused on the validation of silicon substrate-based fabricated single layer annealed and electroformed at 80oC ambient temperature (A-80) RRAM cell. The experimental result concludes that the proposed Pt/HfO2/Pt device provides the forming voltage of 3.8 V, Vset = 1.7 V, and Vreset=-0.8 V. Switching results are compared with the simulated result which is working based on non-linear ion drift, Yakopcic and voltage threshold adaptive memristor (VTEAM) models. VTEAM model gives a closure relationship with experimental data and well suited for our fabricated device. Further, the VTEAM model is modified to contribute accurate results and one of the standard model metrics, accuracy is analysed for a modified VTEAM model. Statistical analysis proves that, the mean error percentage of modified VTEAM and VTEAM models against experimental outcomes are 21.4% and 25.3 % respectively


INTRODUCTION
RRAM is the most capable non-volatile storage device owing to its quality of nanoscale, simple structure, costeffectiveness, quick switching speed, and great compatibility with the CMOS procedure. Among many types of RRAM, metal oxide RRAM is a unique characteristic of matured fabrication compatibility with the CMOS process [1][2][3]. The bottleneck in RRAM is maintaining switching uniformity for entire periods. We rectify this challenge by device dimensions with stack layer structure [4]. The reduction of operating voltage in a scaled RRAM is a major constraint. Post-metal annealing (PMA) is an effective fabrication process to mitigate the voltage reduction problem. [5]. Developing a unique model for a nanoscale metal oxide RRAM device is an important necessity to check its behaviour in a device, circuit-level, and for system implementation. The complicated physics in RRAM leads to confusion to generate the generalized model for a new device. In literature, many models are studied and verified.
Still, no universal model is recommended for an RRAM device. Among that, researchers are more interested in few models (non-linear ion drift, Yakopcic, and VTEAM) which are supported to bipolar, voltage-controlled with the state variables of the doped and undoped region. [6].
The motivation of this work is to fabricate a single layer metal oxide Pt/HfO 2 /Pt RRAM cell and the experimental switching results are measured. Fabricated results are compared with a simulation result based on the three different models. We organize this paper: Section 2 highlights the fabrication results of the device. Section 3 presents the three different models and the modified VTEAM models for the proposed device structure. Section 4 demonstrates the simulated results of three different models with a modified models in cadence environment and the comparison of the switching result of the fabricated device with all the different model cadence output. In section 5 the important model metric is analysed for the optimized VTEAM model.

FABRICATION RESULTS
Single layer metal oxide nanoscale annealed Pt/ HfO 2 /Pt RRAM device is fabricated by sputtering, atomic layer deposition and annealing processes on the RCA cleaned and wet oxidised silicon substrate. Schematic structure, fabrication process flow, FIB-SEM cross-sectional view, XRD analysis, forming voltage (V f ), and I-V characteristics are shown in Figures 1a, 1b, 1c, 1d, 1e and 1f. Results confirmed the low V f and better memory switching function. The effect of annealing yields less operating voltage and better reliability. RRAM cell sample gives a very low Vset = 1.7 V and Vreset=-0.8V. This result is comparable with an annealed tri layer structure [7].

MODELS SELECTION
Validating the proposed device experimental result is mandatory for a successful implementation at a circuit level. Generating a unique model for RRAM is a complexity. In this paper, the experimental results are validated with three general models as per our optimized structure. Since the top switching layer is annealed, it creates number of oxygen vacancies in between the top Pt and HfO 2 layer. This effect leads the device structure state variable are doped and undoped region and gives the bipolar switching operation is present in fig 2.

Fig. 2 Bipolar switching operation based on oxygen vacancy
Moreover, the constructed device results prove the memory cell type is a bipolar with voltage-controlled mechanism. Suitable models are selected to satisfy these above-mentioned conditions. Finally, among the various models [6] Non-linear ion, Yakopcic and VTEAM models are selected for the validation purpose.

-Ve + Ve
The non-linear behaviour of RRAM that is fabricated leads to the development of a non-linear ion drift model. This can be observed from the various experimental results [8]. It is a bipolar device controlled by voltage. It is a non-linear and non-symmetric device with high complexity. Spatial heterogeneous metal/oxide electronic barrier controls the conduction in RRAM devices [9]. The movement of positively charged oxygen vacancies contribute a d ynamic switching. This oxygen vacancies functioning as original dopants will establish or discontinue the filament path that conduct over this electronic blockade. At the boundaries, metal/oxide coherences oxygen vacancy concentration is higher. The active electrode which is a top electrode of the MIM structure is the place where dynamic ON and OFF switching will take place. The resultant resistance of the memristor R MEM is the addition of doped and undoped area The I-V relation is explained as β,γ, χ and η are termed to be as fitting constants. The ON state of the memristor is approached by the term βsinh(αV) in which the electron passes the thin residual electronic barrier. The device state variable (w) range is fixed from 0 (ON) to 1 (OFF). In equation (2) the second term denotes the memristor OFF state and the term η is known as free parameter that is helped to change the switching states. The non-linear drift effects are defined by certain window functions that define the leap for the device. HP team [10] was proposed that multiplication of window function with the state variable is given by For the I-V curve modelling of the manufactured device, using the above equation the best fit is obtained, when14 ≤ ≤ 22. It made clear that the resultant dopant drift rate is very non-linearly dependent on the voltage applied to the device. Therefore, this drift phenomenon at the interfaces is accepted as nonlinear. Lehtonen and Laiho proposed a new relationship for the state variable w and is implemented in SPICE [11,12]. This model is given as [10] = × ( ) × ( ) Here 'a' is the constant, R is the real number, f [0, 1]→ reviewed as a window function and : → is a linear function which is considered in the basic linear model. g (v) is a nonlinear, odd and monotonically increasing function.
The proposed nonlinear equation is The switching between ON and OFF state is very quick in RRAM models. Here, the switching speed is depending on the exponent term q. This model is implemented in a SPICE environment for high switching speed circuits [11,12]. In SPICE, the model is verified, whether the particular model is suitable for implementation or cannot be implemented in the circuit. Although many improvements were made to the later model, it was precise because of its high accuracy that this model became the basis for the remaining RRAM models.

Yakopcic model
The bipolar voltage-controlled device model was originally tested for TiO2 systems. Although the yakopcic model [13,14] was not specifically validated for RRAM cell at its initial period, it resembled numerous RRAM fabricated memory cells. Pickett -Adbala model [15,16] is a source of the yakopcic model, which uses similar state variables but has been altered to incorporate with a synaptic function for neuromorphic system applications. The model has been tested to use in practical neuromorphic systems.
This model's state variable w (t) is defined with the boundary condition of 0 and 1. Model equation for the current is given as, State variables switching is controlled by g (v (t)) and f(x (t)). Moreover, the state variable alteration is dominated by the threshold voltage. When the input voltage is reached greater/lesser than its threshold voltage, the device structure is changing. The term g (v (t)) function simulates the device turn-on and turnoff conditions, taking input voltage polarity into account. When the voltage set (v p ) and reset (v n ) have different threshold values, this better agrees with the bipolar practical devices. This can be expressed as A p and A n controls the speed of filament formation/rupture, these parameter depends on the type of dielectric material which is selected in a switching layer. Threshold support is built into the model to improve applicability. The change of As the model was modelled using HP Labs [8]. Data on the characteristics of the TiO2 memristor, the fitting of the device is good only when the calibration of fitting parameters are properly done. To understand the degree to which the system can withstand variability, the variability must be analysed. If the critical point is reached, read/write errors may occur in the device. The equation of the function G(V(t)) that describes the device threshold is slightly modified accordingly as Where R on is the minimum device resistance and Roff is the maximum device resistance. The values applied are based on the values extracted from the fabricated device.

VTEAM Model
This model combines the advantage of a TEAM model. It focuses the threshold voltage value rather than threshold current [17]. Mathematically, Where w is a state variable, v (t) is a voltage over the device, i (t) -current through that memristor, G (w, v) is a conductance of a cell, and t is a time factor. State variable derivative is given by Where k off , k on , α off , and α on are constants, v on -Threshold on voltage, v off -Threshold off. Parameter k off and k on are positive and negative numbers, foff (w) and f on (w) denotes the derivative off and on state variable w. The window function is w ∈ [w on , w off ]. The relationship between current and voltage with the state variable is Where w on and w off denotes the boundary of internal state variable w; R on and R off represents the corresponding resistance values of the device. Previous equation can be modified in terms of exponentially relating with the state variable is Where λ is a fitting parameter, and = .

Modified VTEAM model
In general the VTEAM model the electroforming ambient temperature (T f ) is not taken into account as. But this temperature plays a vital role in the RRAM device switching operation [7]. We modified VTEAM model, considering this electroforming environment temperature coefficient (E T ). This value is to be dependent on the T f and reference temperature value (T r =298 K). Equation (15) is made different into Equation (16) shows that the current value is exponentially varied with the forming ambient temperature. High T f leads to the increased current value; it modulates the V set and V reset values.

SIMULATED RESULTS COMPARISON
This section deals with the simulation results got from the cadence environment for an RRAM symbol which is developed with a suitable Verilog A code for non-linear ion drift, Yakopcic and VTEAM models. The simulation setup is created in 90 nm technology with a peak-to-peak voltage of 2 V between two electrodes. The source pulse signal frequency is 1 MHz with a 100 ns period and 1ns rise and fall time. We implemented it in a 1R device as shown in figure 3. We executed simulation with the fixed values for, peak-to-peak voltage, frequency, time period, rise, and fall time. In, all three models the same fixed vales are given as an input.

Fig. 3 1R RRAM single Cell
When the top electrode (TE) is connected with a +ve pulse input signal, due to its bipolar switching operation simulated RRAM cell reaches to set (device ON) condition with the voltage of Vset.  When we increase the input signal frequency, the double hysteresis loop is reduced and reaches its linear state, the memory switching is affected. [10]. Speed of the switching is achieved with high mobility dopants, so it can easily crosses the boundary this leads the high switching speed applications. When we introduce low mobility dopants, hysteresis loop becomes a linear curve. In a yakopcic model, based on the fitting parameter values, the I-V graph is changes. When the threshold voltage Vp is greater than the maximum input voltage, it acts as a normal resistor instead of memory operation. Ap, An, Vp, Vn plays a vital role in a switching simulated I-V graph [17].

VTEAM MODEL METRICS ANALYSIS
Quality of models validation is evaluated by its performance against some important model metrics. Different model metrics are analysed for different models [18]. Among a good deal of metrics, accuracy plays a vital role.

Fig. 5 I-V VTEAM and modified VTEAM models simulated output with experiment result
Accuracy of the VTEAM model is calculated in terms of the mean error of the simulated result with the experimental result, Fig 5 proves  VTEAM models accuracy are analysed in term of its calculated mean error percentage value. This work motivates the researcher to fill the gap between the device levels into next circuit level.

Acknowledgements
Part of the reported work (fabrication) was carried out at the CeNSE, IISc Bangalore-India under INUP, which has been sponsored by Government of India.
Funding Statement-This research did not receive any specific grant from funding agencies in the public, commercial, or not-for-profit sectors.
Conflict of interest -Nil, (The authors have no conflicts of interest to declare that are relevant to the content of this article)

Availability of data and material -Not applicable
Code availability-Not applicable

Authors' contributions
Author 1: Napolean A Conceived and designed the analysis, collected the data, contributed data or analysis tools, performed the analysis, wrote the paper.