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Fast settling opamp with low power consumption

This paper presents a design strategy to minimize step response settling time of a two stage miller opamp with low power consumption. Appropriate spacing between poles and zero has been kept, so an underdamped transient response with minimum settling time is obtained. Analytical results show that for a specific load capacitor, if zero frequency is placed at appropriate distance from unity gain frequency, then minimum settling time can be obtained. Analysis using device modelling has been carried out to determine element values for optimum compensation followed by its simulations in triple metal layer n-well CMOS process using 0.5 µ technology. Best simulation results obtained on Tanner tool show 86.2 dB gain, 136.6 MHz unity gain frequency (ωμ ), 25 ns settling time (ts ) with 1pf load, 211 V/µs slew rate (SR) with 1pf load, and 2.56 mW of power dissipation. The approach reported has been found to be the best after carrying out extensive performance evaluation through simulation.