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On-chip input and ground ringing suppression in high-frequency buck converters

Conventional techniques for on-chip input and ground ringing suppression in high-frequency buck converters include slowing-down the gate-drive signals of the power switches, employing a RC snubber circuit, or introducing on-chip decoupling capacitors to ensure the resonance frequency of the impedance network at the input is much lower than switching frequency of the converter. The first two techniques significantly degrade efficiency, while the third consumes large silicon area. This paper proposes employing an on-chip decoupling capacitor that moves the resonance frequency of the impedance network at the input to between the switching frequency of the converter and its first harmonic, thereby achieving ringing suppression without degrading efficiency and with a much smaller on-chip capacitor than conventional methods. A 40-MHz buck converter design in 0.18-μm CMOS technology is used to test the proposed technique. The converter operates from 1.8-V input and produces an output ranging from 0.6-1.2 V with maximum load current of 1 A. The peak efficiency is 91.1%, and the input and ground ringing overshoot is suppressed to less than 0.3 V, which demonstrates the effectiveness of the proposed technique.