{'fraction_non_alphanumeric': 0.03095684803001876, 'fraction_numerical': 0.0300187617260788, 'mean_word_length': 4.798913043478261, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A low-area and high-throughput intra prediction architecture for a multi-standard HEVC and H.264/AVC video encoder

This paper describes a low-area and high-throughput hardware architecture for the intra prediction coding of today's most important video coding standards - the state of the art HEVC and its predecessor H.264/AVC. In order to reduce control complexity, memory accesses and total area, our design works with a subset of the prediction modes and possible block sizes. The multi-standard strategy is desirable because most devices produced prior the HEVC release may only have H.264/AVC accelerators (most of handheld devices, digital TVs, and set-top-boxes). The architecture was fully described in VHDL and synthesized targeting an Altera Stratix V FPGA device. The architecture is capable of processing 2560×1600 videos at 33 frames per second when operating in HEVC mode, and 3840×2160 videos at 45 frames per second in H.264/AVC mode. The cost and performance results achieved are very satisfactory when compared to related works in the literature.