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A robust and low resource FPGA-based stereoscopic vision algorithm

The development of new hardware implementations for stereo vision algorithms requires to establish a balanced trade-off among accuracy, speed and resource consumption requirements. FPGA-based devices allow devising flexible implementations fitting specific applications demands. In this paper, we propose a low resource FPGA-based solution for the calculation of the disparity map in a stereo vision system that employs non-regular shapes for the computation of the aggregate matching. Different strategies for the implementation are evaluated attending to computation speed, precision of the results and hardware demands. In addition, we introduce a new combined cost function for the matching calculation that permits to increase the performance of previous methods in the presence of radiometric changes in both stereo images. The results show that a low resource implementation can be designed with a speed ranging from 2 to 46 frames per second achieving a percentage error in the disparity calculation from 10% to 13%, respectively.