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Study on a common-mode voltage suppression method with high performance for the three-level diode-clamped inverter

Common-mode voltage in the high voltage large power ac driving system and FACTS is a hot research topic. There are many reported common-mode voltage suppression methods based on advanced SVPWM which sacrifice the performance of dc voltage utilization rate and harmonics. The authors proposed a novel common-mode voltage suppression method on the basic idea of SPWM. This proposed method forms a new modulation signal according to the definition of common-mode voltage. It can suppress the common-mode voltage to zero almost but not reduce the dc voltage utilization rate and output voltage harmonic. Three different modulations, which are traditional SPWM, SPWM with common-mode voltage reduction method and the proposed common-mode voltage suppression method, are studied in this paper. The performance of common-mode voltage, output voltage harmonic and dc voltage utilization rate in the three-level diode-clamped inverter are studied and compared. The simulation model of MATLAB is established. Simulation results show the comprehensiveness performance of the inverter with the proposed common-mode suppression method is the best comparing with other two modulation strategy.