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Design and Implementation of Full Adder in One-Transistor-One-Resistor RRAM Array

A new scheme to construct full adder in one-transistor-one-resistor (1T1R) resistive random access memory (RRAM) array is proposed in this work. IMemComp logic gates play the role of fundamental units. By means of these cascadable logic gates, a method to construct 1-bit full adder is proposed and experimentally implemented in parallel, which consists of 10-step NAND logic operations. Basing on this, we can construct half-parallel multi-bit full adder in 1T1R array by cascading more gates. This kind of full adder presents higher efficiency due to the reduction of operation steps.