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Efficient VLSI implementation of radix-8 FFT algorithm

High-radix Cooley-Turkey FFT algorithms have obvious advantages: less multiplications and reduced memory accesses so power consumption can be reduced. However, the disadvantages are that traditional direct mapping implementation of high-radix butterfly element will required more complex multipliers and thus large silicon area will be consumed. In this paper, we proposed an efficient approach to realize the high radix butterfly process element. This approach employed pipelining techniques to cascade the paralleled multipliers and thus fewer complex multipliers are utilized to realize the radix-r butterfly element. This approach can achieve a good trade-off between speed and area in the design of high radix butterfly element.