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Latchup Design Precautions for 1.0 Micron Junction Isolated CMOS ASICs Operating at Temperatures Up to 525K

We have verified the design of latchup-free bulk CMOS devices for operating temperatures up to 525K by simulation and measurement using a 1.0 micrometer twin tub ASIC process with epitaxial layer. It is possible to achieve an increase in holding voltage with rising temperature by applying design precautions. A special ASIC cell library for high temperature circuit operation has been developed and was used for ASIC design. ASIC cell design was optimized using butted contacts. Latchup did not occur during ASIC operation at 525K at a supply voltage of 5V. The use of butted contacts for ASIC cell design proved to be a good compromise between latchup susceptibility and design complexity. The results confirm the suitability of 1.0 micrometer junction isolated CMOS technology for high temperature digital ASICs.