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Investigation on CMOS on-Chip Inductors Using Various Patterned Ground/Floating Shield Techniques

Generally, the quality factors of on-chip inductors in CMOS processes are 15-18 in the frequency band below 6 GHz. It has been presented in the literature that the Q-factor of an on-chip inductor can be improved by using various patterned ground shield (PGS) techniques. The Q-factor can be improved to 17–20 by using traditional PGS. However, the optimal PGS solutions and corresponding suitable frequency ranges for inductors of different inductances are still unclear. In this study, an investigation is conducted on on-chip inductors using various types of PGS techniques. For the inductor of 10 nH, the largest improvement is achieved at 2.5 GHz by using Hilbert PGS, where the Q factor is improved by 23.8%. For the inductor of 7.7 nH, the largest improvement is achieved at 7 GHz by using Horseshoe PGS, where the Q factor is improved by 31.8%. For the inductor of 1.1 nH, the largest improvement is achieved at 8 GHz by using dual-layer PFS, where the Q factor is reduced by 25%. For the inductor of 1 nH, the largest improvement is achieved at 6.8 GHz by using modified PGS, where the Q factor is reduced by 16.2%.