{'fraction_non_alphanumeric': 0.01925925925925926, 'fraction_numerical': 0.0, 'mean_word_length': 5.201834862385321, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A new fault-tolerant architecture for CLBs in SRAM-based FPGAs

This work deals with fault tolerance in digital reconfigurable circuits. We present a novel CLB structure well suited for SRAM-based FPGAs. The proposed solution has a `Butterfly' shape which embeds intrinsic redundance and is highly regular. The behavior of the proposed Butterfly architecture and that of the conventional one toward bit-inversion errors are compared with a couple of approaches: using Matlab simulations and a fault emulation platform. The Butterfly structure has proved to be more reliable and more tolerant than the conventional counterpart, regardless of the number of simultaneous faults.