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Power savings in digital filters for wireless communication

This paper presents a methodology to reduce the power consumption, silicon area, as well as increasing the performance, in digital filters that are feasible for wireless communication circuitries. The method is based on arithmetic reductions in a wave digital filter. Basically, the multipliers are removed to reduce the number of arithmetic operations. All parameters including the dynamic and static power consumption, the silicon area, as well as the delay time are reduced substantially, without any need for trade-offs. The overall improvements in area, power consumption, and delay time, are around 50%, at an average.