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Design and analysis of single precision floating point multiplication using Karatsuba algorithm and parallel prefix adders

Floating point operations like multiplication, division, addition and subtraction are important in digital signal processing applications. Out of all these, frequently used operation is multiplication and it changes the performance of single precision floating point multiplication in terms of delay and area. In this paper, performance analysis of single precision floating point multiplier is done by using Karatsuba algorithm with Vedic technique for multiplication and different Parallel Prefix adders like Sklansky, Brent-Kung and Knowles adders for exponent addition. This combination provides lesser area to compute multiplication compared to that existing multipliers. Further, the performance parameters comparison is done in terms of area and delay. The entire modules of single precision floating point multiplier are developed with Verilog HDL and synthesized with Xilinx ISE tool.