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Techniques for accelerating simulations of electric ships

Simulation execution time often becomes a barrier to rapid system design and analysis. Several techniques may reduce simulation execution time, including the selection of appropriate simulation time step, the use of multi-rate implementations, and simulation acceleration on field programmable gate arrays (FPGAs). However, these techniques present challenges in implementation and do not always yield benefits. Through an example model, the benefits, limitations, and challenges of using these techniques are presented to provide guidance on accelerating simulations of electric ships. The use of high-level synthesis tools is presented as an implementation path for users without expertise in FPGA-based design who are interested in simulation acceleration with FPGAs.