{'fraction_non_alphanumeric': 0.026387625113739762, 'fraction_numerical': 0.0, 'mean_word_length': 5.508875739644971, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Near-ML Detection in Massive MIMO Systems with One-Bit ADCs: Algorithm and VLSI Design

One of the solutions proposed to reduce system cost and power consumption in massive multiple-input multiple-output (MIMO) systems is the use of extremely low-resolution data converters in radio-frequency (RF) chains. The resulting severe signal distortion calls for more sophisticated data detection algorithms. The near Maximum-Likelihood (ML) detection schemes proposed so far, either exhibit numerical instability issues at high SNRs or suffer from prohibitively high computational complexity. In this paper, we propose a modified near-ML detection algorithm for the one-bit quantized case that eliminates the numerical issues with the lowest complexity among similar algorithms. We also present a low-complexity VLSI architecture for the proposed algorithm. Finally, we demonstrate the FPGA implementation results of the proposed architecture and show that its complexity is similar to that of linear detectors, while significantly outperforms them from the symbol error rate (SER) performance perspective.