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1.2 kV 4H-SiC VDMOSFETs with Si-implanted Surface: Performance Enhancement and Reliability Evaluation

This paper reports on the performance improvement in 1.2KV 4H-SiC VDMOSFETs using a Si-implanted surface technique. Firstly, the devices with Si implantation on the surface shows a decrease of carbon atom percentage from XPS and EDX analysis, an improvement of subthreshold slope (SS) and mobility in n-MOSFETs, and a lower interface state density (DIT) near the conduction band edge from n-MOS capacitors. Secondly, high-voltage VDMOSFETs with Si implantation on the surface shows an improvement in SS, ID, breakdown voltage, and electrical safe operating area (SOA). Finally, the reliability including positive/negative bias temperature instability (PBTI/NBTI) and RON stability under high-voltage pulses are evaluated in high-voltage VDMOSFETs. Therefore, the Si-implanted surface technique is effective in enhancing the performance of 4H-SiC power VDMOSFETs without stability concerns.