{'fraction_non_alphanumeric': 0.025029797377830752, 'fraction_numerical': 0.03575685339690107, 'mean_word_length': 4.562913907284768, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Frequency- controllable image rejection down CMOS mixer

This paper presents a low noise frequency controllable image rejection mixer in heterodyne architecture for 2 GHz applications based on 0.18 ¿m CMOS technology. The designed mixer uses an inductor and capacitors as a notch filter to suppress the image signal and parasitic capacitance to improve the noise figure (NF) and conversion gain. Two small value capacitors in parallel with an inductor are used for precise tuning the desired image frequency. An image rejection of 20-70 dB is obtained in a 200MHz of bandwidth around 2GHz with IF varying from 100 to 300MHz. The simulation results show singleside band (SSB) NF improved 3.7 dB, the voltage conversion gain of 14.7 dB, improved by more than 4 dB. The circuit operates at the supply voltage of 1.8V, and dissipates 11.34 mW.