{'fraction_non_alphanumeric': 0.019161676646706587, 'fraction_numerical': 0.0, 'mean_word_length': 5.634920634920635, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design and operating characteristics of a reconfigurable clock distribution network

In this paper, we provide an overview of our reprogrammable multi-clock distribution scheme. We present potential architectures using this scheme, information on controller requirements and the system's operating characteristics, including a skew and jitter study. We show that reference-based clocking provides a skew tolerant scalable solution that can re-route clocks using specially designed switch-points, post-silicon. Our clock distribution is able to combine the best aspects of both active and passive clock distribution architectures by using distinct synchronization and operation phases. We show through simulation that our system is resilient enough to temperature and voltage fluctuations to be used in an ASIC, SoC or FPGA environment.