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Designing array-based CMOS logic gates by using a feedback control system

This paper introduces an expedient method for designing nano-scaled CMOS logic gates based on minimum-sized transistor arrays. NAND and NOR with fanins of 2 and 3 have been used to demonstrate the time-efficacy of the method based on a feedback control technique. The gates designed using the proposed scheme show improvement in terms of performance as well of power/energy consumption.