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NWELL CMOS fabrication process for the Virginia Microelectronics Center

The VMC is developing a CMOS process to help teach microelectronics students the techniques of semiconductor fabrication. It is also intended to be a vehicle for the implementation of VLSI digital and analog circuit designs at VCU. The development of the CMOS process is an on-going senior electrical engineering project. The long-term goal is to fabricate and test CMOS devices entirely in the VMC. To achieve this goal, we must construct a process flow, design a mask set, understand the fundamentals of basic test chip circuit layout design, and become educated on process tool operations. This project is being completed by building upon the n-well test chip layout developed at Rochester Institute of Technology.