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Optimization of diffusion, activation and damage annealing in millisecond annealing

Advances in CMOS technology require continuous reductions in the thermal budget employed for activating ion implanted dopants. However, low thermal budget annealing approaches, such as millisecond annealing, must also remove implant damage to minimize junction leakage. This paper explores the trade-offs between dopant diffusion, electrical activation and damage annealing for ultra-shallow junctions (USJ) formed by low energy B implants into both crystalline and pre-amorphized silicon. The study also addressed how low-thermal budget annealing affects the use of strong halo-style doping from As implants. Several annealing methods were studied, with the main focus on flash-assisted RTP™ (fRTP™) at temperatures between 1250°C and 1350°C. Activation was assessed with RsL™ non-contact measurements and Hg-probe four point-probe sheet resistance measurements, as well as a continuous anodic oxidation technique for depth profiling of carrier concentrations and mobility. Residual damage was assessed by photoluminescence, thermal wave studies, optical reflectance and RsL junction leakage current measurements. fRTP effectively activates high-dose, low-energy B implants, while limiting the diffusion to a few nm of profile movement. The limited thermal budget of millisecond annealing reduces, but does not fully eliminate, implant damage from heavy ions implanted at high energy, although very high process temperatures, e.g. ∼1300°C, are more effective in this regard. Strong halo doping greatly increases the junction leakage and for future device nodes it will be important to reduce implantation damage from both USJ and halo implants. Non-invasive damage metrology can help rapid optimization of implantation and annealing conditions. Such measurements will be even more useful when quantitative models can accurately link them to doping and damage profiles.