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Efficient DFT Strategy for Complex Mixed-Signal SoC

With the improvement of integration capability and technology progress, there are much more challenges in the process of test development. The heterogeneous system formed by various of circuit structures and design styles makes test very difficult, and need more test time and test cost. This paper presents the DFT implementation for one communication baseband SoC. This mixed-signal baseband chip comprises analog and digital block, IP and embedded on-chip memory. To accommodate the requirement of test, using on-chip central test control unit could control all kinds of test mode of SoC, support traditional scan mode and scan-based delay test mode which orient to sub-micro technology, operating at different clock frequencies and domains, configurable on-chip MBIST and specific test modes, and other specific DFT techniques.