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A 23.6-38.3GHz Low-Noise PLL with Digital Ring Oscillator and Multi-Ratio Injection-Locked Dividers for Millimeter-Wave Sensing

This paper presents a 23.6-38.3GHz cascaded PLL with quadrature phases designed and prototyped in 28nm CMOS. Unlike conventional approaches, no on-chip inductor is used for millimeter-wave frequency generation. Instead, a simple inverter-based ring oscillator, with scaled copies of itself and explicit mixers, forms a unique VCO-and-multi-ratio-injection-locked-frequency-divider subsystem suitable for ultra-wide frequency synthesis. The prototype achieves comparable noise performance to its LC-VCO-based counterparts for similar applications. The phase noise is better than −96dBc/Hz at 1MHz offset across the entire range with power consumption less than 35mW. This PLL is intended for integrated wide-band sensing applications at Ka- and W-bands (with an additional frequency tripler).