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Optimal Cache Organization using an Allocation Tree

The increasing use of microprocessor cores in embedded systems, as well as mobile and portable devices, creates an opportunity for customizing the cache subsystem for improved performance. In this work, we outline a technique based on a binary tree data structure to efficiently compute a set of cache size and associativity pairs that result in ideal cache behavior for a given application memory reference trace. In ideal caches, the number of cache misses is reduced to only cold misses while conflict and capacity misses are avoided entirely. Idea cache behavior is critical in real time applications, where it is desired to accurately estimate the worse case execution time of a task in the presence of caches. Likewise, ideal caches play an important role in low power applications by reducing data transmission to/from off-chip memory to a minimum. We demonstrate the feasibility of our algorithm by applying it to a large number of embedded system benchmarks.