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Code Compaction and Parallelization for VLIW/DSP Chip Architectures

The Master of Engineering Thesis presented in this paper implements an assembly code optimizer for Discrete Signal Processing (DSP) or Very Long Instruction Word (VLIW) processors. The work is re-targetable and takes as input minimal generalized chip and assembly language syntax description and unoptimized assembly code and produces optimized assembly code, based on the chip description. The code is not modified, but only re-arranged to take advantage of DSP/VLIW architecture parallelism. Restrictions are placed to make the problem more tractable and optimality is sought using linear programming and other techniques to decrease the size of the search space and thus performance close to that of native compilers is achieved, while maintaining retargetability. This document discusses motivation, design choices, implementation details and algorithms, performance, and possible extensions and applications. Thesis Supervisor: Saman P. Amarasinghe Title: Assistant Professor, MIT Laboratory for Computer Science