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Energy-Efficient CMOS Memristive Synapses for Mixed-Signal Neuromorphic System-on-a-Chip

Emerging non-volatile memory (NVM), or memristive, devices promise energy-efficient realization of deep learning, when efficiently integrated with mixed-signal integrated circuits on a CMOS substrate. Even though several algorithmic challenges need to be addressed to turn the vision of memristive Neuromorphic Systems-on-a-Chip (NeuSoCs) into reality, issues at the device and circuit interface need immediate attention from the community. In this work, we perform energy-estimation of a NeuSoC system and predict the desirable circuit and device parameters for energy-efficiency optimization. Also, CMOS synapse circuits based on the concept of CMOS memristor emulator are presented as a system prototyping methodology, while practical memristor devices are being developed and integrated with general-purpose CMOS. The proposed mixed-signal memristive synapse can be designed and fabricated using standard CMOS technologies and open doors to interesting applications in cognitive computing circuits.


Energy-Efficient CMOS Memristive Synapses for Mixed-Signal Neuromorphic System-on-a-Chip Vishal Saxena, Xinyu Wu, and Kehan Zhu, Members IEEE
Abstract-Emerging non-volatile memory (NVM), or memristive, devices promise energy-efficient realization of deep learning, when efficiently integrated with mixed-signal integrated circuits on a CMOS substrate. Even though several algorithmic challenges need to be addressed to turn the vision of memristive Neuromorphic Systems-on-a-Chip (NeuSoCs) into reality, issues at the device and circuit interface need immediate attention from the community. In this work, we perform energy-estimation of a NeuSoC system and predict the desirable circuit and device parameters for energy-efficiency optimization. Also, CMOS synapse circuits based on the concept of CMOS memristor emulator are presented as a system prototyping methodology, while practical memristor devices are being developed and integrated with general-purpose CMOS. The proposed mixedsignal memristive synapse can be designed and fabricated using standard CMOS technologies and open doors to interesting applications in cognitive computing circuits.

I. INTRODUCTION
A grand challenge for the semiconductor industry is to "Create a new type of computer that can proactively interpret and learn from data, solve unfamiliar problems using what it has learned, and operate with the energy-efficiency of the human brain [1]." Deep neural networks, or deep learning, have been remarkably successful with a growing repertoire of problems in image and video interpretation, speech recognition, control, and natural language processing [2]. However, these implementations are compute intensive and employ high-end servers with graphical processing units (GPUs) to train deep neural networks. Furthermore, the new International Roadmap for Devices and Systems (IRDS) that replaces the ITRS roadmap, looks forward to More-Moore and Beyond-Moore technologies to develop radically different data-centric computing architectures [3], [4]. New architectures are required to transcend the device variability and interconnect scaling bottlenecks in nano-scale CMOS, should exploit massive parallelism, and employ in-memory computing as inspired from biological brains. Recent progress in memristive or resistance-switching devices (RRAM, STTRAM, phase-change memory, etc.) has spurred renewed interest in neuromorphic computing [5]- [11]. Such memristive devices, integrated with standard CMOS technology, are expected to realize low-power neuromorphic system-on-a-chip (NeuSoC) with embedded deep learning and orders of magnitude lower power consumption than GPUs, as illustrated in Fig. 1 [12], Figure 1. A neuromorphic SoC architecture: (a) A fully-connected spiking neural network (SNN); (b) Crossbar synaptic array and column/rows of mixed-signal CMOS neurons; (c) A synapse between the input (pre-synaptic) and output (post-synaptic) neurons that adjusts its weight using STDP; (d) Floorplan of 2D SNN arrays. [13]. Since 'analog' memristor device technology is yet to mature while practical demonstration in neural circuits are being pursued [14]- [16], we earlier proposed a low-risk and robust alternative for circuit prototyping using a CMOS memristor emulator [17], [18]. In this work, we extend this CMOS memristor concept to memristive synapse circuits that realize bioplausible spike-timing dependent plasticity (STDP) learning. The rest of the manuscript is organized as follows: Section II presents energy-estimation of memristive NeuSoCs; Section III and IV describe the CMOS memristor and synapse circuits. Finally Section V presents simulation results and application in an image classification task, followed by conclusion.

II. ENERGY-EFFICIENCY OF NEUROMORPHIC SOCS
The primary motivation of exploring memristive (or emerging NVM-based) spiking neural network is to achieve orders of magnitude energy-efficiency improvement over the contemporary digital architectures. This is expected to be achieved by employing event-driven asynchronous spiking neural networks (SNNs), with low-power circuits and ultralow-power synaptic (memory) devices. In an SNN, the spike shape parameters and the low-resistance state (LRS) resistance, R LRS , of the memristive devices (R HRS is typically order(s) of magnitude higher than R LRS ) contribute to the energy consumed in an spike event. The total energy consumption is also decided by the sparsity, i.e. the percentage of synapses in LRS state, spiking activity, and the power consumption in the CMOS neurons. Assuming a rectangular spike pulse-shape of amplitude V p and width T p , the current input signal is I syn = Vp R M , and the energy consumption for a spike driving a synapse with resistance R M , R LRS < R M < R HRS , is given by The approximate SNN energy consumption for one event can be formulated as where η sparsity is the sparsity factor (i.e. the fraction of neurons firing on average), η LRS is fraction of synapses in the LRS-state, N s is the number of synaptic connections, N n is the number of neurons. P neuron is the neuron power consumption; energy consumed in the peripheral circuits is ignored to simplify the analysis. To provide a rough systemlevel comparison, the AlexNet convolutional neural network for deep learning used for the Imagenet Challenge comprised of 61M synaptic weights and 640k neurons [19]. We assume that an equivalent SNN is constructed through transfer learning [20], or spike-based equivalent of backpropagation algorithm [21]; the circuit architecture is essentially the same. With an estimation based on the RRAM-compatible spiking neuron chip realized in [22], 4-bit compound memristive synapses [14], [15], [23], and R LRS ranging from 0.1-10M Ω, the energy consumption for processing (training or classification) of one image is shown in Table I. By comparing with the contemporary advanced GPU Nvidia P4 [24] (170 images/s/W), a memristive architecture with R LRS = 100kΩ provides a meagre 14× improvement in energy-efficiency. However, the energy consumption can be significantly reduced if the LRS resistance of the memristive devices can be increased to high-M Ω regime, leading to a potential 1000× range performance improvement; high LRS also helps reduce the power consumption in the opamp-based neuron circuits [22], [25].Since there has been less focus on realizing high-LRS devices as the multi-valued memristive devices are still under development, circuit solutions are desired to address this wide energy-efficiency gap.

III. CMOS MEMRISTOR
Memristor was defined as a two-terminal circuit-theoretic concept in [26], and later extended to a wider class of memristive devices [27]. The fundamental promise of the memristive devices lies in their 'analog' memory, that enables them to store as well as manipulate information in analogdomain. This is harnessed in neuromorphic computing, where memristors realize incremental synapses that learn based on STDP, a bio-inspired local learning rule that implements spikebased expectation maximization (SEM) algorithm [12], [15], [21], [28]- [30]. The author recently proposed a compact CMOS memristor (emulator) circuit [17], [18]. The fundamental concept is illustrated in Fig. 2 (a&b), where an nchannel MOSFET (NMOS) M 1 implements a floating variable resistance between terminals A and B. The transconductor G m senses the voltage across the two terminals, produces a smallsignal current which is integrated as charge on capacitor C m . When the strobe Φ 1 is low, the capacitor C m is disconnected from the transconductor and holds the stored charge; thus realizing a dynamic analog memory. Figure 2. A CMOS memristor circuit with its pinched hysteresis curve [17], [18].
Here, the voltage on the capacitor, V G , controls the gate of M 1 and is thus the 'state,' x, of the synapse. The switch (SW ) prevents G m 's output from leaking the state (x ≡ V G ) on capacitor C m when no inputs are applied. Assuming that M 1 is in triode, the dynamics of the memristor circuit are approximated as where V GS and V T HN are the gate-to-source and threshold voltages; β = KP n W L , KP n is the transconductance parameter, W/L is the sizing for M 1 . In order to force M 1 in triode for large drain-source voltage swings, a zero-or lowthreshold voltage (ZVT/LVT) transistor is employed [17], [18]. The simulated current-voltage characteristics for the memristor circuit, seen in Fig. 2 (c), confirms the pinched hysteresis signature of an ideal memristor.
Contemporary memristive devices exhibit several limitations; they exhibit stochastic switching and variability in resistance states, depending upon the initial 'forming' step [31]- [33]. Further, it is challenging to realize stable multi-valued weights with filamentary devices [15], [34]; Oxide-switching devices have exhibited~9 states and their performance insitu a circuit is being investigated [35]. A greater impediment for realizing NeuSoCs is the lower LRS resistance observed in memristive devices (100Ω − 10kΩ) [35], which leads to energy inefficiency as detailed earlier in Section II. Thus, it is desirable to realize CMOS based memristive synapses for enabling system-level exploration while the memristive devices mature in research.

IV. MEMRISTIVE SYNAPSE CIRCUIT
Memristive spiking circuits typically use analog spikes with rectangular positive pulse with a negative exponential tail [22]; however, representation of spikes with digital pulses is highly desirable for large-scale NeuSoC implementation. Further, an accelerated neural dynamics with moderate speed (few MHz's) is preferred over biological time-scales (sub-kHz) for optimizing CMOS circuit area and energy consumption [36]. Current-output type bio-mimetic synapses are pervasive in literature ( [37] and references therein), where subthreshold analog techniques were used to mimic synaptic ion-channel dynamics. Most recently, [38] reported a pair-wise STDP synapse with short-term retention, and [39] combined subthreshold circuits with a latch. In contrast, we have proposed memristive STDP-learning synapse concept shown in Figure  3 and was previously disclosed by us in [17]. In this work, we expand on the previous disclosure, and present circuits and system-level details. The circuit employs the trace decay method for emulating STDP as used in the event-driven simulators for computational neuroscience [38]- [40]. The STDP weight update block converts the relative timing between pre and post spikes (∆t = t post − t pre ) into change in V G , and thus the synaptic weight. Figure 3 (b) shows schematics for the synapse, and one of several possible transistor-level implementations is shown in Fig. 4. Here, the input pre and post pulses are converted into voltage traces V p,exp and V m,exp respectively, using the two Exponential Decay Circuit (EDC) blocks. The outputs of the EDCs are translated to a current using the shared G m , which are then integrated on C 1 . The exponential trace is implemented using active resistors, R p,m , with time-constants τ p,m = R p,m C p,m which can be independently tuned.    Figure 5 (b). Here, the (pre)-synaptic spike arrives earlier than the (post)-synaptic spike. EDC output, V p,exp , is then sampled by the post spike. This sampled voltage V p,exp (∆t) leads to an increase in the voltage V G (i.e. the state of the synapse) and increase in synaptic weight/conductance (w ≡ G(V G )); synapse undergoes short-term potentiation. Similarly, in the second case, the post spike arrives earlier than pre which in turn reduces the synapse state V G ; the synapse undergoes short-term depression. The references A + and A − determine the maximum synaptic potentiation/depression as ∆w p,m ≈ ± βGm C1 A ± T p = ±γA ± . Even though the dynamic STDP synapses provide analog states, they can only realize short-term potentiation/depression as the capacitor memory leaks away in few milli-seconds. However in a NeuSoC, the final weights after training must be persistent and amenable for read-out/in. This is realized by employing long-term bistability in synapses where after short-term STDP learning, the weights are quantized to either a high or low binary conductance state. As shown in Figs. 3&4, a weak latch is connected to V G . This slow resolving subthreshold latch is designed for very large regeneration timeconstants (τ w =1-5ms) such that it doesn't interfere with the short-term STDP learning. However, once the STDP pulses are no longer present, the weak bistable latch slowly steers the state of the synapse to either a large voltage (LRS) or to a low-voltage (HRS) long-term states, which can easily be read-out. The synapse circuit in Fig. 4 is implemented in a 130nm CMOS technology with supply V DD = 1.2V . The transistor sizing and parameter values used in this circuit are listed in Table II. The memristive synapse, for the given sizing for M 1 , realizes LRS and HRS resistances of 0.4M Ω and 16M Ω respectively, providing significant improvement over contemporary memristive devices. As detailed in [22], [30], the traditional subthreshold neuron designs are not suitable for driving memristive load. The opamp-based integrate-andfire neurons with winner-take-all STDP learning interface from author's prior work in [30] can directly be adapted to interface with the presented synapses; higher LRS resistance will further help simply opamp design.

V. SIMULATION RESULTS
In this design, the total standby current drawn from V DD is 490pA, while 10.4nA is drawn during the pre/post spike event. This results in a static power consumption of 588pW and dynamic energy consumption of 91.24fJ/spike (for V pre − V post = 600mV ) in the LRS state. This circuit can be easily modified to different specifications and further optimized for energy-efficiency, area and speed. Figure 6 shows transient simulation for a single synapse; pre and post pulses are applied with ∆t = t post − t pre = −1µs, spaced by 50µs and the state voltage V G and synaptic current between pre and post terminals are displayed. We can observe that the weight undergoes monotonic decrease due to pair-wise STDP updates with a corresponding decrease in synapse weight/conductance, w, and thus the synaptic current, I syn = w(V pre − V post ).  Fig. 7 is constructed to determine the STDP learning function for the synapse circuit. Here, pre and post spikes are applied with progressively changing ∆t from −10µs to 10µs with spacing of 50µs to allow the transients to completely decay. This results in approximate double-exponential learning function characteristic of pairwise STDP function seen in Fig. 5(b).  Table  II. Long-term bistability is demonstrated through simulations in Fig. 8 where spikes are applied such that the weight crosses the latch's threshold point, V w,thr ≈ 0.6V in Fig. 8(left) and is below threshold in Fig. 8 (right). The weak latch is biased in subthreshold and has a regenerative time-constant of τ w ≈ 2ms; the latch slowly resolves the synaptic state to logic high (LRS) or low (LRS). An SNN, similar to [30], was setup using the bistable memristive synapse and winner-take-all neuron macro-models using Brian2 libraries in Python [40]. The UCI handwritten digits dataset (3,823 training and 1,797 test 8 × 8 bitmap images [41]) was used to train the fully-connected SNN with 64 input and 10 output neurons, 640 synapses, and with a teacher signal enforcing the output labels. Fig. 9 shows the learned weights for each output neuron. For analog synapses the test accuracy was 83% for all 10 digits (96% for 4 digits); the bistable synapses achieve accuracy of~74% for 10 digits due to binary quantization during training. Care must be taken to ensure that τ w is much larger than the time for which input samples are presented (50µs) to avoid catastrophic forgetting. In this experiment, the bistable SNN was trained for 500 images as a large number of weights, w ijk , start approaching w max = 1, resulting in loss of classification accuracy. Further, w min 0.01 must be used as otherwise there is a chance of all the weights getting quantized to 0, and the neurons will never fire.

Next, a transient simulation shown in
Trained weights after 3000 samples with analog synapses Trained weights after 100 samples with bistable synapses Trained weights after 300 samples with bistable synapses Trained weights after 500 samples with bistable synapses Figure 9. SNN for handwritten digits classification. Synaptic weight evolution rearranged as 8×8 bitmap for analog and the proposed bistable synapses.

VI. CONCLUSION
A compact analog memristive STDP synapse circuit, with long-term binary retention and high LRS resistance, is introduced and designed in standard CMOS and analytical as well as simulation results are presented. The circuit is used to realize image classification application and the challenges are discussed. In summary, the synapse provides an efficient circuit solution for NeuSoC architecture exploration, while memristive devices on CMOS platforms reach maturity.