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HyperFPGA: A possible general purpose reconfigurable hardware for custom supercomputing

In this work we propose and analyze a possible hardware architecture for experimentation on fine-grained reconfigurable supercomputing based on modern Field Programmable Gate Array (FPGA) technology. It is proposed a scalable cubic array of elementary computational units which are interconnected according to a tridimensional toroidal mesh network. Each computational unit is essentially formed by an FPGA plus an onboard external RAM memory. While the adjacent units in the bulk are directly interconnected through the regular FPGA IOs; the external units at opposite faces of the cubic array are interconnected by mean of high speed serial links in order to grant homogeneous data transfer bandwidth among all topologically adjacent units. Among several relevant issues we discuss the feasibility, scalability and portability.