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An evolutionary approach to GHz digital systems

Genetic-algorithm based techniques have been used to successfully calibrate both analogue and digital VLSI chips. This paper investigates the potential of applying the developed techniques to a generic high-speed digital system, which comprises an analogue-to-digital converter and digital logic integrated on a single chip. It is concluded that evolvable calibration techniques are most likely to be applied to VLSI design where the actual value of a variable is critical rather than the more common instance of the variable having to be greater than a given value or the quantity of interest is the ratio of two matched components. Probably the best example of this is delay. As clock frequencies approach 1 GHz variation of buffer delay and clock skew become increasingly important.