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PSPICE Implementation of an 8-bit Low Power Energy Recovery Full Adder

Energy recovery technique has attracted interest of low power VLSI designers in recent years. This low power design technique has been proposed and discussed by many researchers. In this paper, we implemented energy recovery technique in the PSPICE using an 8-bit full adder circuit as an example. Full adder circuit has been widely used in arithmetic operations for addition, multipliers and Arithmetic Logic Unit (ALU). It is a building block used in digital signal processing, image processing and microprocessor. An 8-bit low power and low transistor count static energy recovery full adder (SERF) is implemented in this paper. The power consumption and general characteristics of the SERF adder are then compared with the 8-bit traditional CMOS full adder. PSPICE power simulation is used to verify its power consumption for the given input pattern sequence. Simulation result demonstrates effective power saving of the energy recovery full adder compared to static CMOS full adder.