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Efficient implementation of PID control algorithm using FPGA technology

In this paper, an efficient design scheme for implementation of the proportional-integral-derivative (PID) controller using field programmable gate array (FPGA) technology is presented. The algorithm is implemented using a distributed arithmetic (DA)-based scheme where a look-up-table (LUT) mechanism inside the FPGA is utilized. Two novel DA-based PID controllers have been proposed for FPGA implementation. The implementation results show that, the two DA methods require 13% and 4% of logic devices, respectively, compared to the design using multipliers. Furthermore, the power consumption is reduced by about 40%. A design which is efficient in terms of power consumption and chip area while having adequate speed means that the FPGA chip can be used to accommodate more controllers with low power consumption, resulting in a cost reduction of the controller hardware.