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An advanced input-queued ATM switch with a pipelined approach to arbitration

In this paper, we consider the transmission latency of request and grant data between input buffers and a central arbiter in an input-queued ATM switch. We propose a new input queuing switch architecture to allow the transmission latency and to increase the throughput of a switching system using a pipelined approach to ATM switch arbitration. Our scheme achieves the same saturation throughput as an output-queued ATM switch, using the arbitration algorithm of a basic 2DRR.