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A 28.16-Gb/s Area-Efficient 60-GHz CMOS Bidirectional Transceiver for IEEE 802.11ay

This article presents a 60-GHz CMOS transceiver designed for IEEE 802.11ay. To reduce the manufacturing cost, an area-efficient bidirectional technique is utilized in this work. The proposed bidirectional amplifier allows the sharing of interstage passive components. A five-stage power-amplifier (PA)-low-noise-amplifier (PA-LNA) designed based on the proposed bidirectional amplifier occupies less than half on-chip area, while staying a similar performance with the conventional standalone PA-LNA. Considering the multiple-in–multiple-out (MIMO) configuration, this work integrates two transceiver elements in the same chip. Thanks to the area-efficient bidirectional circuits, the transceiver in this work only requires 0.96-mm2 core area including the quadrature upconversion and downconversion. The occupied core area for a five-stage PA-LNA is 0.44 mm2. The measured noise figure for the proposed transceiver in RX mode is 5.4 dB at 60 GHz. The measured TX-mode error vector magnitude (EVM) is −26 dB in 64 quadrature amplitude modulation (QAM) with an output power of −4.2 dBm. This work realizes a maximum data rate of 28.16 Gb/s in 16-QAM. A 64-QAM two-channel-bonding data rate of 21.12 Gb/s is also achieved by the transceiver with a −22.5-dB TX-to-RX EVM. The power consumptions are 94 mW in TX mode and 105 mW in RX mode.