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A mechanism for the detection and removal of limit cycles in the operation of sigma delta modulators

Sigma delta modulators (SDMs) may suffer from limit cycles, where the output bits may enter a repeating pattern. Current methods of preventing this phenomenon introduce unwanted noise, do not always succeed, and are implemented when not needed. We present a more effective method for detecting and removing unwanted limit cycles. This destroys the periodicity of sigma-delta ADC modulator's output sequence and, thereby, removes the limit cycles. Compared with conventional methods, the SDM has less SNR penalty and the mechanism is simple to implement. Moreover, the SDM has a higher allowed input dynamic range than conventional modulator dithering schemes. Analog and digital implementations of the limit cycle detection and removal schemes are discussed for both feedforward and feedback designs. Results are reported which demonstrate the success of these methods.