{'fraction_non_alphanumeric': 0.0196078431372549, 'fraction_numerical': 0.0, 'mean_word_length': 5.551282051282051, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Speeding up hardware prototyping by incremental simulation/emulation

We describe a method for the automatic construction of a testbench, able to dynamically communicate a standard VHDL simulator with a logic emulator by means of text files. The proposed approach significantly reduces turn-around times in an emulation based rapid system prototyping environment. In this way, time-consuming logic synthesis and technology mapping steps are moved, in the design cycle, after a previous functional verification.