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Continuous-time quadrature bandpass sigma-delta modulator with capacitive feedforward summation for GSM/EDGE low-IF receiver

This paper presents a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology-which is suited for implementation in low power applications. A new compensation scheme for a polyphase filter is proposed. The summation of feedforward signals is implemented by weighted capacitors, without the necessity of any additional active components. The effectiveness of the proposed architecture is proved on a test chip which was designed in a standard 0.25-mum CMOS technology. The designed SigmaDelta modulator has a power consumption of 2.7 mW at 1.8 V supply voltage, a dynamic range of 90.3 dB and a SNDR of 86.8 dB. The chip is 0.5 times 1.4 mm2 including pads.