{'fraction_non_alphanumeric': 0.020481927710843374, 'fraction_numerical': 0.0, 'mean_word_length': 5.343511450381679, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design methodology for accelerating software executions with FPGA

Reconfigurable logic is a flexible solution for offloading some of computations from a processor. In particular, in applications where small kernels are repeated often, e.g., in DSP. However, the traditional development style for reconfigurable logic is hardware design, while application code for CPU is software, thus there is need for an design methodology for converting software partition to an hardware structure. In this paper, we propose a design method, which can be used to create a FPGA configuration from a software code. The FPGA configuration can be executed in parallel with software execution. The application-specific hardware structures for the FPGA are generated automatically with the required interfaces and device drivers for data transfers.