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A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards

In this paper we present an efficient system-on-chip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable datapath and can be dynamically reconfigured to support multiple 4G standards. We utilize a pipelined version of the layered belief propagation algorithm to achieve partial-parallel decoding of structured LDPC codes. Instead of using the sub-optimal Min-sum algorithm, we propose to use the powerful belief propagation (BP) decoding algorithm by designing an area-efficient soft-input soft-output (SISO) decoder. Two power saving schemes are employed to reduce the power consumption up to 65%. The decoder has been synthesized, placed, and routed on a TSMC 90 nm 1.0 V 8-metal layer CMOS technology with a total area of 3.5 mm2. The maximum clock frequency is 450 MHz and the estimated peak power consumption is 410 mW.