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Design for prototyping of a parameterizable cluster-based Multi-Core System-on-Chip on a multi-FPGA board

Reaching a physical limitation in terms of power consumption, the new chosen axis to increase the performance is to scale the number of processing elements (PEs) instead of increasing the speed of processors. These complex systems often take the form of a Multi-Core System-on-Chip (MCSoC) in which individual nodes are connected using a Network-on-Chip (NoC). FPGA-based prototyping is no longer optional to test these very large designs. A multi-FPGA prototyping board, which is a collection of FPGAs, is used when the logic capacity of a single FPGA is insufficient. Nevertheless, multi-FPGA boards come with some constraints, which lower the system frequency. However, cluster-based MCSoCs have a great value: their flexibility in terms of form factor. In this paper, a parameterizable cluster-based MCSoC with a mesh topology has been designed. An indicator based on the average Rent's Rule of cluster-based MCSoCs has been proposed to predict the best form factor in order to obtain the maximum prototyping system frequency. The targeted prototyping platform is a six Virtex-5 multi-FPGA board. The results show that for a given total number of PEs in cluster-based MCSoCs, a lower indicator can result in a higher system frequency.