{'fraction_non_alphanumeric': 0.03152709359605911, 'fraction_numerical': 0.003940886699507389, 'mean_word_length': 6.055555555555555, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Heterogeneous dual memristive circuit: Multistability, symmetry, and FPGA implementation

An improved heterogeneous dual memristive circuit (DMC) is proposed based on Chua’s circuit, which shows good symmetry and multistablility. For the difficulty in controlling the initial conditions, which restricts the engineering applications, the 3rd-order model (3OM) in flux–charge domain is derived from the 5th-order model (5OM) in volt–ampere domain by using the flux–charge analysis method (FCAM). The consistence of symmetry and multistability before and after dimensionality decreasing is meticulously investigated via bifurcation diagram, Lyapunov exponents, and especially attraction basins. The comparative analysis validates the effectiveness of reduction model and improves the controllability of the circuit. To avoid the noise in the analog circuit, a field-programmable gate array (FPGA) is utilized to realize the reduction model, which is rarely reported and valuable for relevant research and application.