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An improved reversed miller compensation technique for three‐stage CMOS OTAs with double pole‐zero cancellation and almost single‐pole frequency response

This paper presents an improved reversed nested Miller compensation technique exploiting a single additional feed‐forward stage to obtain double pole‐zero cancellation and ideally single‐pole behavior, in a three‐stage Miller amplifier. The approach allows designing a three‐stage operational transconductance amplifier (OTA) with one dominant pole and two (ideally) mutually cancelling pole‐zero doublets. We demonstrate the robustness of the proposed cancellation technique, showing that it is not significantly influenced by process and temperature variations. The proposed design equations allow setting the unity‐gain frequency of the amplifier and the complex poles' resonance frequency and quality factor. We introduce the notion of bandwidth efficiency to quantify the OTA performance with respect to a telescopic cascode OTA for given load capacitance and power consumption constraints and demonstrate analytically that the proposed approach allows a bandwidth efficiency that can ideally approach 100%. A CMOS implementation of the proposed compensation technique is provided, in which a current reuse scheme is used to reduce the total current consumption. The OTA has been designed using a 130‐nm CMOS process by STMicroelectronics and achieves a DC gain larger than 120 dB, with almost single‐pole frequency response. Monte Carlo simulations have been performed to show the robustness of the proposed approach to process, voltage, and temperature (PVT) variations and mismatches.