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Transistor level budgeting for power optimization

We present an optimal budget distribution method for low power circuit design using transistor sizing. The algorithm distributes the available budget inside the functional unit by efficient traversal of the Series Parallel Graph representation. The technique can be efficiently applied at different abstraction levels of the design as well as toward other optimization goals (such as area optimization). The complexity is O(n) in terms of the number of transistors in the circuit. Incorporating our method in the design flow yields significant improvements in power consumption. Experiments on circuits extracted from MCNC91 benchmark suite have revealed improvements up to 59% in average power and 65% in maximum power dissipation compared to an alternative budget distribution algorithm.