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Design and Implementation of Hardware to Perform Testing the Matching Packet Header Based on FPGA

The hardware architecture of the parallel process multiple RAM that emulates the behaviors of content addressable memory for packet classification is presents in this paper. With the increase in Internet networks’ speed, the speed of detection of intruders has become a basic requirement. In this work, a packet header field is used in a fast and efficient way to detect intruders to prevent them from accessing the data. The application test results were fast and compatible when used FPGA board technique from xilinx. Finally, the design, synthesis of this parallel process multiple RAM packet header detector has been achieved using Vivado 2018.2 simulator, and coding is written in Verilog HDL language and implemented on Virtex – 7 FPGA (Field Programmable Gate Array) kit.


Introduction
Packet classification is a forwarding engine that uses the incoming packet header to generate the action as the output, which is usually one of the three decisions (Accept, Deny, or Drop). Therefore, the speed of the forwarding engine must be high enough to process data within the speed of guided media. Many studies have been done in classifying packet headers in the past, and programs have been used to implement various algorithms for classifying packets. Most of them depend on the hierarchical tree decision, which is very efficient in terms of usage memory, easy to create a stratified tree from multiple header fields for rules, and rule updates to enhance the search performance. However, these low-speed algorithms methods become useless due to its delay to the high speed of data and increase the number of rules [1] [2][3] [4]. Another method to test the packet header is to use packet forwarding using multidimensional effective range matching [5]. The traditional router architectures rely on buffer flow architectures to classify packets. The basic idea is that the arrival of packets determines the flows, meaning that if a packet belongs to a new stream arrives, more packets of that stream are expected to arrive soon. Using these expected behaviors, the first beam of streaming is processed by a slow pathway that analyzes the full head. Then the package header is inserted into a cache or hash table with the action to be applied to the first package and all other streaming packages. When subsequent packets arrive in this flow, the corresponding action can be determined from a cache or hash table [6]. Newly work has been moved to use: and encoding rules were set for SRAM-based matches using a bit selection policy. The specified bits from the input key were used to access a base in SRAM for comparison. The results obtained from the header classifier can reach the Throughput of 426 million packets per second.
The main focus of this paper is on building hardware for FPGA-based matching packet header testing. Subsets of RAM components equal to the number of bytes in the IP address were chosen in the packet header to achieve FPGA memory efficiency. Matching packet header testing was designed and implemented with VHDL based on the Virtex -7 FPGA kit. This paper is organized as follows: Section 2 provides an overview of the FPGA memory packet address test with a summary of the procedure. The third section contains an explanation of the corresponding packet header design. The fourth section discusses the implementation of the proposed PH-Matching in the FPGA, and the results of the design. Finally, the conclusion in the final section.

An overview of header beam matching designs using FPGA
As the Internet has evolved towards multi-media applications and quality of service, packet processing has become a prerequisite for the next generation of Internet routers. Significant advances in internet speed have resulted in the rapid transition to higher speed FPGA components, and research in this area indicates a shift in use in packet processing design.
FPGAs put in force high-velocity block-RAM (BRAM) in a silicon substrate. For example, the Xilinx Virtex-6 FPGA carries 720 BRAMs; the Virtex-5 [9] carries 288 at 36Kb and affords working frequencies above 500MHz [10]. Several researchers have used BRAM to implement different algorithms for classification or matching packet headers, each with their advantages and disadvantages. In addition to many papers being done to address the disadvantages of not effectively investing in size of memory, memory has been sub-divided into several small sizes and used with better investment. In addition to high speed and investment of BRAM and to avoid the circuit complexity, it has been made in simulating Triple Content Addressable Memory (TCAM) [11], design TCAM based on SRAM on FPGA. The TCAM compares the input word with all words stored parallel and outputs the address of the stored matched word. TCAM stores words in three states:0, 1,and X (don't care 0 or 1) [12]. Commercial TCAMs are built into an application-specific integrated circuit (ASIC), which features high-speed searches. TCAM has been widely used for designing high-speed search engines and has applications in networks, artificial intelligence, lookup engine, image processing, and many other real-time applications.
The most important packet header fields are the source and destination address, source and destination port range, and protocol field. Typically, packet classification or matching works with three types of input data. It can be a prefix to specify an address, range to specify port numbers, or specify protocols with precision. So Ternary content addressable memories (TCAMs) are the best memory for address matching, while port and protocol matching can be implemented using block RAM (BRAMs). [13]  Despite the advantages provided by the TCAM memory, its implementation based on BRAM memory on FPGA, results in disadvantages that the increase in the word size of TCAM bits results in an exponential growth in BRAM memory usage. And due to the minimum depth limitation of BRAM of 512 × 72 bits, it is required several BRAM to implement a large TCAM word size. For example, the design proposed in [14], requires 56 BRAMs of size 36Kb to implement an 18Kb TCAM.
This disadvantage impact can be reduced by sequencing multiple small SRAM blocks in designing TCAM on FPGA. However, this also leads to decrease operational frequencies. This is specifically due to the complicated-extensive indicators routing among BRAMs and good judgment on account of immoderate utilization of BRAMs and complicated precedence encoding devices synthesized in good judgment slices.

3.The proposed IP matching design based on FPGA RAMs
To take advantage of BRAMs on FPGAs and avoid the circuit complexity and flaws that accompanied others' designs. In this paper, we proposed an IP matching design based on parts of IPv4. They are four parts represented in decimal notation, and each fraction represents a decimal number ranging from 0 to 255 independently of the others. The packet header consists of five fixed fields: source IP address using 4 bytes, destination IP address using 4 bytes, source port number using 2 bytes, destination port number using 2 bytes, and protocols field using 1 byte. Since each byte is independent, it has allocated separate RAM memory to store its contents, also the 16-bits port number has been divided into two bytes to reduce the size of RAM memory as shown in figure 1. The specific prefixes addresses have been converted to a number of direct addresses and previouslystored into related addressable content RAMs (CAM RAMs) shown in figure 1.
The contents of the packet header have been used as the address to read the content of the distributed CAM RAMs, also used as the input to the comparators that compare these inputs with the RAMs outputs, all the RAMs, and comparators circuits run in parallel. The output of the comparators circuits arrives as input to the AND gate, the input header does not match unless all the comparators' results are matches.

Implementation of the proposed packet Header (PH) Matching
In this work, the Vrtix-7 [15] FPGA has been used to implement packet header matching, and according to the use of this new type of FPGA, a new Xilinx tool has been also used, I mean Vivado 2018.2. Xilinx Vivado, is a High-Level Synthesis Kit (HLS), a suite for capturing C ++ based design,  In the running simulation, 80 bits of input data have been used to define malicious clients that should be blocked. these data stored into the 10 CAM RAMs of size 2 8 x8 bits, the "PH_BIT_enb" bit line has been set to write enable to write into the RAMs memory as the initial setting, then the write enables bit, disabled to start the reading the content of memory for the matching process with the new input data. figure 3, shows the waveforms for, write-enabled,the input data, and the red color waveform of matching signal that change from mismatch to match when new data identical to that previously stored has been entered. After the success of the design and implementation of the packet header matching which was used in a fast and efficient way to detect intruders, it prevented them from accessing the data. The two Vivado reports and the project summary can be viewed. The utilization Design Information that contains the slice Logic, a summary of Registers, Memory, Clocking, and other information. Table 1 shows the Slice Logic information. The design uses a small number of LUT and memories.  The parts of report power analysis and report timing summary show the design used low power and the is no timing delay at the inputs or outputs also, there is zero checking multiple clocks register /latch pins. as a result, this report proved there are 81 input ports with no input delay specified; When checking the output delay, there is one port with no output delay. as shown in table 2 parts a and b. As expected, since all CAM RAMs designed to work in parallel.

Conclusion
In this study, was built TCAM based on RAM. We designed hardware architecture of the parallel process multiple RAM that emulates the behaviors of content addressable memory for packet classification to increases speed of detection of intruders on networks and we achieved low power & no Delay in inputs and output with no circuit complexity design. the reports in table 2 (a)&(b) above showing our result. by using Virtex -7 FPGA kit.