{'fraction_non_alphanumeric': 0.020334059549745823, 'fraction_numerical': 0.006535947712418301, 'mean_word_length': 5.263636363636364, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Register allocation compilation technique for ASIP in 5G micro base stations

The currently available compilation techniques are for general computing and are not optimized for physical layer computing in 5G micro base stations. In such cases, the foreseeable data sizes and small code size are application specific opportunities for baseband algorithm optimizations. Therefore, the special attention can be paid, for example, the specific register allocation algorithm has not been studied so far. The compilation for kernel sub-routines of baseband in 5G micro base stations is our focusing point. For applications of known and fixed data size, we proposed a compilation scheme of parallel data accessing, while operands can be mainly allocated and stored in registers. Based on a small register group (48×32b), the target of our compilation scheme is the optimization of baseband algorithms based on 4×4 or smaller matrices, maximizing the utilization of register files, and eliminating the extra register data exchanging. Meanwhile, when data is allocated into register files, we used VLIW (Very Long Instruction Word) machine to hide the time of data accessing and minimize the cost of data accessing, thus the total execution time is minimum. Experiments indicate that for algorithms with small data size, the cost of data accessing and extra addressing can be minimized.