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Exploration of different implementation styles for graphene-based reconfigurable gates

The exceptional electro-mechanical and optoelectronic properties of graphene have recently been exploited to devise a novel switching device that allows steering carriers from input to output; this device, called Reconfigurable Gate (RG) naturally behaves as multiplexer yet with better performance, area and power compared to one implemented with traditional CMOS technology. This RG could become a popular choice among the many emerging technology devices thanks to its flexibility and efficiency; however, its widespread adoption requires significant research on the automation of the design process, including modeling, optimization, and synthesis. In this work, we focus on synthesis, and specifically on the implementation style of designs that use RGs. We compare three different styles, namely a traditional standard cell flow, one using a direct mapping from BDD representations, and a third one based on a Look Up Table (LUT)-based implementation. We analyze the performance, area and power consumption of benchmarks synthesized using the three different styles, and compare to a bulk CMOS implementation. The results show that RG-based circuits are superior w.r.t. CMOS, and that the choice of the implementation style strongly affects the quality of the results.