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Gate Insulator Inhomogeneity in Thin Film Transistors Having a Polycrystalline Silicon Layer Prepared Directly by Catalytic Chemical Vapor Deposition at a Low Temperature

Polycrystalline silicon (poly-Si) films were prepared directly at a low temperature (<200 °C) by using catalytic chemical vapor deposition (Cat-CVD) technique without subsequent crystallization steps. Top-gate coplanar type thin-film transistors were fabricated using the as-deposited poly-Si films. We obtained a high mobility of ∼40 cm2/(V s) and a subthreshold slope of 0.54 V/decade. Instability in threshold voltage with the drain bias could be suppressed by improving the homogeneity in the gate insulator.