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Extraction of Gate Resistance in Sub-100-nm MOSFETs With Statistical Verification

This paper presents an improved z-parameter based approach to extract the gate resistance at low frequencies. The effectiveness of this approach, compared with other y-parameter based approaches, is verified using 430 samples fabricated in 40-, 55-, 90-, and 110-nm CMOS technology nodes. The influence of the nonquasi-static (NQS) effect, resulting from the distributed channel resistance, on the gate resistance extraction is studied, and the optimum processes are suggested to reduce the NQS effect. Finally, the extraction of the channel resistance in the lightly doped drain region is also presented.