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Impact of Dot-Size and Dot-Location Variations on Capacitance–Voltage Characteristics and Flat-Band Voltage Shift of Quantum-Dot Non-Volatile Memory Cells

This article performs three-dimensional simulations to analyze capacitance versus voltage (C–V) characteristics of metal–oxide–semiconductor (MOS) capacitors including nano-scale Si quantum dots inside the insulator. It is anticipated that performance of nonvolatile memory in use of Si quantum dots is strongly influenced by the dot-size variation, the dot-depth variation, and the dot-layout variation. Accordingly, the impacts of the variation in the physical parameters of Si quantum dots on C–V characteristics are simulated assuming symmetric and asymmetric distributions of the physical parameters. It is shown that the C–V characteristics of a MOS capacitor with Si quantum dots whose depths are somewhat distributed can be approximately estimated by assuming that the Si quantum dots are uniformly allocated with averaged depth. It is also revealed that the impact of the size variation of quantum dots on the C–V characteristics becomes more significant as the average size of the quantum dots increases. On the other hand, it is demonstrated that the C–V characteristics of a MOS capacitor having Si quantum dots with a certain size variation can be well reproduced by summing some typical capacitance components that are weighed with the quantum dot size distribution function. It is revealed that in-plane variation of quantum dot allocation yields a weak impact on the C–V characteristic. Quantum mechanical simulations suggest that reverse engineering can be applied to analysis of the variation of quantum dot size and depth.