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Transistor, Cell, and Interconnect Modeling: Basics to Advances

Description: An understanding of recent transistor, cell, and interconnect models that address the primary physical phenomena impacting design at the 65nm technology node and beyond is essential for CAD engineers, developers, and researchers. In the transistor modeling space, a new standard has emerged with the acceptance of the surface potential-based MOS model, PSP, by the Compact Modeling Council. Surface potential-based models are more physical than previous threshold voltage based models and offer higher accuracy for digital, analog and RF applications. In addition, modern transistor models are required to cover new physical phenomena relevant to state-of-the-art process technologies, like quantum mechanical confinement, gate leakage, non-quasi static effects, strain Si, lateral doping gradient effects, etc., while fulfilling the conflicting requirement of sufficient accuracy and solution speed for practical circuit simulations. Similarly, current-source-based cell models (CSMs) capable of implicitly handling nonlinear input waveforms, active receiver and interconnect loads, cross-capacitance, multiple input switching effects, and supply variation are receiving increased attention with the adoption of CSM variants by major EDA vendors in their timing analysis and library characterization offerings. With the dominant role of interconnects in determining integrated circuit performance, an in-depth understanding of RC (and L) extraction is essential. Furthermore, with the emerging importance of variations induced by manufacturing processes, variational interconnect modeling and extraction techniques are an active research topic. This tutorial which covers modeling basics in addition to the most recent advances is intended for novices as well as experts from associated fields.