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Power reduction strategies for DRAM used in data centric applications

To catch up pace with development in processors, power consumption of a memory module is often amortized for higher bandwidth and lower latencies. As a result memory module consumes a major fraction of total power consumption in a system. This has led to low power design. This paper will evaluates three new DRAM interface, viz. MemBlaze, MemCorrect and MemDrowsy, developed at Stanford University, USA. Paper intends to extract out know-hows, tradeoffs incurred, and energy saving mode, hardware overheads and application area of the interfaces. All the three architectures work on reducing wakeup latencies of a Power-Up mode in DRAM, thus allowing the DRAM to use their Power-Down modes rigorously. The technique is capable of reducing the background power consumption up to 50%. The interface finds its application in the field which demands heavy memory usage like that of data centric applications, server memories, handling Big Data and Online Transaction Processing (OLTP) and Online Analytical Processing (OLAP).