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VLSI oriented asynchronous architecture

In order to realise dedicated functions that have no special parallel algorithms for efficient full custom VLSI implementation, we propose an asynchronous architecture that consists of several asynchronous functional modules and controls the chip by the local communication among these functional modules. As this architecture is very suitable for mapping from the behavioral specification described by the software onto silicon, it is very useful as a target architecture for silicon compilers.
This paper describes the concept and the VLSI implementation of the asynchronous architecture. An evaluation of the size and the execution speed of chips based on this architecture model is also described.