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Exploring the Cache Design Space in a Multithreaded Processor

Multithreading can be used to hide latency in a non-blocking cache architecture. By switching execution form one thread to another, the CPU can perform useful work, while waiting for pending requests to be processed by the main memory. This frequent context switching however, produces a very irregular memory referencing pattern. In this paper we examine the effects of associativity and block size on cache performance in such a hostile environment. We find that for associativity equal to the number of threads, the cache produces very low miss rate even for small sizes, which helps improve the performance of the processor. By increasing the block size to more than 32 bytes, although the miss rate is reduced, the processor performance degrades with a given memory bandwidth.