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Stacking Dies: Combined Virtual Prototyping and Reliability Testing Based Design Rules

Since the last 2-4 years, the focus in microelectronics is gradually changing from front-end to packaging. More added values are put into packages, where System in Packages (SiP) is an answer for the ongoing function integration trend. In SiP several dies are placed into one package, either side-by-side or on top of each other. The miniaturization trend more or less forbids placing dies side-by-side, since it will make the package larger. Several stacking die concepts exist, in this paper we have investigated two different ones: silicon spacer versus ball spacer. In the silicon-spacer concept, a thin piece of silicon is used to separate the actives dies in the stack. In the glue-spacer concept this is accomplished with a filler-filled die-attach. Virtual prototyping techniques are used to explore the stress/strain hotspots for different package types, being QFN, BGA, QFP, and LQFP using both stacking concepts. It is found that the QFN package type has the highest stress levels compared to BGA and QFP. Optimization techniques are used to explore the design space of the worst-case package type. For example, it is found that the spacer thickness should be equal or thinner than the die stacked on top of it to prevent the occurrence of die crack. Standard qualification experiments on specific worst-case design will be conducted in future to verify the calculated responses. By combining virtual prototyping techniques with smartly chosen reliability tests allows that possible failure mechanisms within stacked die SiP packages to be better understood and thus prevented.