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Nanoscale Transistors—Just Around the Gate?

Advanced geometries for gate electrodes that reduce current leakage can decrease the size of high-performance transistors. Further reduction in the size of the metaloxide semiconductor field-effect transistors (MOSFETs) used in computer chips will require more complex geometries to enhance the gate control of the current flow in the transistor channel (1). These advanced designs allow transistor scaling (maintaining performance as size decreases) and minimize the leakage of current when the device is in the off-state. The voltage of operation can be reduced without loss of performance, making the devices function with less power dissipation per operation. The optimal MOSFET geometry surrounds a cylindrical channel with the gate electrode (2). This “gate-all-around” (GAA) enhances electrostatic control of the entire channel surface (see the figure), and when used with superior charge transport materials, should deliver enhanced performance. Franklin et al. (3) now report on nanoscale complementary MOSFETs in which suspended single-walled carbon nanotubes (SWCNTs) form the channel with a GAA geometry. This work marks a milestone in moving SWCNT nanoelectronics from laboratory prototypes toward a manufacturable technology.