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MIP-based detailed placer for mixed-size circuits

By modifying an existing Mixed Integer Programming (MIP) model for optimizing the placement of cells in sliding windows, we develop a detailed placer for large-scale mixed-size circuits. To make it possible to optimize the placement of larger sliding windows in reasonable time, we reduce the number of integer variables in the modified MIP model such that when compared with the original complete MIP model, the solution time is shortened greatly while the solution quality does not degrade much. Experimental results on DAC12 benchmark circuits show that our detailed placer manages to further reduce half-perimeter wirelength (HPWL) of the placement results generated by many other existing detailed placement techniques. Moreover, by making use of a commercial router, we also evaluate the routability of the placement results before and after the application of our detailed placer. Both the routed wirelength and the number of vias in routing solutions are reduced, while the number of design rule violations does not change much for most circuits, implying the routablity of placement results are not perturbed.