{'fraction_non_alphanumeric': 0.023868312757201648, 'fraction_numerical': 0.0, 'mean_word_length': 5.4, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed

FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. Actual-delay circuits operate according to the actual, physical device delays of the FPGA device components and not according to STA predictions, exhibit data-dependent delay,latency and output completion detection, and can thus detect when their outputs are ready to be latched. In this paper we demonstrate an FPGA flow, based around existing FPGA tools, capable of implementing actual-delay circuits, and through worst-case, upper-bound analysis show that such circuits exhibit reduced delay and higher performance than their conventional counterparts. The FPGA flow incorporates a logic synthesis transformation step for converting a conventional single-rail circuit to monotonic, dual-rail and a LUT mapper for mapping the latter to LUTs while preserving monotonicity. In addition, through our implementation of actual-delay circuits we are able to measure intra and inter-FPGA timing margins and we present results on the STA margin and timing deviation over four devices