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Hardware reduction in delta-sigma digital-to-analog converters via bus-splitting

This paper discusses a bus-splitting technique for hardware reduction in error feedback digital delta-sigma modulators (DDSMs). The technique is based on error masking and is applied to DDSMs with sinusoidal inputs. We consider the components that contribute to the output signal-to-noise ratio in conventional DDSMs and review new architectures for implementing the digital algorithms without sacrificing performance.