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Rise time reduction of high speed digital signals on interconnects of the CMOS 45 nm node by optimizing interconnect inductance

High speed digital signals propagated on interconnect require short rise times in order to guarantee high clock frequency (higher than 4 GHz) and put an upper limit on IC's consumption. Interconnect of the 45 nm node suffer from limited bandwidth because of their high resistance and capacitance. By inserting serial inductance between portions of considered interconnects, bandwidth is increased and thereby rise times are reduced. Criterion to set the optimal inductance which reduces rise times without degrading signal integrity or increasing propagation delays is proposed.