{'fraction_non_alphanumeric': 0.03664921465968586, 'fraction_numerical': 0.008726003490401396, 'mean_word_length': 4.979166666666667, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Characteristics of Dual-gated Poly-Si Junctionless Nanowire Transistors with Asymmetrical Source/drain Offsets

In this paper, a novel gate-all-around (GAA) junctionless (JL) nanowire (NW) transistor with dual gate was proposed, fabricated and characterized. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end.