{'fraction_non_alphanumeric': 0.02294792586054722, 'fraction_numerical': 0.00088261253309797, 'mean_word_length': 5.230769230769231, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing

Prebond TSV testing is a powerful technique to identify faulty TSVs prior to 3-D stacking and to boost up the chip yield rate significantly. Existing prebond test methodologies experience fault detection resolution challenges, large implementation overheads, and most importantly, wide performance fluctuations in presence of process corners, supply voltage, temperature (PVT) variations. In this work, we propose a no-touch TSV test methodology that is resilient against PVT variations, or test environment parameters, thus suitable for industry practical uses. The proposed methodology is based on the idea of charging the TSV RC-network and counting the number of voltage pulses required to charge up the TSV. We undertake a detailed performance evaluation of the test methodology by adopting state-of-the-art industry technology parameters. The major advantage of the test methodology is its strong resilience to PVT variations and simplicity of implementation. In addition, a DFT circuitry is proposed to share among a group of TSVs to lower the design overhead.