{'fraction_non_alphanumeric': 0.044709388971684055, 'fraction_numerical': 0.020864381520119227, 'mean_word_length': 4.1692307692307695, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A 3.4-Gbps clock and data recovery circuit with a forwarded clock in a 0.13-μm CMOS technology

A clock and data recovery (CDR) circuit has been developed for a clock-forwarded 3.4-Gbps serial link. The loss of the signal channel is compensated by a linear equaliser whose output is applied to eight samplers which provides edge- and data-samples of the serial data input. Based on the edge- and data-samples, the phase of a voltage-controlled oscillator (VCO) running at one-fourth of the data rate is adjusted to get the optimum eight-phase sampling clocks. Implemented in a 0.13-μm standard CMOS process, the CDR circuit shows the bit-error rate (BER) less than 10−15.