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On Modelling and Analysis of Receive Livelock and Cpu Utilization in High-Speed Networks

Abstract Under heavy network traffic such as that of Gigabit Ethernet, interrupt-driven kernels can perform very poorly. Application processes can starve as CPU bandwidth of network hosts is consumed by the overhead involved in handling interrupts and processing incoming packets. The potential of having a high network bandwidth has little value in practice if no CPU power is left for applications to process or forward data. In addition, the system throughput can significantly be degraded, resulting in a receive-livelock condition. In this paper, we present analytical study of receive livelock and CPU utilization. We develop analytical models based on queueing theory and Markov processes. We consider and model three systems: ideal, PIO, and DMA. In an ideal system, the interrupt overhead is ignored. In PIO, DMA is disabled and the CPU performs copying of incoming packets. In DMA, copying of incoming packets is performed by DMA engines. Our analysis work can be valuable for engineering and designing certain system parameters. It becomes prudent to understand and predict how a host system behaves and performs when subjected to high network traffic. Good overload behaviour is critical. Simulations and reported experimental results show that our analytical models are valid and give an adequate approximation.