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Stage-based frame-partitioned parallelization of H.264/AVC decoding

Strong demands for high resolution video services lead to active studies on high speed video processing. Especially, widespread deployment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a homogeneous multi-core platform. Parallelization of H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Stage-based Frame-Partitioned Parallelization (SFPP). In SFPP, we divide a frame into multiple partitions, and execute them in a pipelined fashion. To reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition (HD) and a full high-definition (FHD) video, respectively compared with that of a popular existing method.