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A tool for automated analog CMOS layout module generation and placement

Layout design is a very important step of the analog CMOS IC design flow. Good layout quality featuring low susceptibility to digital noise and low sensitivity to process variation requires layout designers with significant expertise. The layout optimization process needs new CAD tools that will quickly generate multiple versions of analog CMOS IC layouts for parasitic extraction and post-layout simulation. We propose a new CAD tool that will produce analog CMOS layout modules in a given CMOS process. Multiple use of the tool with different control parameters results in obtaining several versions of CMOS layout modules of a single circuit. These layouts can be used for post-layout simulation and layout optimization. This paper presents the tool's architecture and examples of its use for analog CMOS layout design.