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Implementation of DES using pipelining concept with skew core key scheduling in secure transmission of images

Digital image processing is a very expanding area with applications reaching out into various fields such as defence, medicine, space exploration, authentication, automated industry inspection and many more areas. Many digital communication systems require reliable security in processing and transmission of digital images. The fast development of internet in the digital world demands more concern in to the security of digital images and have attracted much attention [1]. Encryption of digital images is the preferred way while transmission and can be used to frustrate opponent attacks from unauthorized access. Digital images are exchanged over various types of networks related to a number of purposes. The data to be transmitted may be very confidential in nature. Many encryption methods are now available to encrypt and decrypt confidential data's[2].Here we uses a block cipher, a modified DES algorithm, which is enhanced by implementing pipelining concept and skew core key scheduling to encrypt images which provide faster encryption rates and high throughput. The hardware implementation of the design is also made and compared with various FPGA devices.