{'fraction_non_alphanumeric': 0.02540220152413209, 'fraction_numerical': 0.002540220152413209, 'mean_word_length': 6.120481927710843, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Heterogeneous Multi-core SoC Implementation with System-Level Design Methodology

The trend towards heterogeneous multi-core integration and higher communication bandwidth drastically increases the complexity of the SoC. Architecture design and system validation become extremely challenging. This paper presents a multi-core computing platform which consists of general-purpose microprocessor and dual programmable digital signal processor (DSP) cores for multimedia applications. To demonstrate its outstanding performance and energy efficiency, we develop multimedia and image processing applications, such as H.264 decoding and object detection, on this multi-core computing platform. In addition, to evaluate the system performance and energy efficiency, electronic system-level (ESL) design with power information is conducted for the embedded system evaluation. According to the experimental results, the system-level virtual platform can assist the hardware engineers and software engineers to enhance the multi-core platform performance and application efficiency, respectively. The system-level design methodology benefits to the embedded multi-core design are discussed.