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New approaches for synthesis of redundant combinatorial logic for selective fault tolerance

With shrinking process technologies, the likelihood of mid-life faults in combinatorial logic is increasing. Approximate logic functions are a promising approach to mitigate such faults as the technique can be applied to any digital circuit, it protects against multiple fault models and offers a trade-off between increased area and fault coverage. In this paper we present a new algorithm for generating approximate logic functions. The algorithm considers the failure probabilities of the gates and it uses a sum of product (SOP) representation. The results on some circuits show that FIT rate can be reduced by 75% with an area penalty of 46% and inserting only two additional layers of logic.