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Design and Implementation of a 32-bit RISC Microprocessor

History has marked a large number of man endeavours towards building machines that are capable of performing arithmetic operations more efficiently than he can do himself. These started with very primitive instruments but evolved over the course of time due to the accumulative knowledge of man kind. In the recent decades, many computer architectures exhibiting various design methodologies and computation models have been developed. One of the most widely accepted of which is von-Neumann architecture. The brilliant mathematician, John Louis von-Neumann (1903 1957) proposed in 1945 a model for a general purpose computer that provides programmability and re-programmability thanks to a memory structure that stores programs and data. This thesis introduces Micro6, A microprocessor that adopts vonNeumann architecture and is implemented on FPGA. In addition to that, the thesis presents a software development environment for Micro6. Micro6 exhibits the characteristics of a RISC (Reduced Instruction Set Computer). It has a small set of instructions and a limited number of addressing modes. Micro6 control unit follows the conventional model as opposed to the microprogrammed one. Micro6 can perform arbitrary computations on integer data but however, the size of the program is constrained by the size of the memory. An I/O Unit is attached to Micro6 which facilitates basic I/O as well as DMA (Direct Memory Access) transactions. Writing programs in high-level language like C is not supported by Micro6. However, this thesis introduces an assembler, known as VAS, that supports the assembly language of Micro6. The assembler output files can be used for both simulation and implementation purposes. VAS can be used to write programs that exploit almost all the microprocessor hardware resources. This is very important in the development stage.