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Efficient architecture and scheduling technique for pairwise sequence alignment

A novel efficient hardware architecture to optimize the execution time of dynamic programming-based (DP) pairwise sequence alignment algorithms in hardware is proposed. It is realized by introducing an efficient overlapped scheduling of alignment matrix computation and substitution coefficients pre-loading onto processing elements (PEs) in folded systolic arrays. A new metric is also proposed as an independent performance evaluator to compare different core implementations on different FPGA platforms fairly. Implementation results show that the new hardware architecture for sequence alignment achieves a minimum of 40 percent area normalized speed-up compared to the state-of-the-art hardware implementation, with the speed-up growing linearly with the number of folds e.g. 120 percent speed-up for 16-fold. Compared to equivalent software implementations, the novel hardware architecture achieves a minimum of 103x speed-up, with the speed-up growing linearly with the number of folds e.g. 140x speed-up for 20-fold.