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A research of heuristic optimization approaches to the test set compaction procedure based on a decomposition tree for combinational circuits

In this paper an improved procedure of compaction of a test set for combinational circuits is considered. The goal of optimization is to exclude a covering step from the earlier proposed method. In result we will have a heuristic algorithm which will work much quicker and will suppose a lot of possible future improvements and wide space of further development. The compaction procedure is oriented to a test set that represented as set of test cubes. The main idea of compaction a test cubes is to find all the maximally compatible subsets by constructing a decomposition tree. We will consider the practical applications, experiments and evaluative analysis.