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Design Flow for The Implementation of Obfuscated Finite State Machines

Hardware obfuscation is a useful technique for IP (intellectual property) protection. Several previous works have paid attention to the design of obfuscated FSM (finite state machine). Their common way is to insert an extra obfuscation mode to prevent the attackers from entering the normal mode. Based on the concept of obfuscation mode, in this paper, we study the design flow for FPGA implementation. The proposed design flow includes two main steps: RTL coding (for the obfuscation mode) followed by FPGA synthesis. Experiments with a real circuit show that the FPGA implementation can work without any degradation on circuit speed.