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Three‐dimensional analytical modeling and performance analysis of triple material trigate silicon‐on‐insulator MOSFET

The semiconductor industry has implemented the technique of wrapping the gate electrode on different sides of channel to mitigate the degrading electrostatic effects in nanometer transistor. Intel adopted trigate architecture, wherein the channel is surrounded by gate electrode on three sides to improve the gate control over the channel. In order to further enhance the performance and diminish the short channel effects, triple material trigate silicon‐on‐insulator (SOI) MOSFET is explored in this work. An analytical model to determine the device electrostatics and match deviations due to device geometry has also been developed. The consequence of quantum confinement effects (QMEs), which arise due to ultra‐thin body structure, on the inversion charge and threshold voltage has also been included. Thus, the analytical model presented in this work is based on a self‐consistent solution of three‐dimensional Poisson's equation and two‐dimensional Schrodinger equation with proper boundary conditions. The model is verified by the uniformity obtained between the results from analytical model and TCAD simulations. The superiority of the device has been demonstrated by comparing performance parameters like potential distribution, field variations, drain induced barrier lowering (DIBL) with already existing device structures like single material trigate (SMTG) and dual material trigate (DMTG) SOI MOSFETs