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Methods for the Charge Pump Power Efficiency Improvement in Triple Well Technologies

Four methods for the charge pump (CP) power efficiency improvement are presented in this paper, where the high voltage MOSCAP transistors as capacitors are used. In the chosen 55 nm triple well technology, the MOS transistors have a high-voltage p-well (HVPW) and a deep n-well (DNW) doping regions introducing high parasitic capacitances directly responsible for low power efficiency. With the new approach, the so-called deep n-well switching technique, the efficiency is increased by approximately 12.5% with schematic extracted simulation in Cadence (maximum efficency of 34.55%), compared to the case when the deep n-wells of the CP capacitors are biased from the power supply voltage (maximum efficency of 22.09%), which is the typical approach in semiconductor industry when all parasitic diodes are reverse biased between the power supply and ground.