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Low Power Design Technique in Passive Tag to Reduce the EMD Noise for Reliable Communication with Reader

This paper describes the digital design technique to reduce electromagnetic disturbance (EMD) noise generated by a passive tag, Proximity Integrated Circuit Card (PICC) while processing commands issued by a reader, Proximity Coupling Device (PCD). The higher EMD noise reduces reliability of communication if its frequency falls close to the sub-carrier modulation frequency of 848KHz, which is generally observed at low field strengths. The proposal uses voltage sensor to detect the higher EMD noise and adjusts the clock-gating of the digital design. The voltage sensor output is monitored to detect a pattern, which eventually scales to an EMD noise. Based on the pattern, a pre-defined clock-gating is applied to shift the EMD noise frequency from 848KHz to 3.39MHzThe mixed-signal simulation shows 4mV peak EMD noise reduced to 1mV with the solution and the same has been confirmed by silicon validation. The clock-gating impacts the command processing time, which is increased at low field strengths.