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Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration

In this paper, we discuss the potential foundry announced integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FDSOI). The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next-generation voltage-controlled magnetic anisotropy MTJ are separately integrated into a 28-nm FDSOI process as the MRAM or magnetoelectric random access memory (MeRAM)-on-FDSOI integration. Micromagnetic and electrical simulations are used to evaluate the performance of hybrid circuits. Circuit-level design strategies are explored that use FDSOI leverage and spin-device characteristic to realize writing and sensing power-delay efficiency, robust, and reliable performance in the one-transistor one-MTJ MRAM/MeRAM bit-cell and sensing circuits. Reliability issues are discussed. Process variation and aging resilience strategies, e.g., step-wise back-bias, flip-well re-configuration, and write assist, are proposed to address failure and aging degradation in the MRAM/MeRAM-on-FDSOI integration. A qualitative summary demonstrates that the MRAM/MeRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration.