{'fraction_non_alphanumeric': 0.04141104294478527, 'fraction_numerical': 0.004601226993865031, 'mean_word_length': 5.278846153846154, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Impact of size variation in junctionless vs junction planar SOI n-MOSFET transistor

In this paper, the effect of silicon body thickness (TSi) and silicon body width (WSi) variation on DC characteristics in 100 nm gate length silicon-on-insulator (SOI) junctionless (JL) and junction transistors has been investigated by using numerical simulations. The digital figure-of-merits characteristics such as threshold voltage (VTH), on-current, subthreshold voltage, and drain-induced-barrier-lowering are the main parameters that have been investigated. Based on the simulations, the JT device is less sensitive to variation of TSi and WSi compared to JLT.