{'fraction_non_alphanumeric': 0.028553299492385786, 'fraction_numerical': 0.0006345177664974619, 'mean_word_length': 5.384615384615385, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Enhanced Candidate Selection Algorithm for Analog Circuit Verification

In latest years, the complexity and applicability of modern Integrated Circuits (ICs) grew exponentially, hence the high-pressure to deliver IC designs faster on the market. For safety, a design meeting its specification under any allowed operating condition and fabrication variation is a prerequisite. Therefore, pre-Silicon (pre-Si) analog IC verification is an extremely important task, as in certain regions of this large parameter space, the device exhibits degraded performance, or it fails completely. During verification, a designer must find these regions of the input parameter space where the circuit fails. Ideally this must be done during pre-Si phase, to avoid potential huge re-design delays during prototyping or production. In this context, this paper presents a Machine Learning (ML) approach, where we sample the input space to offer good initial coverage of the operating conditions (OCs) hyperspace, with a small number of simulations. We denote one input of a circuit as an Operating Condition. We then leverage a ML-surrogate model of the circuit instead of time-consuming simulations to propose, during a candidate selection phase, new circuit worst cases, where the circuit fails. After updating the candidate proposal algorithm to include a Gradient Descent (GD) step, we highlight the performance improvement of this new method on synthetic circuits, where we obtain relative absolute verification errors below 1%, while using less simulations than other classical approaches.