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The impact of energy barrier height on border traps in the metal insulator semicondoctor gate stacks on III–V semiconductors

We investigated the effect of a thin interfacial layer (IL) made of silicon or germanium between high-k dielectrics and III–V semiconductors on the frequency dispersion of the capacitance–voltage (C–V) curves in detail. We demonstrated experimentally that the frequency dispersion at accumulation voltage is strongly dependent on the energy barrier height (ΦB) between high-k dielectrics and semiconductors. It was revealed that the improvement of frequency dispersion for n-type III–V semiconductors with IL is attributed to the increase in ΦB realized by inserting Ge IL. Moreover, the border trap density did not necessarily decrease with IL through the assessment of border trap density using a distributed bulk-oxide trap model. Finally, we proved that it is important to increase ΦB to suppress the carrier exchange and improve high-k/III–V gate stack reliability.