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Modifying FPGA Design Flow for Achieving better Circuit Optimizations

Logic synthesis in FPGAs has a well-defined design flow that starts with design entry and goes through different phases like translation, mapping and place & route. While a designer may drive the synthesis process towards a particular optimization goal, the optimization strategy as such is not transparent. In this paper, we modify the traditional design flow and include some additional phases prior to the design entry. While the synthesizer still uses its own strategies during the implementation, the inclusion of these phases allows the designer to have some manual intervention in the mapping process. We have detailed out a case study regarding the implementation of binary adders based on the modified FPGA design flow. Experimental results using Xilinx Virtex-5 FPGAs show a subsequent improvement in performance. Several other circuits designed using the modified FPGA design flow show an improvement in different performance parameters as well.