{'fraction_non_alphanumeric': 0.06688963210702341, 'fraction_numerical': 0.019230769230769232, 'mean_word_length': 4.925742574257426, 'pattern_counts': {'":': 0, '<': 1, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Flip-Mirror-Rotate: An Architecture for Bit-write Reduction and Wear Leveling in Non-volatile Memories

This paper proposes Flip-Mirror-Rotate (FMR), an architecture for bit-write reduction and endurance enhancement in emerging non-volatile memories (NVMs). FMR comprises three components: adaptive Flip-N-Write (aFNW), Mirror-N-Write (MNW), and Rotate-N-Write (RNW). aFNW and MNW focus on word-level bit-write reduction, which reduces NVM dynamic energy while also improving endurance. RNW is an intra-word wear leveling scheme that operates at cache line granularity. The proposed FMR architecture is integrated with frequent pattern compression (FPC) to simultaneously reduce bit-writes and wear in NVMs. Trace-based simulations of the SPEC CPU2006 benchmarks show that for the same memory overhead and < 1% loss in memory bandwidth, FMR reduces bit-writes (dynamic energy) by 48% (29%) in comparison to classical read-modify-write (DCW), 39% (13%) in comparison to Flip-N-Write (FNW), and 21% (14%) in comparison to FPC. Simultaneously, FMR also reduces the peak bit-writes per cell by 47% in comparison to DCW, 34% in comparison to FNW, and 47% in comparison to FPC, improving NVM endurance.