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Verification Planning to Functional Closure of Processor-Based SoCs

Functional verification consumes more than 70% of the labor invested in today’s SoC designs. Yet, even with such a large investment in verification, there’s more risk of functional failure at tapeout than ever before. The primary reason is that the design team does not know where they are, in terms of functional correctness, relative to the tapeout goal. They lack a functional verification map for reference that employs coverage as its primary element.