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Improving Student Comprehension with Logisim-based RISC Processors

This Work in Progress paper in Innovative Practice details continued efforts to improve student comprehension of computer architecture across MIPS and ARM. Students majoring in Computer Science at the United States Air Force Academy (USAFA) are typically enrolled in the department’s Computer Architecture course during the spring of their sophomore year. These students traditionally struggled to understand exactly what was occurring in the Central Processing Unit (CPU) of a computer and demonstrated poor performance on assignments, tests, and the final exam on these concepts. Other institutions have had success giving their students a series of assignments which culminate in their implementing a complete CPU architecture in a logic simulator. However, this fairly time consuming assignment was not deemed feasible at USAFA where student time is divided between various required duties, academics, and athletics. The authors’ previous work showed that providing students with a reduced version of the MIPS (Microprocessor without Interlocked Pipelined Stages) single cycle architecture (SCA) implemented in Logisim increased student comprehension as it allowed them to observe the internal processor operations at a very detailed level. In 2021, the course switched from MIPS to ARM, and students were not provided with this tool and their performance on assessments regressed. In 2022, students were provided with a simulated ARM processor built in Logisim to recreate the improved performance from the MIPS tool. The paper shows five years of data across multiple instructors, virtual/in-person learning, different architectures, and various texts showing that observing simulated processors improves overall student performance with very little additional work from the instructors or the students.