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A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers

This paper proposes a new scheme utilizing a small offset-voltage (Vos) sense amplifier (SA) to reduce the deterioration of the read speed and cell stability at low power supply. This concept has been introduced to realize a low-voltage-operation SRAM with a small area penalty. The transistor threshold voltage (Vth) shift caused by hot carrier injection (HCI) is used for Vos trimming after chip fabrication. This scheme is observed to become more effective when repeated trimmings are applied. The SA with offset trimming circuit is implemented in 40-nm CMOS technology, and the reduction in the Vos by 76 mV is confirmed using the measurement and simulation results. This reduction corresponds to a 40% improvement in the read frequency and a 6× improvement in the failure rate at 0.6-V supply voltage.