{'fraction_non_alphanumeric': 0.023062730627306273, 'fraction_numerical': 0.0036900369003690036, 'mean_word_length': 5.095505617977528, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Clock Skew Optimization for Voltage Variation

Clock skew minimization has been extensively studied. However, the problem is still difficult to resolve because clock skew needs to satisfy many different environmental corners. It has been known that optimizing skew at one corner may cause violation at another corner. Traditionally, skew optimization may require iterations of optimization among various corners which can take very long time or even fail the constraints. We observe in several real designs that the clock skew problem can be easily solved if the library has special clock buffers. In this paper, we propose a novel buffer design called wide-divergence buffers (WDBs), whose delay under the low voltage (the worst corner) is about several times of the delay under the high voltage (the best corner). We first describe how a WDB can be implemented using analog techniques. Then, we also propose an efficient optimization framework for WDB customization. Our experimental results consistently show that the total negative slack (TNS) reduce 84.23% for industrial design.