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Built-in self-repair architecture generator for digital cores

Built-in self-repair (BISR) concept is widely utilized and proven by industry to increase the reliability of regular structures such as memory cores. The idea of using this concept in mostly irregular structures such as logic cores is quite new and represents a challenging task with many problems involved; e.g. the identification of regular parts in a logic core suitable for reconfiguration, excessive area overhead and complexity of reconfiguration logic, etc. Current promising solutions for an efficient BISR architecture design are based on reconfigurable logic blocks (RLBs). In this paper, a new automated generator of the adequate BISR reconfiguration architecture is proposed. The generation process input is a simple description of arbitrary logic core already divided into RLBs and the generated output is the synthesizable HDL description of the BISR architecture for the core.