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Experimental and theoretical verification of channel conductivity degradation due to grain boundaries and defects in 3D NAND

In this paper, Epi-Si process is used to investigate the impact of traps and grain boundaries in vertical 3D NAND. With this channel morphology, we show that the defects have a reduced impact on device performances compared to the usual poly-Si channel devices. These results are also confirmed and extrapolated to other geometry using 3D TCAD simulations.