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Plating challenges associated with high-density fan-out (HDFO) technology

High-density fan-out wafer-level packaging (HDFO WLP) is an emerging technology, promising smaller form factors and lower cost compared to traditional WLP applications. However, the process of plating large features employed as interconnects in this approach often encounters mass transport limitations that can curtail the deposition rate. In this work, this effect is explored in detail via computational modeling. The aspect ratio of through-resist features is shown to have a severe impact on minimum fill time, where a high (4:1) aspect ratio feature takes more than 7.5 times as long to fill as a low (1.2:1) aspect ratio feature. Convection of the electrolyte above the surface of the photoresist, which is largely influenced by the plating reactor design, is shown to have a pronounced impact on fill times over the range of feature dimensions modeled.