{'fraction_non_alphanumeric': 0.018556701030927835, 'fraction_numerical': 0.003092783505154639, 'mean_word_length': 5.79020979020979, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Deflection routing in multi-channel photonic network on chip architecture

Ultralow-latency and less power consumption have become necessary in multi-processor interconnection network on chip, photonic interconnection as a solution to meet above requirement, provides high performance interconnection on chip. But the photonic network on chip architecture design and performance is limited because photonic interconnection hasn't buffer, photonic network architecture must be designed to relieve this limitation. In this paper, we present a multi-channel photonic network on chip architecture employing deflection routing, optical data packets can inject/eject from processor core by four channels at the same time. Simulation result shows this network architecture has 60% latency decrease compared to generic photonic network on chip, and the photonic network architecture is only consume 7% power of the electronic interconnection network on chip with the same scale.