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Using At-Speed BIST to Test LVDS Serializer/Deserializer Function

LVDS is the acronym for Low-Voltage-Differential-Signaling and is described in both the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. High performance yet Low Power and EMI have made LVDS a popular choice for high-speed card-to-card serial links. A typical application is the serializer/deserializer (ser/des) function where wide TTL datastreams including clock is converted to a serial LVDS bit stream, sent over a cable, and deserialization and clock recovery performed on the receiving card. This is a powerful design technique but presents interesting challenges from a testability perspective. First, LVDS links have a much different fault spectrum than the well-established stuck-at models used for TTL logic levels. The LVDS interconnect is a transmission line model, where the signal carrying integrity of the cable, fault models and fault detection are very frequency dependent. In addition, the Ser/Des function with clock recovery requires the two devices to achieve synchronization, so efforts to test the link and ser/des functionality must meet the timing requirements of the internal logic. Ideally, any built-in-test capability for the link should be accessible via the JTAG port to take advantage of the existing industry tools and infrastructure.This paper describes a JTAG activated at-speed BIST technique used to test a high-speed ser/des chip set and cable.