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SEE Detection and Mitigation Strategy for GNSS Coprocessor IP-Core

In this work a combined hardware-software test strategy to detect the Single Event Effects (SEE) in the GNSS IP-Core is presented. The IP-Core is implemented in FPGA and it is part of the digital processing stage of flight models GNSS receivers for low-cost missions. The SEE in silicon devices are a very common problem in space missions, especially when commercial components are used instead of hardened radiation components due to its lower price. The proposed tests are a very useful tool to monitor the status health of the flight receiver and to take actions in case of SEE detections. They are integrated as a task of the operative system (OS) of the receiver and can be executed by a command sent from the Earth or by a periodic task controlled by the OS. In case of SEE detection, the verification task can decide to disable part of the IP-Core, reset the software of the receiver or reprogram the FPGA.