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A functional model of clocked microarchitectures

Models for the simulation of computer systems at the microarchitectural level are widely used to assist in design analysis and verification, and the development of microcode. The general model we describe here represents the behaviour of a clocked microarchitecture through the application of functions to component states and signal values. The operational semantics of the model are based partly on data flow and partly on graph reduction, allowing use to be made of the concept of 'lazy' evaluation to aid efficient simulation.