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A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency

In this paper, two kinds of simplified cell structures for low voltage noise immunity and a hybrid Markov Random Field probabilistic-based circuit design technique are proposed to reduce the hardware overhead and improve the noise immunity. To demonstrate the proposed technique, four kinds of test chips with an 8-bit carry lookahead adder (CLA) are fabricated in a 130nm CMOS technology. Measurement results show the proposed hybrid MRF CLA improves 14% noise immunity, saves 53% energy consumption and reduces 11% circuit area than the other CLAs.