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A tool for translating VHDL to finite state machines

The overall research goal in Gurkh is to build a framework for design, verification and execution of safety critical applications. The framework consists of both software tools for application verification and hardware platforms for execution and real-time monitoring. This paper discusses within the context of the Gurkh project, the development of a tool to translate safety critical VHDL code into a formal representation. Different formal techniques can then be applied on this representation in order to verify properties such as liveness and deadlock and to validate that the timing constraints of the original system hold. This paper will discuss three aspects of the tool implementation: transformation of source code into an intermediate representation, verification of real-time properties, and some tool-related implementation issues.