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A novel Overlapping Circular-Gate Transistor (O-CGT) and its application to analog design

This paper introduces an Overlapping Circular-Gate Transistor (O-CGT) that allows gate overlaying between neighboring cells, enhancing layout packing with respect to conventional circular- and rectangular-gate structures. Although a section of gate annulus does not contribute to the drain current, a higher aspect-ratio is attained. Besides, both drain and source junctions have their area minimized, so that faster transients can be reached. A first-order model for (W/L)eff of the proposed device is developed and its validity attested by a range of 3D-simulation of IDS × VDS characteristics from ATLAS3D software. Error between analytical and 3D-simulation data was limited to only 2.9%. With respect to a conventional circular-gate transistor (CGT), the O-CGT breakdown voltage BVDS is reduced by only 6.1%. An O-CGT-based power FET with on-resistance of tens of mΩ is laid out. An area saving of 18.6% is achieved as compared to rectangular geometries. O-CGT geometries as unit cells to compound a radiation-hardened OTA are also studied.