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Power efficiency of digit level polynomial basis finite field multipliers in GF(2283)

Several digit level finite field multiplier architectures have been proposed in the literature. Some of them are with power estimation with different VLSI technology for different field sizes which makes it difficult to compare their power efficiency. In this paper, we perform VLSI simulation for several existing digit level field multipliers in the same field, GF(2283), and with the same 0.18μm VLSI technology so that an effective comparison of their power efficiency along with other IC features such as area and critical path delay can be made. Recommendations of the most efficient finite field multiplier are given for the different application constraints. Detailed discussion is provided for power constrained mobile and wireless applications. The comparison results obtained in this paper are expected to be useful for those who design and/or implement elliptic curve cryptography for wireless and portable systems.