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Design and implementation of a TCP checksum offload engine based on the multiport memory controller and the processor local bus

The TCP protocol has a checksum operation to verify the data integrity. This operation is performed over all bytes of a TCP segment, consuming several clock cycles and occupying precious processing time from embedded processors. This paper presents the implementation of the TCP checksum in an independent hardware module to reduce the processing time. This module, called the TCP Checksum Offload Engine (TCOE), integrates a Multiport Memory Controller (MPMC) and a Processor Local Bus (PLB) to improve the response time. The experimental results reported performance improvements in the TCOE-based system compared to the performance of the baseline implementation for segment sizes greater than or equal to 79 bytes. The clock cycles of the TCOE-based system also represented only 1% of the baseline clock cycles after increasing segment size and reaching its maximum value.