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Performance Evaluation of a Cell Reassembly Mechanism with Individual Buffering in an ATM Switching System

We present a performance evaluation model of cell reassembly mechanism in an ATM switching system. An ATM switching system may be designed so that communications between processors of its control part can be performed via its switching network rather than a separate inter-processor communications network. In such a system, there should be interface to convert inter-processor communication traffic from message format to cell format and vice versa, that is, mechanisms to perform the segmentation and reassembly sublayer. In this paper, we employ a continuous-time Markov chain for the performance evaluation model of cell reassembly mechanism with individual buffering, judicially defining the states of the mechanism. Performance measures such as message loss probability and average reassembly delay are obtained in closed forms. Some numerical illustrations are given for the performance analysis and dimensioning of the cell reassembly mechanism.