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An FPGA based accelerator for discrete Hartley and fast Hadamard transforms

In this paper we present two design methodologies ideally suited for the implementation of discrete Hartley and fast Hadamard transforms which are useful in many types of applications including image and signal processing. The proposed architectures are based on conventional arithmetic and distributed arithmetic principles respectively. In order to efficiently implement the two architectures, Handel-C - a recently developed C-like programming language for compilation of high-level programs directly into FPGA hardware - has been used to interface the VHDL cores developed for the two transforms. The algorithms have been implemented and verified on the Celocixa RC1000 PCI based FPGA board with Xilinx Virtex-2000E FPGA. An evaluation has also been reported based on maximum system frequency and chip area