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Guest Editors’ Introduction: Emerging Challenges and Solutions in SoC Verification

Verification has been one of the major bottlenecks in integrated circuit design process, which is exacerbated by the sheering design complexities nowadays. The increased design size is only one dimension of the growing complexities. Recent System-on-Chips (SoC) often feature multiple heterogeneous embedded processors and accelerators. While the heterogeneous architecture is more power efficient, it adds verification complexities of the hardware/software interaction and interconnect coherency. It is common that tens or hundreds of IP blocks, among which analog IPs occupy an increasing portion, are integrated into a single chip. Moreover, the growing market shares of devices for Internet-of-Things (IoT) and automotive applications have signified the requirements for verifying security and safety, which adds new dimensions to the complexities. As a result, the industry has encountered emerging challenges for correctly verifying increasingly complex SoCs in a timely manner, which create the “verification gap.” This special issue is devoted to address the verification challenges, the needs for advanced verification technologies to close the gap, and the state-of-the-art solutions.