{'fraction_non_alphanumeric': 0.02763157894736842, 'fraction_numerical': 0.0, 'mean_word_length': 5.394957983193278, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Fast simulation of interconnect-dominant circuits

As the convergence of programmable cores, memory blocks. sensors and other analog/RF circuits on system-on-a-chip (SoC) for networking and wireless applications is striding forward swiftly, there is an increased demand for accurate circuit-level verification of SoC designs. This paper presents a new simulation method of interconnect-dominant circuits via a two-step LU matrix factorization method. By using this new method, unnecessary repetitions of arithmetic operations are avoided in circuit analysis. As a result, plenty of simulation time is saved without losing accuracy. The simulation results show that this method is much more efficient than HSPICE while simulating interconnect-dominant networks.