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A Flexible Chip Multiprocessor Simulator Dedicated for Thread Level Speculation

Thread level speculation (TLS) is a promising way to enhance the performance of chip multiprocessor (CMP). Up to now, effective time-accurate CMP simulator dedicated for TLS is still in demand. This paper presents a novel flexible chip multiprocessor simulator "TLSim" dedicated for thread level speculation. By TLSim, the special and credible program behavior and architecture design features in TLS can be gained to guide the speculative multicore design. It illustrates the special speculative architecture and programming model in TLSim. Furthermore, it trades off several important design factors in coming speculative multicore architecture. The experimental results show that: (1) TLSim has good scalability and low speculative overhead. (2) The impact of several important decisions in the coming speculative multicore design, such as the proper instruction issue width is 2 and out-of-order issue way is still important in multicore design that is against the conventional perception.