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Error analysis and inter-cell interference mitigation in multi-level cell flash memories

With an aim to characterize, model and understand the types of errors caused by the inter-cell interference (ICI) effect in flash memories, we perform a series of program/erase (P/E) cycling experiments designed to quantify the effects of ICI. We create a database of errors at various levels of granularity such as bit, cell, page, block and record the neighborhood data patterns of cells in error to provide a quantitative understanding of the underlying channel model in multi-level cell (MLC) flash memories. We then utilize this empirical data to model and study the flash memory channel as a time-varying 4-ary discrete memoryless channel (DMC). We also present results from experiments to quantify the error rate performance gain obtained by the use of constrained codes, which prevent some ICI-susceptible data patterns from being written to the flash memory.