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Reconfigurable Hardware Architecture Design and Implementation for AI Deep Learning Accelerator

This paper proposes the Convolution Neural Network hardware accelerator architecture with 72PEs to achieve 14.4GOPS@100Mhz. The proposed CNN hardware accelerator is a layer-based architecture which can be reconfigured the layer parameters to suitable for different CNN architectures. The proposed architecture is based on operating three rows of input feature maps and then generate a one-row output feature map. The proposed architecture uses 322KB on-chip memory to store input feature maps, bias values, weights, and output feature maps to improve the efficiency of data reuse and reduce bandwidth utilization.