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A 32-Kb High–Speed 8T SRAM with Fine-Grained Bitline Stacking for Leakage Reduction in 7nm Technology

A conventional dual port 8-transistors (8T) SRAM circuit allows an asynchronous reading and writing feature, but its leakage power is significantly higher compared to the conventional 6T cell in the same technology. We proposed transistors stacking technique to reduce leakage power consumption in the fine-grained 8T cell’s read bitline. Furthermore, power gating and floating write driver techniques are proposed to further reduce the leakage power consumption in the bank-level wordline (WL) driver. Post-layout simulations show that the leakage power consumption of the 32-Kb SRAM is reduced by 75% in stand-by mode with only 13% read access time increase with 1.5% area penalty.