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PH3 Ion Shower Implantation and Rapid Thermal Anneal with Oxide Capping and Its Application to Source and Drain Formation of a Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistor

PH3 Ion shower implantation (ISI) and rapid thermal anneal (RTA) are examined for applications in the source and drain (S/D) formation of a fully depleted (FD) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET). After the PH3 ISI, oxide capping by plasma enhanced chemical vapor deposition (PECVD) prior to the RTA not only prevents dopant out-diffusion, but also improves activation efficiency. In oxide capping case, the dopants diffuse more. However, it is confirmed that lower sheet resistance and less dopant diffusion can be achieved by decreasing the thermal budget with oxide capping, compared with the case of RTA without oxide capping. We extract the dopant lateral diffusion length and the lateral abruptness experimentally for a 40-nm-thick SOI from the electrical characteristics of an FD SOI MOSFET. Under the annealing conditions of 900°C for 20 s with oxide capping, the sheet resistance, the lateral diffusion length and the lateral abruptness for a 40-nm-thick SOI are 250 Ω/sq, 35 nm and 5.7 nm/dec, respectively.