{'fraction_non_alphanumeric': 0.024857954545454544, 'fraction_numerical': 0.0, 'mean_word_length': 5.64622641509434, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Improving Operational Stability of p‐Type Field‐Effect Transistors by Charge Selective Electrodes: a General Strategy

Operational instability caused by unintentional electron injection is a common problem for field‐effect transistors (FETs) based on relatively narrow‐bandgap semiconductors. Typically, the electron injection is followed by electron trapping at the semiconductor/dielectric interface or sometimes in the bulk semiconductor, resulting in a modification of the built‐in field in the FETs. Such a dynamic process causes continuous threshold voltage or Dirac voltage (Vth/Dirac) shift and thus unstable device operation. A charge‐selective electrode (CSE) design is used to address these problems. The CSE is formed by inserting a molybdenum trioxide interlayer between the electrode and the semiconductor, which creates an energy barrier to block electron injection. It is shown that the CSE strategy can generally work for FETs based on three semiconductor families, namely conjugated polymer, graphene, and quantum dot, and greatly suppresses the Vth/Dirac shift, enhancing the bias stress stability as well as reducing the noise level of the FETs. The mechanism for CSE‐reduced bias stress is investigated through trap analysis. CSE is a general strategy for achieving stable and low‐noise operation of unipolar FETs. The device design concept can be applied to other device configurations.