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Low-Power CMOS Library Design Methodology

The emphasis in VLSI design has shifted from high speed to low power due to the proliferation of portable electronic systems. The goal of this project is to develop a methodology for designing low power circuits and cells, and to implement this methodology in constructing a general purpose cell library that can be used to design low power integrated circuits. The design methodology encompasses all aspects of circuit design; it optimizes transistor size, logic style, layout style, cell topology, and circuit design for low power operation. The cell library is implemented within the framework of the LagerIV CAD suite for rapid logic synthesis and layout generation. Several chips designed with the low power library demonstrate the power reduction that can be achieved. The entire cell library is characterized to determine typical delay, average power consumption, and area for each cell so the IC designer can make reasonable speed, area, and power estimations while still in the architecture design stage.