{'fraction_non_alphanumeric': 0.015930485155684286, 'fraction_numerical': 0.0, 'mean_word_length': 5.398148148148148, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFIC

Crosstalk propagating through the silicon substrate is a serious limiting factor on the performance of advanced mixed analog-digital CMOS integrated circuits. This problem also appears in RF chips in the form of power leakage from local oscillators or power amplifiers, as well as the noise coupled from the digital baseband circuitry. Several studies have presented measurements on simple test structures to determine the best approach to minimize this leakage. Nevertheless, these studies are usually restricted to a single technology, and the consequences of applying results to other technologies are not evaluated. Also, these studies are usually performed with on-wafer samples, and thus package effects are not taken into account. However, package parasitics are an important factor in the substrate crosstalk, since they determine how much of the leakage finds a return path to external ground. In this paper, we discuss different technological approaches to increase isolation between coupled circuits. Measurements of the isolation on some test structures fabricated in a CMOS RF technology are presented. The package parasitics effect is evaluated by comparing on-wafer vs packaged samples. Measurement results are complemented with simulations of a broader range of situations.