{'fraction_non_alphanumeric': 0.027331189710610933, 'fraction_numerical': 0.03376205787781351, 'mean_word_length': 4.877358490566038, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A fully integrated injection-locked picosecond pulse receiver for 0.29pSrms-jitter wireless clock synchronization in 65nm CMOS

This paper reports a picosecond pulse receiver based on a three-stage divide-by-8 injection-locked frequency divider. The receiver operates for pulses with center frequency of 77 GHz and locks its output to the 9.6-GHz repetition rate with an effective locking range of 142 MHz. This receiver, which consumes 42 mW dc power, is used to demonstrate wireless clock synchronization with a 0.29ps RMS timing jitter and indicates an estimated sensitivity of −65.5 dBm in detecting picosecond pulses.