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Loop Transformations for Power Consumption Reduction in Wireless Sensor Networks Memory: A Review

Wireless Sensor Networks (WSNs) have made the power consumption crucial. Memory is known to be extremely power consuming. The increasing gap between processor and memory performance has motivated the design of systems with deep memory hierarchies, cache memory is recognized to improve the performance of memory in WSNs, therefore code transformations are a well-known hardware/software partitioning (Co-Design) to take the most advantage of memory hierarchy. Therefore, this paper proposes code transformations which are performed on loops that constitute parts of WNSs software. This proposal presents techniques to reduce the WSNs memory power consumption and improve the performance by loops transformations that can fully exploit the optimization opportunities which apply cache miss rate predictions techniques and systems resources measurements. In this paper, a background of WSNs code optimizations and their advantages and limitations and some proposed techniques of loops transformations are presented.