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A FPGA-based Soft Multiprocessor System for JPEG Compression

To achieve a balance between high performance and energy efficiency embedded systems often use heterogeneous multiprocessor platforms tuned for a welldefined application domain. However, due to extremely high design cost and NRE for deep submicron IC, not many applications can afford that [1]. An alternative solution is FPGA-based multiprocessor system. In this way, both high programmability and low risk can be obtained. Recent research shows such a system which loses only 2.6X in performance (normalized) compared to a dedicated ASIP for IP packet forwarding application [2]. In this paper, we demonstrate the design flow of an FPGA-based multiprocessor system for high performance multimedia application and explore different on-chip interconnects for multiprocessor system. We construct a JPEG encoder on multiprocessor on Xilinx Virtex-II Pro FPGA. The design can compress a BMP image into a JPG image in high speed. We also implement different interconnects between processors, including bus, dualport memory, FIFO and DMA controller, and explore the trade-off between them.