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Optimizing Design and FPGA Implementation for CABAC Decoder

Based on the research of CABAC arithmetic and the decoding flow, the paper indicates the bottleneck in CABAC decoding process and presents a novel architecture of CABAC decoder which takes optimization design for main function modules. Detail design for its architecture and function modules is described in the paper. Simulation and FPGA verification are implemented, and the results show that the decoder can increase the decoding speed efficiently and meet the demand of real-time high level video communication.