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Chip Health Monitoring Using Machine Learning

In nanoscale technology nodes, process and runtime variations have emerged as the major sources of timing uncertainties which may ultimately result in circuit failure due to timing violation. Therefore, in-field chip health monitoring is essential to track workload-induced variations at runtime in a per-chip basis. There exist a variety of monitoring circuits to track the delay changes of different on-chip components. However, existing techniques either need to stop normal execution of the chip or introduce a significant overhead unless they are carefully placed for very selective locations. Another challenge is to infer the information regarding the health of every critical paths of the chip with limited information obtained by the monitoring system. We address these challenges in this work using a representative path-selection technique based on machine learning. This technique allows us to measure the delay of a small subset of paths and assess the circuit-level impact of workload for a larger pool of reliability-critical paths.