{'fraction_non_alphanumeric': 0.023140495867768594, 'fraction_numerical': 0.0, 'mean_word_length': 5.3125, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection

Accurate prediction of device aging plays a vital role in the circuit design of advanced-node CMOS technologies. In particular, hot-carrier induced aging is so complicated that its modeling is often significantly simplified, with focus limited to digital circuits. We present here a novel reliability-aware compact modeling method that can accurately capture the full post-stress I-V characteristics of the MOSFET, taking into account the impact of drain depletion region on induced defects.