{'fraction_non_alphanumeric': 0.02830188679245283, 'fraction_numerical': 0.012129380053908356, 'mean_word_length': 4.944, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Statistical modeling of the program/erase cycling acceleration of low temperature data retention in floating gate nonvolatile memories

Charge leakage from nonvolatile memory floating gates at temperatures below 200/spl deg/C has been observed by many authors. The leakage, which we refer to as low temperature data retention (LTDR), is activated by program/erase (P/E) cycling of a flash memory array. LTDR can be observed as tailbits in experimental threshold voltage distributions. In this paper, we describe cycling acceleration using experimental data across a wide range of P/E cycles from 10 to 1x10/sup 5/. To account for the random nature of LTDR, we apply a statistical modeling methodology using data from large sample experiments.