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An Automatic Placement Algorithm for Superconducting Rapid Single-Flux-Quantum Logic Circuits

With the demand for data processing and storage increasing rapidly, the existing CMOS-based computing system is gradually unable to meet the amplification demand because of its high-power consumption. Due to high frequency and low power consumption, superconducting rapid single-flux-quantum (RSFQ) logic circuit technology is an attractive candidate. In this paper, we propose a novel placement method based on the layer layout. We layer the gates according to the logic level, which is the length of the longest path in terms of the number of clocked gates from any primary input (PI) of the circuit to the gate. Dummy gates are inserted so that any two adjacent layers can form a bipartite graph. Then the gates of each layer are reordered to minimize the half-perimeter wirelength (HPWL). Finally, the gates of each layer are assigned vertical positions to make the edges as straight as possible. The distance between adjacent layers is determined by the number of bending points of the edges between layers. We use several superconducting RSFQ logic circuits to evaluate the effectiveness of our proposed placement method, which uses HPWL and area as evaluation metrics. The experimental results show that compared with the Simulated Annealing (SA)-based placement method, the proposed approach can reduce the total HPWL and total area by an average of 77.77% and 57.56%, respectively.