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Cache-aware development of high integrity real-time systems

Cost, performance and availability considerations are forcing even the most conservative high-integrity embedded real-time systems industry to migrate from relatively simple hardware single-core processors to ones equipped with caches and other acceleration features. This irresistible migration threatens to disrupt the approach, practices and solutions that industry had developed and consolidated over the years to address the challenge of timing analysis. Industry that are confident with the efficiency and effectiveness of their verification and validation processes for old-generation hardware processors, do not have sufficiently solid insight on the effects that may be incurred by the migration to cache-equipped processors. Caches are perceived as an additional source of complexity, which has potential for shattering the guarantees of costand schedule-constrained qualification of their systems. The current industrial approach to timing analysis is ill-equipped to cope with the potentially large jitters incurred by the use of caches. Conversely, the application of advanced WCET analysis techniques on real-world (hence large and massively complex) industrial software, developed without analysability in mind, is often irremediably infeasible. Building on those considerations we propose the adoption of a structured “cacheaware” development approach aimed at minimising the extent and source of cache jitters, as well as at enabling the application of advanced WCET analysis techniques to large complex systems. We defined our approach as a combination of three main constituents: (i) identification of those software constructs that may impede or exceedingly complicate timing analysis in large and complex systems; (ii) elaboration of practical means, under the model-driven engineering (MDE) paradigm, to enforce the automated generation of software that is time predictable by construction; and (iii) implementation of an incremental layout optimisation method to remove cache jitters that stem from the software layout in memory, with the intent of actively facilitating incremental software development, which is of high strategic interest to industry. The integration of those constituents in a coherent structured approach to timing analysis achieves two interesting properties: the resulting