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Optimization of shared memory controller for multi-core system

This paper presents an optimized architecture of shared memory controller in packet processing multi-processor system on chip (MPSoC). The rotation priority algorithm in arbitration mechanism is ameliorated so that fairness of the memory access response and continuity of read/write commands are guaranteed. A ‘ping-pong’ structure is adopted in SRAM interface logic which optimizes the memory data throughput. The test results show that the proposed architecture improves total performance by up to 64.1% compared with original memory controller and the 100% peak utilization of the data bus can be obtained. The efficiency of memory access shared by multi-processor cores is advanced remarkably.