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Adoption of abstract power-management specification to FPGA-based design

Modern system-on-chip designs are characterized by their high complexity. It results in an increased number of transistors in a single chip, size of which is continuously decreasing due to market requirements. These issues have negative impact on reliability of the system, mainly because of the overheating of the device due to its power requirements. The result is that designers have to implement power-management techniques to reduce power. Due to high complexity of the systems, the modern trend is to specify power management at the high abstraction levels. However, the existing low-power design methodologies mostly target the application-specific integrated circuit (ASIC) devices, because they offer more flexibility in adoption of various power-reduction techniques. In this paper, we target field-programmable gate array (FPGA) designs. We adopt the previously developed low-power systems design methodology to FPGA platforms, enabling power management at early design stages. A high degree of automation is involved in the adopted methodology, which ensures fast development of FPGA-based low-power systems. The utilized abstraction and automation is suitable especially for novice designers, such as students; therefore, the proposed methodology is useful in education. The experiments illustrate power-management overhead of the offered methodology as well as its usefulness for modern designs.