RevRagnarok's blog - Blog: Here's the PCI Spec I DID find... [ Google Groups Link] {{{ The PCI (Peripheral Component Interconnect) Bus This file is not intended to be a thorough coverage of the PCI standard. It is for informational purposes only, and is intended to give designers and hobbyists an overview of the bus so that they might be able to design their own PCI cards. Thus, I/O operations are explained in the most detail, while memory operations, which will usually not be dealt with by an I/O card, are only briefly explained. Hobbyists are also warned that, due to the higher clock speeds involved, PCI cards are more difficult to design than ISA cards or cards for other slower busses. Many companies are now making PCI prototyping cards, and, for those fortunate enough to have access to FPGA programmers, companies like Xilinx are offering PCI compliant designs which you can use as a starting point for your own projects. For a copy of the full PCI standard, contact: PCI Special Interest Group (SIG) PO Box 14070 Portland, OR 97214 1-800-433-5177 1-503-797-4207 There is also a spec for CompactPCI, which uses the same timing and signals, but uses a eurocard connector and format. This is not presently covered in any detail within this document. Pinout (5 volt and 3.3 volt boards) -12V 01 *TRST TCK +12V GND TMS TDO TDI +5V +5V +5V *INTA *INTB *INTC *INTD +5V *PRSNT1 reserved reserved 10 +I/O V (+5 or +3.3) *PRSNT2 reserved GND Key3.3 GND GND Key3.3 GND reserved reserved GND *RST CLK +I/O V (+5 or +3.3) GND *GNT REQ GND +I/O V (+5 or +3.3) 20 reserved AD31 AD30 AD29 +3.3V GND AD28 AD27 AD26 AD25 GND +3.3V AD24 C/BE3 IDSEL AD23 +3.3V GND AD22 AD21 AD20 AD19 30 GND +3.3V AD18 AD17 AD16 C/BE2 +3.3V GND *FRAME *IRDY GND +3.3V *TRDY *DEVSEL GND GND *STOP *LOCK +3.3V *PERR 40 SDONE +3.3V *SBO *SERR GND +3.3V PAR C/BE1 AD15 AD14 +3.3V GND AD13 AD12 AD11 AD10 49 AD9 GND Key5 GND GND Key5 GND AD8 52 C/BE0 AD7 +3.3V +3.3V AD6 AD5 AD4 AD3 GND GND AD2 +I/O V (+5 or +3.3) +I/O V (+5 or +3.3) *ACK64 60 *REQ64 +5V +5V +5V 62 +5V (64 Bit Bus Extension Only) reserved 63 GND GND C/BE7 C/BE6 C/BE5 C/BE4 +I/O V (+5 or +3.3) GND PAR64 AD63 AD62 AD61 GND +I/O V (+5 or +3.3) 70 AD60 AD59 AD58 AD57 GND GND AD56 AD55 AD54 AD53 +I/O V (+5 or +3.3) GND AD52 AD51 AD50 AD49 GND +I/O V (+5 or +3.3) AD48 AD47 80 AD46 AD45 GND GND AD44 AD43 AD42 AD41 +I/O V (+5 or +3.3) GND AD40 AD39 AD38 AD37 GND +I/O V (+5 or +3.3) AD36 AD35 AD34 AD33 90 GND reserved reserved reserved GND GND 94 reserved * - Active Low PCI slots are keyed so that a 3.3 volt card cannot be plugged into a 5 volt slot, and a 5.5 volt card cannot be plugged into a 3 volt card. Dual voltage cards are possible. Key3.3 - At this location, a key is present on 3.3 volt boards. On 5 volt boards, these pins are GND. Key5 - At this location, a key is present on 5 volt boards. On 3.3 volt boards, these pins are GND. Signal Descriptions: AD(x): Address/Data Lines. CLK: Clock. 33 MHz maximum. C/BE(x): Command, Byte Enable. FRAME: Used to indicate whether the cycle is an address phase or or a data phase. DEVSEL: Device Select. IDSEL: Initialization Device Select INT(x): Interrupt IRDY: Initiator Ready LOCK: Used to manage resource locks on the PCI bus. REQ: Request. Requests a PCI transfer. GNT: Grant. indicates that permission to use PCI is granted. PAR: Parity. Used for AD0-31 and C/BE0-3. PERR: Parity Error. RST: Reset. SBO: Snoop Backoff. SDONE: Snoop Done. SERR: System Error. Indicates an address parity error for special cycles or a system error. STOP: Asserted by Target. Requests the master to stop the current transfer cycle. TCK: Test Clock TDI: Test Data Input TDO: Test Data Output TMS: Test Mode Select TRDY: Target Ready TRST: Test Logic Reset The PCI bus treats all transfers as a burst operation. Each cycle begins with an address phase followed by one or more data phases. Data phases may repeat indefinately, but are limited by a timer that defines the maximum amount of time that the PCI device may control the bus. This timer is set by the CPU as part of the configuration space. Each device has its own timer (see the Latency Timer in the configuration space). The same lines are used for address and data. The command lines are also used for byte enable lines. This is done to reduce the overall number of pins on the PCI connector. The Command lines (C/BE3 to C/BE0) indicate the type of bus transfer during the address phase. C/BE Command Type 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 reserved 0101 reserved 0110 Memory Read 0111 Memory Write 1000 reserved 1001 reserved 1010 Configuration Read 1011 Configuration Write 1100 Multiple Memory Read 1101 Dual Address Cycle 1110 Memory-Read Line 1111 Memory Write and Invalidate The three basic types of transfers are I/O, Memory, and Configuration. PCI timing diagrams: ___ ___ ___ ___ ___ ___ CLK ___| |___| |___| |___| |___| |___| |___ _______ _________ FRAME |_________________________________| ______ _______ ______ ______ ______ AD -------<______><_______><______><______><______>--- Address Data1 Data2 Data3 Data4 ______ _______________________________ C/BE -------<______><_______________________________>--- Command Byte Enable Signals ____________ ___ IRDY |_________________________________| _____________ ___ TRDY |________________________________| ______________ ___ DEVSEL |_______________________________| PCI transfer cycle, 4 data phases, no wait states. Data is transferred on the rising edge of CLK. [1] [2] [3] ___ ___ ___ ___ ___ ___ ___ ___ CLK ___| |___| |___| |___| |___| |___| |___| |___| |__ _______ _________ FRAME |________________________________________________| A B C ______ ______________ ______ _____________ AD -------<______>---------<______________><______><_____________>--- Address Data1 Data2 Data3 ______ ______________________________________________ C/BE -------<______><______________________________________________>--- Command Byte Enable Signals Wait ____________ _____ ___ IRDY |__________________________________| |_______| Wait Wait ______________________ ______ ___ TRDY |_______| |_______________________| ______________ ___ DEVSEL |______________________________________________| PCI transfer cycle, with wait states. Data is transferred on the rising edge of CLK at points labled A, B, and C. Bus Cycles: Interrupt Acknowledge (0000) The interrupt controller automatically recognizes and reacts to the INTA (interrupt acknowledge) command. In the data phase, it transfers the interrupt vector to the AD lines. Special Cycle (0001) AD15-AD0 0x0000 Processor Shutdown 0x0001 Processor Halt 0x0002 x86 Specific Code 0x0003 to 0xFFFF Reserved I/O Read (0010) and I/O Write (0011) Input/Output device read or write operation. The AD lines contain a byte address (AD0 and AD1 must be decoded). PCI I/O ports may be 8 or 16 bits. PCI allows 32 bits of address space. On IBM compatible machines, the Intel CPU is limited to 16 bits of I/O space, which is further limited by some ISA cards that may also be installed in the machine (many ISA cards only decode the lower 10 bits of address space, and thus mirror themselves throughout the 16 bit I/O space). This limit assumes that the machine supports ISA or EISA slots in addition to PCI slots. The PCI configuration space may also be accessed through I/O ports 0x0CF8 (Address) and 0x0CFC (Data). The address port must be written first. Memory Read (0110) and Memory Write (0111) A read or write to the system memory space. The AD lines contain a doubleword address. AD0 and AD1 do not need to be decoded. The Byte Enable lines (C/BE) indicate which bytes are valid. Configuration Read (1010) and Configuration Write (1011) A read or write to the PCI device configuration space, which is 256 bytes in length. It is accessed in doubleword units. AD0 and AD1 contain 0, AD2-7 contain the doubleword address, AD8-10 are used for selecting the addressed unit a the malfunction unit, and the remaining AD lines are not used. Address Bit 32 16 15 0 00 Unit ID | Manufacturer ID 04 Status | Command 08 Class Code | Revision 0C BIST | Header | Latency | CLS 10-24 Base Address Register 28 Reserved 2C Reserved 30 Expansion ROM Base Address 34 Reserved 38 Reserved 3C MaxLat|MnGNT | INT-pin | INT-line 40-FF available for PCI unit Multiple Memory Read (1100) This is an extension of the memory read bus cycle. It is used to read large blocks of memory without caching, which is beneficial for long sequential memory accesses. Dual Address Cycle (1101) Two address cycles are necessary when a 64 bit address is used, but only a 32 bit physical address exists. The least significant portion of the address is placed on the AD lines first, followed by the most significant 32 bits. The second address cycle also contains the command for the type of transfer (I/O, Memory, etc). The PCI bus supports a 64 bit I/O address space, although this is not available on Intel based PCs due to limitations of the CPU. Memory-Read Line (1110) This cycle is used to read in more than two 32 bit data blocks, typically up to the end of a cache line. It is more effecient than normal memory read bursts for a long series of sequential memory accesses. Memory Write and Invalidate (1111) This indicates that a minimum of one cache line is to be transferred. This allows main memory to be updated, saving a cache write-back cycle. Bus Arbitration: This section is under construction. PCI Bios: This section is under construction. t (C) Copyright 1996 by Mark Sokos. This file may be freely copied and distributed, provided that no fee is charged. This information is provided "as-is". While I try to insure that the information is accurate, errors and typos may exist. Send corrections and comments to The latest version of this file may be found at References: "Inside the PCI Local Bus" by Guy W. Kendall Byte, February 1994 v 19 p. 177-180 "The Indispensible PC Hardware Book" by Hans-Peter Messmer ISBN 0-201-8769-3 }}} en-US Trac 1.4 RevRagnarok's blog