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A simple analytical model for the electrical characteristics of depletion-mode MOSFET's with application to low-temperature operation

A simple analytical model for depletion-mode MOSFET's is developed based on the gradual channel approximation and taking into account carrier freeze-out onto impurity sites implanted for threshold voltage modification. Theory is found to be in reasonable agreement with experimental results for n-channel depletion-mode MOSFET's at room temperature and at 77 K. It is shown that the common methods used for enhancement-mode devices to determine carrier channel mobility and threshold voltage, respectively, from the slope and voltage intercept of the current-gate voltage characteristics are invalid for depletion-mode devices. By comparison of enhancement and depletion devices on the same chip, it is shown that the processes associated with ion implantation had no effect on electron channel mobility at room temperature and caused at most a 25-percent reduction at 77 K. The model also is applicable to buried p-channel devices as used in CMOS technologies.