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Designing a multi‐layer full‐adder using a new three‐input majority gate based on quantum computing

Recently, quantum dot‐cellular automata (QCA) has fascinated much attention because of its potential less area consumption, low power usage, less intricacy, and low delay. The full‐adder circuit is used in this technology for several procedures, like multiplication, subtraction, and division in the arithmetic logic unit. For this reason, the full‐adder is generally investigated as a central unit in the development of QCA technology. The present investigation demonstrates a new efficient QCA‐based full‐adder layout utilizing the TIEO gate and new 3‐input majority gate. In this design, the inputs get inside one side, and the outputs are derived from another circuit side. Other cells do not embrace the output and input signals, and they may simply be available, helping produce a more impressive circuit layout. Concretely speaking, in this design, the 0.02 μm2 region and the latency of the 0.5 clock cycle have been implemented using only 18 cells. Utilizing the QCADesigner tool, the suggested design in the current investigation has been functionally approved. The simulation outcomes show that this layout conducts properly and works faster than the oldest designs.