{'fraction_non_alphanumeric': 0.02333931777378815, 'fraction_numerical': 0.004488330341113106, 'mean_word_length': 5.482558139534884, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
LUT-based Image Rectification Module Implemented in FPGA

This paper presents a real-time hardware architecture able to perform simultaneously, image rectification and image distortion removal. The entire process is based on Look-Up Tables (LUTs) relating pixels from rectified image and original image with sub-pixel precision. For increased flexibility, we created a parameterized VHDL version of the design, which allows us to generate different hardware configurations, based on adjustable parameters: image resolution, number of bits to store the sub-pixel precision. Other advantages of the proposed solution that worth to be mentioned are scalability (can be replicated for any number of rectified images) and portability on many FPGA-based hardware platforms. We analyze the performance of different configurations on a VirtexE600 FPGA. As rectifying an image based on bilinear interpolation has a blurring effect, with negative consequences on 3D reconstruction, we increased the sub-pixel precision and studied the impact on 3D lane detection accuracy, processing time and resource usage inside the chip.