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Signal Integrity Effects in System-on-Chip Designs-A Designer ' s Perspective

In this paper, we present a designer's perspective to the signal integrity issues that affect authors and integrators of blocks used in System-on-Chip designs. In particular, after presenting typical process parameters used for such designs, we focus on signal integrity issues in the context of power grid noise, interconnect crosstalk and substrate coupling. In each case, we describe the problem from the point of view of System-on-Chip designers (both block authors and block integrators), and briefly discuss standard techniques that are used to alleviate the problem.