{'fraction_non_alphanumeric': 0.01935483870967742, 'fraction_numerical': 0.002150537634408602, 'mean_word_length': 5.248322147651007, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
High throughput RST metrology to optimize 3D integration

Through Silicon Via (TSV) processing is crucial for the later performance and reliability of a device. Therefore, an accurate and efficient metrology loop to control and inspect underlying production steps is essential. Specifically, the TSV depth is of importance and must be constantly monitored to guarantee high yield of the final product. This joint work presents a fast and reliable study to control the TSV processing before reveal by measuring the Remaining Silicon Thickness (RST) after the TSVs are filled with copper. Spectral Coherence Interferometry (SCI) technology is used in combination with a so-called statistical approach to realize measurements on a rotational stage with an acquisition rate up to 4 kHz. The directly measured RSTs are compared to the calculated ones (Silicon Thickness-TSV depth) in order demonstrate the reliability of this approach.