{'fraction_non_alphanumeric': 0.028963414634146343, 'fraction_numerical': 0.010670731707317074, 'mean_word_length': 5.57, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Using structured ASIC to improve design productivity

Structured ASIC is a well-developed technology that enables a shorter design Turn-Around-Time (TAT) as well as less Non-Recurring-Engineering (NRE) cost for very deep submicron designs. Since 2003, Faraday Technology has developed its own structured ASIC solutions. Based on its own competitive technology architecture, Faraday has proposed platform-based SoC solutions and realized more than 100 customer projects using its structured ASIC technology. This paper presents Faraday's experience of using structured ASICs and shows Faraday's efforts to establish a high-productivity structured ASIC flow.