{'fraction_non_alphanumeric': 0.022970903522205207, 'fraction_numerical': 0.010719754977029096, 'mean_word_length': 4.5423728813559325, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Ultra low voltage and high speed CMOS flip-flop using floating-gates

In this paper we present a novel ultra-low-voltage (ULV) CMOS flip-flop (FF) exploiting ULV semi-floating CMOS logic. The ULV gates applied offer increased speed compared to other CMOS logic styles for low supply voltages. ULV logic gates can be operated at a clock frequency more than 10 times than the maximum clock frequency of a similar complementary CMOS gate operating at the same supply voltage. The ULV FF may operate at supply voltages down to 150mV. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90nm CMOS process.