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A unified reconfigurable floating-point arithmetic architecture based on CORDIC algorithm

This paper presents the design methodology and implementation of reconfigurable coordinate rotation digital computer (CORDIC) architecture that can be configured to operate in different modes and rotations to achieve singleprecision floating point division, multiplication and square-root operations. Through introducing pre- and post-processing, the float-point operations can be integrated into a unified CORDIC iteration procedure. According to the characteristics of different operations, we propose a pipeline-parallel mixed architecture to optimize the area-delay-efficiency. Finally, the prototype based on Xilinx XC7VX690T has been established to test the performance of the proposed design. The result shows the related error with arithmetic computation is less than 10−6, and the resource-consumption of the proposed design is less than the sum of existing IP cores.