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Finite-difference methodology for full-chip electromigration analysis applied to 3D IC test structure: Simulation vs. experiment

A novel electromigration (EM) assessment method based on a finite-difference (FD) approach has been implemented to study EM degradation in 3D integrated circuit (IC) supply current ports. A dual damascene copper through-silicon via (TSV) based EM test structure was used, which consisted of redistribution (RDL) and M1 metal layers connected by four TSVs on one side and a single TSV on the other side. The mean-time-to- failure (MTF) obtained with FD simulation agrees well with the MTF found using a finite-element analysis (FEA) method as well as with the measured MTF. The results demonstrate that the EM- induced MTF in 3D IC structures can be correctly predicted with FD simulations, by representing them as combinations of 1D interconnect branches with suitable boundary conditions (BC) for the branch junctions.