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Sensitivity Analysis on Hardware Resources in SMT Processors

The microprocessor performance is increased by allowing multiple threads per clock cycle to issue instructions in simultaneous multithreading processors. Shared hardware resources are the key components of SMT processor performance. In SMT processors, impact to the performance will not be same among many hardware resources. To design an optimal hardware configuration for SMT processors, sensitivity analysis on hardware resource variation is required. In this paper, we evaluate the impact of parameters such as cache, physical register sizes, issue queue, instruction fetch policies and branch prediction accuracy on the performance improvement in the SMT processors, which demonstrates the efficacy of hardware resources among the threads. This research helps in choosing the best hardware resource sizes and the techniques in allocating these resources among the threads.