{'fraction_non_alphanumeric': 0.0467706013363029, 'fraction_numerical': 0.0066815144766146995, 'mean_word_length': 5.164383561643835, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Characterization of CMOS latch-up

The purpose of the work was to characterize the latch-up in an N-well CMOS process with minimum channel length of 1.25\microm. Structures including SCRs, buffers, inverters, and input protections were characterized. Latch-up susceptibility is reduced for P-epi on P+substrate, starting material of low resistivity, guard band structure, relaxed layout spacings, deeper N-well, and shallower source-drain diffusion.