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Thermal modeling of 7 nm node bulk fin-shaped field-effect transistors for device structure-aware design

As semiconductor node technology becomes finer, the corresponding device dimensions should be reduced. To improve the side effects caused by the scaling-down strategy, fin-shaped field-effect transistors (FinFETs) have been introduced and are being actively researched. However, these thin silicon fins, especially confined within silicon dioxide (SiO2), have a relatively low thermal conductivity when compared with conventional planar bulk FETs. Thus, another issue, called the self-heating effect (SHE), has appeared with the emergence of FinFETs. In this paper, the self-heating effect on 7 nm node bulk FinFETs was investigated through calibrated technology computer-aided design (TCAD) simulation. A thermodynamic transport model is used to consider the self-heating effect on the device. The thermal resistance (RTH) was extracted from the TCAD result and modeled empirically to predict the RTH of sub-7 nm node technology. The empirical RTH model was also implanted in a Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG) to conduct an accurate Simulation Program with Integrated Circuit Emphasis (SPICE) model and simulation.