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Time‐interleaved SAR ADC design with background calibration

In this article, a low power time‐interleaved SAR (TI‐SAR) ADC is presented. Background calibration is used to improve the linearity of the ADC. Offset, gain, and capacitor mismatches between interleaved channels are calibrated by postprocessing the ADC output. Besides, a novel trimming‐based calibration algorithm is used to calibrate the timing mismatches between channels. The proposed calibration algorithm is more power‐efficient compared with most of its counterparts. The ADC consists of 18 parallel channels, a reference channel with two dummy channels, and a channel for timing calibration. The timing calibration channel is clocked only when the reference channel samples. The dummy channels are utilized to equalize the input load over time as they sample one after another to fill the gap where the reference channel does not sample. There is no need for any other dummy channels for timing calibration channel since it has low kickback noise over input driver. Each parallel channel operates at 111 ms/s while the reference channel runs at 105 ms/s. The aggregate sampling speed of the converter is 2 GS/s, and 52‐dB SNDR is accomplished near Nyquist frequencies.