{'fraction_non_alphanumeric': 0.025145067698259187, 'fraction_numerical': 0.015473887814313346, 'mean_word_length': 4.954022988505747, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Effects of Technology Scaling on Area-Delay Characteristics of RTL Designs: A Case Study

The paper investigates the effects of technology scaling on area/delay characteristics of registertransfer level (RTL) designs. Based on experimental modeling of RTL components and interconnect, whose feature sizes have been scaled down from 1.5 m to 0.25 m, we evaluate the critical path delay and area of several data-paths and report on efficiency of layout and RTL optimization techniques at the 0.25 m technological level.