{'fraction_non_alphanumeric': 0.025017618040873855, 'fraction_numerical': 0.0021141649048625794, 'mean_word_length': 4.782077393075356, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Accurate High Resolution Time Digital Converter Array for Single-Photon Image Sensors

Fluorescence-lifetime imaging microscopy (FLIM) has been primarily used to detect photosensitizers in the cells and cancer tissues. This imaging technique is based on different decay rates of the fluorescence from different type of cells. By reading the intensity of the fluorescence using image photo-detectors, high-contrast imaging of spatial structure of the target tissue is possible. Usually lifetime of the fluorescence is extracted by making a histogram of the intensity of the detected light in fixed portion of time. To achieve precise images, high time-resolution is needed as well as high sensitivity. Single photon Avalanche Diodes (SPAD) can be employed as extremely highsensitive photo-detectors that is provided by compact, low-cost CMOS technology. To make the histogram of the fluorescence, timing information of the detected photons is also needed. An accurate highresolution Time Digital Converter (TDC) is proposed in this work to measure time of photon detection. Because of high rate of photon detection the resolution of the TDC must be in the order of tens of picoseconds. Therefore sub-gate delay resolution is needed for the TDC which can be provided by Vernier Delay Line (VDL) or pulse shrinking or passive interpolation methods [1-3]. These methods can provide high-resolution, however they demand large number of delay elements for high dynamic range (DR) which will result into high area and high power consumption. As large in-chip TDCs reduces fill-factor of the SPAD detectors and sensitivity of the image sensor, TDC proposed in this work was tried to be as small as possible by using hierarchical method and by dividing the TDC into 4 parts (two coarse TDC and two fine TDCs) to achieve high resolution together with high DR (which is necessary for FLIM) and reasonable fill factor for SPADs. Fill factor is of more concern in our work as we are using TDC array instead of sharing a single TDC for all of the SPAD pixels. This is necessary as full parallel operation is required to obtain high frame-rate operation. Many groups have recently tried to use hierarchical method for designing TDCs [4-5] but to specifically design high-resolution, high DR TDCs for image sensors, special consideration regarding size of TDC and fill-factor of SPAD were applied in this work by dividing each of coarse and fine TDC into two parts. Tapped delay line and VDL are used as coarse and fine TDCs and Process, voltage and temperature (PVT) variation are cancelled using dual Delay Locked loop (DLL). SPAD image sensor that is used is a sensitive, low dark-count-rate SPAD that has been designed in our group [6]. Using this SPAD and the proposed TDC, accurate FLIM is achievable with high spatial resolution and high contrast.