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Analytical Modelling and Benchmarking of Fully Depleted Buried Metal Layer Junctionless Transistor

In this work, we propose surface potential and subthreshold current models for a buried metal layer based junction-less transistor, for the first time, and the proposed models are verified with the simulation results using Sentaurus TCAD. The buried metal layer (BML) induces the bottom depletion layer and its workfunction is important for volume depletion in OFF-state. The buried metal layer workfunction (ϕBML) required for full depletion is derived and its impact on short channel effects (SCE) and drain induced barrier lowering (DIBL) is studied. The scalability of the buried metal layer technology is benchmarked against the existing double gate architecture, using its natural length (λ), electrostatic integrity (EI), Vth roll-off and subthreshold slope (SS) as the figure of merits. It is found that the buried metal layer based junctionless transistor (BML-JLT) can be scaled higher than double gate (DG) provided ϕBML ≥ ϕBML,FD however, its subthreshold slope needs to be improved further.