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Integrated Test Pattern Extraction and Generation for Accurate Lithography Modeling

A set of good test patterns is a key for accurate lithography modeling. We address three sub-problems in test pattern extraction: (1) Each pattern is associated with one or more gauges, where CD is measured and modeling is performed. We perform gauge clustering in feature space, while the goal is to minimize the number of chosen patterns. (2) Sample patterns do not usually guarantee enough coverage, so once coverage of chosen patterns is identified, some synthetic patterns are systematically generated to fill the empty region in feature space. (3) Pattern representation defines the feature space. We propose to use some Gaussian convolutions (or a few of their principal components) together with image parameter set (IPS) to reflect exposure for optical model and both PEB and development for resist model. Experiments with 1xnm DRAM design demonstrate that lithography modeling through our test pattern extraction and generation is performed with 35% smaller number of test patterns while CD error is reduced by 55%, with pattern extraction in feature space of IPS parameters as a reference.