{'fraction_non_alphanumeric': 0.019367991845056064, 'fraction_numerical': 0.0163098878695209, 'mean_word_length': 5.254777070063694, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Reconfigurable Hardware Implementation of AES-RSA Hybrid Encryption and Decryption

Based on the structure of hybrid encryption algorithm, this paper proposes an area-saving hybrid AES-RSA encryption module which can be integrated into network processing unit system. In the implementation of the algorithm, combined with the advantages of reconfigurable technology and traditional algorithms, the reconfigurable computing module which is compatible with the two algorithms is designed. At the same time, an application specific control unit is designed in the periphery, which balances the core area and the usability and flexibility of the algorithm core. The synthesis result based on SMIC 0.13um technology library shows the designed circuit can run at 200 MHz clock within the area of 163.7 thousand gates. According to the test report, the throughput of AES encryption and decryption can reach 2.1Gbps, and the throughput of RSA encryption and decryption can reach 107.2Kbps.