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A Hands-on Fixed-Point DSP Lab for Undergraduate Students

For many applications fixed-point DSPs are advantageous because of their comparatively low chip-size, power consumption and overall cost. On the other hand, due to the reduced dynamic range (compared to floating point devices) scaling is often necessary. This leads to an increased software development effort. Furthermore, the choice of a suitable filter structure is much more critical for fixed-point devices. In the proposed DSP exercise undergraduate students are enabled to hearing and measuring the performance of three different filter topologies (direct form 1, cascaded second order sections and Kingsbury structure) and three numerical representations (floating point emulation, 32-bit fractional and 16-bit fractional) running simultaneously in real-time on a single 16-bit fixed-point DSP