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Test Architecture Design and Optimization for Three-Dimensional System-on-chips

Core-based system-on-chips (SoCs) fabricated on three-dimensional (3D) technology are emerging for better integration capabilities. Among all available manufactures techniques, 3D SoCs manufactured with die-to-wafer and die-to-die bonding techniques provides higher yield due to its capability of pre-bond test. Effective test architecture design and optimization techniques are essential to minimize the manufacturing cost for such giga-scale integrated circuits. In addition, the prebond test-pin-count constraint during optimization should be carefully considered since these pins occupy large silicon area that cannot be used in functional mode. To address above issues, in this thesis, we first propose novel test access mechanisms solutions for 3D SoCs by our simulated annealing-based technique, considering both testing time and routing cost. In addition, the proposed test-architecture design takes the SoC layout and pre-bond-test-pin into consideration and facilitates the sharing of test wires between pre-bond tests and post-bond test, which significantly reduces the routing cost for a test-access mechanism in 3D technology without violating the test-pin constraint. Afterwards, a thermal-aware test scheduling algorithm is proposed to eliminate the hotspots during test. Experimental results for the ITC’02 SoC benchmarks circuits demonstrate the effectiveness of the proposed solution.