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Interactive Test-Bench Synthesis for Assertion-Based Verification

In recent years, Assertion-Based Verification (ABV) is being widely accepted as a key technology in the pre-silicon validation of chips. Developing test sequences that trigger non-vacuous interpretations of the assertions is a complex problem, and is considered to be one of the major challenges in ABV. In this paper we present a language called Open-LTL for specifying temporal specifications and input constraints in a unified way and a formal methodology for generating interactive test-benches from these specifications that drive protocol compliant inputs to the Design-Under-Test (DUT).