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Teaching computer architecture with a new superscalar processor emulator

Current computers use several techniques to improve performance such as cache memories, pipeline and multiple instruction issue per cycle. Using a real computer to teach these concepts is actually impractical, because these computers are designed to be programmed in high-level languages.In order to solve this problem, we have implemented a superscalar processor emulator, where most of the processor and cache parameters can be defined by the student. Its objective is to create a set of laboratory works allowing the student to observe how the different components of the computer evolve while executing an assembler program. It allows detection of the different kinds of cache misses and hazards as well as their impact on performance. Then, the student can apply some software techniques to reduce cache misses and to avoid hazards.