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Static scheduling of multi-domain memories for functional verification

The presence of multiple clock domains presents significant challenges for large parallel verification systems such as parallel simulators and logic emulators that model both design logic and memory. Specifically, multiple asynchronous design clocks make it difficult to verify that design hold times are met during memory model execution and causality along memory data/control paths is preserved during signal communication. We describe new scheduling heuristics for memory-based designs with multiple asynchronous clock domains that are mapped to parallel verification systems. The scheduling approach scales to an unlimited number of clock domains and converges quickly to a feasible solution if one exists. It is shown that when the technique is applied to an FPGA-based emulator containing 48MB of SRAM, evaluation fidelity. is maintained and increased verification performance is achieved for large, memory-intensive circuits with multiple asynchronous clock domains.