{'fraction_non_alphanumeric': 0.03159252095422308, 'fraction_numerical': 0.020631850419084462, 'mean_word_length': 4.969230769230769, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform

Long-term monitoring of electrocardiogram (ECG) requires a portable inspection system that can offer both high energy efficiency and good signal quality. To manage challenges caused by this requirement, this brief presents an ASIC design for both ECG recording and R-peak detection. By supporting data compression and using a dual-ping-pong-memory architecture, this design leads to a large reduction in the whole system energy. To reduce the hardware cost, the techniques of coefficients truncation and resource sharing are adopted. Importantly, parameters optimization and periodic extension are employed to improve quality of the reconstructed signal under high compress ratio (CR). Experimental results based on MIT-BIH database show that the proposed design obtains a high CR of 10.3 with a percentage root-mean-square difference of 0.64% under recording mode, and it achieves an R-peak detection sensitivity of 99.72% as well as a positive prediction of 99.49% with 13.68× data reduction. This design has been fabricated under TSMC 65-nm CMOS technology with area cost of 0.41 mm2. Measurement results indicate that the total system energy consumption for processing one segment of signals can be reduced by 5.7× and 2.3× in recording and detection modes, respectively. Compared to a software implementation on the same chip, this ASIC implementation achieves a 41% and 50% reduction in energy consumption per sample under the two modes, respectively.