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High-speed robust level converter for ultra-low power 0.6-V LSIs to 3.3-V I/O

A new level converter aimed at ultra-low core voltage and wide range I/O voltage is designed using deep submicron process with standard MOS transistor without adding extra mask or process step. Simulation results demonstrate the performance improvement of the proposed level converter which can convert high-speed clock signals from 0.6-V to 3.3-V I/O interface within 0.5ns and maintain 50:53 of duty ratio.