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Integrated Inference for Hardware-Software Efficiency : A Case Study in SpMV and Smart Memories

Energy efficiency is the fundamental challenge in computing. Dennard scaling has stopped, which means that Moore’s Law provides more transistors but power densities increase with integration. These power densities, combined with Amdahl’s Law, will also limit the efficiencies and tractability of future multi-core integration. Without process and parallelism to drive efficiency, we must rely on customization and integrated design. However, customization has become prohibitively expensive, primarily due to the challenge of integrated software and hardware design. Customization is facilitated by recent advances in software and hardware generators, which constrain a design space, parameterize the remaining degrees of freedom, and automatically produce functional implementations for any combination of parameter values. To address these challenges, we propose using generators more effectively by creating an integrated design framework that synthesizes key interactions between hardware and software. We demonstrate a proof of concept for sparse matrix-vector multiply (SpMV) on an embedded processor hardware base, by using statistical regression modeling. With models that capture the highly non-monotonic SpMV performance topologies, we perform integrated optimization to demonstrate a performance gain of 5.0x (Mflop/s) while reducing the energy costs per operation by 10 percent (0.9x nJ/Flop).