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Synchronous controller models for synthesis from communicating VHDL processes

VHDL permits design descriptions with communicating multiple processes and provides signal assignments and wait statements to facilitate coordination and communication among the processes. These constructs lead to concise behavioral specifications but make controller generation in high level synthesis difficult. Current work on synthesis from VHDL restricts the behavioral subset, excluding or limiting the use of some of these constructs, thus leading to simple controller structures. Our paper proposer a controller model based on multiple, synchronous, communicating finite state machines. The proposed controller model permits the use of multiple processes with signal assignments and wait statements in behavioral specifications.