{'fraction_non_alphanumeric': 0.012448132780082987, 'fraction_numerical': 0.0, 'mean_word_length': 5.6422018348623855, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
EFFECT OF FINE-LINE DENSITY AND PITCH ON INTERCONNECT ILD THICKNESS VARIATION IN OXIDE CMP PROCESSES

The oxide polishing characteristics of fine-linewidth features typically encountered in realistic chip layouts have been examined using electrical test structures. Even at these small dimensions, we find that global pattern density plays a major role in determining the final polished oxide thickness. In addition, differences in the initial dielectric deposition profile for small features produces an apparent pitch effect which must also be taken into account. Based on experimental results, linewidth biasing during the computation of global density for modeling of CMP dielectric planarization behavior is suggested.