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VSIP : Video Specific Instruction Set Processor for H.264/AVC

H.264/AVC adopts new features compared with previous multimedia algorithms. It is inefficient to implement some of the new features with existing DSP instructions. This paper presents an application specific instruction set processor (ASIP) for implementation of H.264/AVC, called VSIP. The proposed VSIP has novel instructions for new features, such as intra prediction, deblocking filter, integer transform, etc. In addition, VSIP employs hardware accelerators for inter prediction and entropy coding. Performance comparisons show a significant improvement compared with existing DSPs. Moreover, the proposed hardware accelerators have small size and can support real-time video processing. The results indicate that VSIP is one of promising solutions for H.264/AVC