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An Inverter Gate Design Based on Nanoscale S-FED as a Function of Reservoir Thickness

In this paper, an inverter logic gate has been successfully designed based on the previously proposed side-contacted field-effect diodes (S-FEDs). Effect of the reservoir thickness on the S-FED performance is investigated, and then the output characteristics of the S-FED-based inverter are studied and compared with those of the existing CMOS technology. The S-FED performance evaluation is performed in terms of important figures of merit for logic application in various reservoir thicknesses, including transconductance, intrinsic gate delay time, energy delay product, and subthreshold slope. The numerical results demonstrate that the optimum reservoir thickness is 7 nm, and the threshold voltage can be controlled by reservoir thickness. Mixed-mode simulations also indicate that, in the design of an inverter utilizing S-FEDs, the delay and the power dissipation of the logic gate are reduced. These results indicate that the S-FED can be an interesting candidate for designing low-power and high-speed logic gates.