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High-level synthesis hardware implementation and verification of HEVC DCT on SoC-FPGA

The new High Efficiency Video Coding (HEVC) standard compresses the video twice as efficiently as the previous standard with the same quality. This comes at the expense of much higher computational complexity. Hence, real time HEVC encoder becomes a challenging task. Discrete Cosine Transform is one of the computational intensive modules in the HEVC encoder and decoder. In this paper, High Level Synthesis FPGA implementation of HEVC Discrete Cosine Transform algorithm is proposed targeting Xilinx Zynq ZC702. Then, The DCT core is verified as a standalone IP using real test vectors from HEVC encoder. Next, DCT is implemented in HDL, synthesized and compared to HLS approach. The results show that HLS approach is comparable regarding the resources utilization and advances in development time significantly. Also, the proposed HLS DCT implementation is able to support encoding of 1920×1080 at 30 fps.