{'fraction_non_alphanumeric': 0.026217228464419477, 'fraction_numerical': 0.003745318352059925, 'mean_word_length': 5.331753554502369, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Effect of underlap length variation on DC/RF performance of dual material cylindrical MOS

Significant down‐scaling of device dimension has made cylindrical gate MOSFET (CG‐MOS), a cutting edge device for low power applications. But in order to sustain the competition for real‐time devices, it should have improved RF performances as well. In this paper, an analytical model of dual material cylindrical gate MOSFET (DMCG‐MOS) with underlap engineering has been developed using the solution of 2‐D Poisson's equation. The electrical parameters such as surface potential, threshold voltage and drain current are determined and compared with that of conventional CG‐MOS. The effect of the variation of underlap length on the DC/RF performance of the model has been extensively discussed. The results show improvement in the performance of threshold voltage, leakage current and transconductance generation factor (TGF) with the introduction of underlap at the drain end. On the contrary, the model with source underlap exhibits better drain current and higher cut‐off frequency. The analytical results are validated using Sentaurus TCAD device simulator. The improvement in DC and RF performance of this model would address emerging challenges posed by high frequency and low power applications. Copyright © 2016 John Wiley & Sons, Ltd.