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Influences of the wafer-level testing method on unclamped inductive switching

For power MOSFETs used in industrial and automotive applications, the Unclamped Inductive Switching Safe-Operating Area (UIS-SOA) is critical for motion control, especially when used as a pulse-width modulation control device. The current after turn-off of the inductive load will flow through the device's source/body diode in an avalanche condition, placing a large current and thermal load on the device. Robustness to this loading is the key to the durability of the power MOSFET, and is described by the supported time in avalanche (tAV), the current in avalanche (IAV), and a ruggedness rating known as the K value. The process window for UIS is bounded by thermal failure at long times in avalanche (tAV) and by latch-up failure in high current, short tAV conditions where parasitic bipolar devices can activate and cause localized failure. Determination of the device capability in wafer level testing proves difficult as thin die are required for RDSon characterization while thick die are more robust to thermal failures, and the die thickness is shown to impact the IAV value at larger inductor values.