{'fraction_non_alphanumeric': 0.02987205848754855, 'fraction_numerical': 0.016563856522732467, 'mean_word_length': 4.4477286869944, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 1, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
2-output spin wave programmable logic gate

This paper presents a 2-output Spin-Wave Programmable Logic Gate structure able to simultaneously evaluate any pair of AND, NAND, OR, NOR, XOR, and XNOR Boolean functions. Our proposal provides the means for fanout achievement within the Spin Wave computation domain and energy and area savings as two different functions can be simultaneously evaluated on the same input data. We validate our proposal by means of Object Oriented Micromagnetic Framework (OOMMF) simulations and demonstrate that by phase and magnetization threshold output sensing AND, OR, NAND, NOR and XOR and XNOR functionalities can be achieved, respectively. To get inside into the potential practical implications of our approach we use the proposed gate to implement a 3-input Majority gate, which we evaluate and compare with state of the art equivalent implementations in terms of area, delay, and energy consumptions. Our estimations indicate that the proposed gate provides 33% and 16% energy and area reduction, respectively, when compared with spin-wave counterpart and 42% energy reduction while consuming 12x less area when compared to a 15 nm CMOS implementation.


I. INTRODUCTION
During the past decades, the human society experienced an information technology revolution that resulted in a huge increase of easy available raw data, which processing requires efficient computing platforms ranging from high-performance clusters to simple Internet of Things (IoT) nodes 1,2 . However, CMOS downscaling that provided the means to meet the data processing energy and performance requirements 3 became more and more difficult due to various technological hurdles indicating that Moore's Law will soon come to its end mainly because of: (i) leakage wall 4,5 , (ii) reliability wall 6 , and (iii) cost wall 4,6 . Therefore, to keep the pace with "exploding" market needs, novel alternative technologies are under investigation 3 . Among them Spin-Wave (SW) stands apart as one of the most promising avenue 3,7,8 because it has: (i) ultra low power consumption potential -SW based calculations are performed by means of SW interactions and do not require charge movements, (ii) acceptable delay, and (iii) high scalability -SW wavelengths can reach into the nm-range.
Therefore, novel Spin Wave technology circuit design methodologies are of great interest.
Up to date different SW logic gates have been introduced, e.g., [9][10][11][12][13][14][15][16][17] . The current controlled Mach-Zehnder interferometer was employed to construct a NOT gate, which is considered to be the first experimental work to implement logic gates using spin-waves 9 . Afterwards, XNOR, NAND and NOR gates were implemented using Mach-Zehnder as well 10,11,18 . Furthermore, a magnon transistor has been utilized to build an XOR gate by embedding two transistors in the Mach-Zehnder interferometer arms 12 . Moreover, research was conducted to implement voltage controlled XNOR and NAND using two parallel re-configurable nanochannel magnonic devices 13 . Information encoding in SW phase rather than in SW amplitude also proposed 14 and buffer, inverter, AND, NAND, OR, NOR and XOR gate designs introduced 14 . Furthermore, a 3-input majority gate design, which can perform 2-input AND and OR by assigning one of its inputs to 0 or to 1, respectively, was presented 14 . In addition, OR and NOR were implemented using the cross structure 15 . Furthermore, two experimental prototypes for majority gates were presented 16 and 17 . However, due to SW interaction way of operation, all of the reported logic gate designs cannot provide fan-out support, which is an essential gate feature for the effective implementation of larger circuits. Hence, if a SW gate output should serve as input for multiple following gates in the circuit it has to be replicated, leading not only to area overhead, but also to higher energy consumption. This paper solves the above limitation and proposes a 2-output Programmable Logic Gate (PLG). Depending on the design of the structure, the 2 outputs can produce the same or different functions simultaneously. The main contributions of this work are: • Design of 2-input 2-output PLG: Two logic functions (including AND, NAND, OR, NOR, XOR and XNOR) can be implemented using a single 2-output structure. For example, assuming that the gate inputs are x and y it can simultaneously provide both AND(x, y) and XOR(x, y).
• Validation of gate functionality: Object Oriented Micromagnetic Framework (OOMMF) software is used to successfully validate the proposed gate behaviour for all considered Boolean functions and input cases.
• Demonstration of the superiority: The evaluations indicate that the proposed 2-output gate saves 33% of energy and 16% of area without incurring any delay penalty when compared with functionally equivalent designs based on state-of-the-art spin-wave gates. Moreover, the proposed design outperforms 15 nm CMOS in terms of energy and area by providing an energy reduction of 42% while consuming 12x less area.
The rest of the paper is organized as follows. Section II provides basic spin-wave technology background. Section III describes the proposed Programmable Logic Gate design.
Section IV introduces the OOMMF simulation setup and results while in Section V we evaluate the proposed design, compare it with the state of the art, and discuss issues like scalability, variability, and thermal noise effects. Section VI concludes the paper.

II. SW TECHNOLOGY BACKGROUND
A Spin Wave (SW) is the collective spin excitation in a magnetic system 19 and this precessional motion of the magnetization is described by the Landau-Lifshitz-Gilbert equation 2021 as: where α is the damping factor, γ the gyromagnetic ratio, M s the saturation magnetization, m the magnetization and H ef f the effective magnetic field given by where H ext is the external field, H ex the exchange field, H demag the demagnetizing field, H ani the magneto-crystalline field and H sh ani the shape field. The main interactions which give rise to spin waves are the exchange and dipolar interaction for respectively short and long wavelength spin waves 19 . Depending on SW propagation direction relative to the orientation of the magnetization and effective magnetic field, different SW types can be excited and each has its own characterstics. Three main spin-wave regimes exist depending on the wavelength: exchange spin-waves, exchange-dipole spinwaves, and dipole (magnetostatic) spin-waves. There is a single dispersion relation, which one characterised with its own dispersion relation 23 . We note that FVMSW in-plane propagation is isotropic and as a result the same wave number is excited in all directions, which is not the case for other types. In view of this FVMSWs are the most promising from the circuit design prospective 23 and are utilized in this paper.
As depicted in Figure 1 spin-waves at different frequencies (f ) 25,26 . This makes it possible to use spin-waves as data carriers and their interaction as data processing mechanism to enable parallelism in SW circuits. If multiple waves co-exist in the same waveguide, their interactions is based on the interference and superposition principles. When SWs interfere in the waveguide, their interaction can be constructive or destructive depending on their phase difference. Figure 2 illustrates these two cases. Two spin waves having the same wavelength (λ) constructively interference if they have the same phase (∆φ = 0) and destructively if they are out of phase (∆φ = π). If more than two waves coexist in the waveguide, then their interference results is based on a majority decision. By assuming that input SWs can have phases φ = 0 or φ = π their interference results in a SW with φ = 0 if the majority of inputs have φ = 0, and in a SW with φ = π otherwise. This implies that SW interaction provides natural support for, e.g., single gate 3-input majority function implementation, which in a CMOS technology based Boolean logic based implementation requires 18 transistors 14,27 .

III. 2-INPUT 2-OUTPUT PROGRAMMABLE LOGIC GATE
This section describes the proposed gate structure and discusses different logic gate em-

bodiments.
A. Proposed Programmable Logic Gate Structure Figure 3 graphically depicts the topology of the proposed programmable logic gate that has a ladder shape structure. It has 2 inputs (I 1 and I 2 ) placed on the stair's stpdf and Phase detection method is based on a predefined phase reading, i.e., if the detected spin wave has a phase of π, then the result is logic 1, and a logic 0 if the detected spin wave has a phase of 0. However, threshold detection method is based on a predefined threshold, i.e., if the output magnetization is greater than or equal to a certain threshold, then the gate output is 0 and 1 otherwise.

B. Logic Function Programming
The logic function performed by the structure in Figure 3 depends on the detection mechanism as follows: (i) If phase detection is utilized the gate can evaluate (N)AND and (N)OR operators and (ii) if threshold detection is in place the structure implements X(N)OR.
To explain the programmable 2-input gate operation based on phase detection, we consider the structure in Figure 3 under the assumption that the control signals are C 1 = 0 and C 2 = 1. If a logic 0 is applied on both I 1 and I 2 , spin-waves with the same frequency, wavelength, and phase are excited in both horizontal waveguides. In the first stage, SW generated at I 1 constructively interferes with the one generated at C 1 . The resulting SW continues the propagation downwards in the waveguide and eventually constructively interferes with the spin wave emitted by I 2 , which results in a logic 0 at the output cell O 1 because the interference results in a SW with phase of 0. If I 1 = 0 and I 2 = 1, the waves (from C 1 and I 1 ) interfere constructively and the resulted SW propagates downwards to destructively interfere with the wave from I 2 , which results in a logic 0 at the output cell O 1 because the interference results in a SW with phase of 0. When I 1 = 1 and I 2 = 0, the waves from the I 1 and C 1 interfere destructively, which diminishes the resulted SW energy to a minimum if not make it vanish completely. Thus, the wave emitted by I 2 is the only one still present in the waveguide and propagates to the output resulting in a logic 0 at O 1 because the interference results in a SW with phase of 0. Finally, when I 1 = 1 and I 2 = 1, the same interference as in the previous case happens but since I 2 is now logic 1, the output is logic 1 at O 1 because the interference results in a SW with phase of π. Thus, the left side of the structure behaves as an AND gate. Following the same line of reasoning, one can easily demonstrate that the right side behaves as an OR gate. By changing the control signals values to C 1 = 0 and C 2 = 0, C 1 = 1 and C 2 = 0, and C 1 = 1 and C 2 = 1 the gate functionality is changed to where m x and m y are the x and y magnetization components, respectively.
We also note that, as output detection methods are not mutually exclusive, one output can be read in phase and the other one by thresholding, which enables the parallel evaluation of mixed function pairs, e.g., (AND,XOR), (OR,XOR).

IV. SIMULATION SETUP AND EXPERIMENTS
To validate the behaviour of the proposed SW programable gate we make use of an Object Oriented MicroMagnetic Framework (OOMMF) 28 based simulation platform.
During the OOMMF simulations we made use of the parameters summarized in Table I Table I and wavelength, the SW frequency is determined as f = 9 GHz at a spin wave number k = 2π/λ = 57 rad/µm.  constructive interference occur (resulting in a weaker output). Thus, the output detection mechanism must be able to deal with such variability phenomena. Table II presents  in this case is obtained when I 1 I 2 = 00. Note that the results for the other possible control input combinations, i.e., C 1 C 2 =01, C 1 C 2 =10, and C 1 C 2 =11, are similar to those obtained for C 1 C 2 = 00.

B. Threshold Detection based XOR/XNOR gate
The basic idea behind the threshold based output value interpretation is to define an appropriate MSA value M SA th and, e.g., classify the gate output as 0 if its MSA value is larger than M SA th and 1 otherwise. By applying this principle on the Table II values and choosing M SA th = 0.41 the gate outputs will be both 0 if I 1 I 2 = 00 and I 1 I 2 = 11 and 1 otherwise, which means that the gate provides the XOR functionality. If the detection rule is changed such that logic 1 is reported when the normalized MSA value is larger than M SA th and logic 0 otherwise, the proposed structure evaluates an XNOR function. Thus, in this case the output reading location is not relevant as the inverted version of the output is obtained by switching the thresholding rule.

V. PERFORMANCE EVALUATION AND DISCUSSION
To asses the implications of our proposal, we make use of the proposed gate to implement a fanout of 2 3-input majority (MAJ3) gate, evaluate its area, delay, and energy consumption and compared it with the state of the art SW 30 , and 15 nm CMOS based counterparts.
To this end we instantiated a MAJ3 gate design with a waveguide width of 48 nm and λ = 96 nm and validated it by means of OOMMF simulations as presented in Figure 5. i.e., d 6 = d 7 = 0, (iv) MAJ3 gate outputs are directly driving the following SW gates, thus no delay and energy overhead is accounted for the ME cells at the gate output, and (v) The spin-wave through the waveguide propagation delay is negligible. Note that due to the SW technology early stage of development some of these assumptions might not accurately reflect the physical reality, but their discussion is out of the scope of this paper.
In addition, in order to compare with CMOS, we evaluated a 3-input Majority gate implemented with two NAND gates and one OR-AND-Invert (OAI) gate in 15 nm technology at V dd = 0.8 V, 25 • C, and an output load capacitance of 20 fF.  In the remainder of this section we briefly discuss issues related to the scalability of our proposal and some practical implementation aspects.
Logic Scalability: The proposed structure is certainly scalable in terms of inputs and outputs. Additional inputs can be added by increasing the number of ladder stpdf. However, as the number of inputs increases, the inputs nearer to the outputs must be excited at lower energy to compensate for the potential degradation due to the damping effect in the waveguides of the SW inputs traveling from more faraway inputs. If the SW propagation delay is neglected the gate delay is number of inputs independent, while the energy increases linearly as the it is proportional to the number of inputs. In addition, the area of the proposed structure increases linearly with the number of inputs as the structure length increases by w + λ when an input is added to the structure and the structure width is constant. In term of outputs, the scalability is limited by the number of columns. However, because SW propagates in all directions the two columns can be vertically extended such that outputs (up to 4) can be read both at the top and bottom of each column. Thus the number of inputs and outputs of the proposed structure can be increased as depicted in Figure 6, but the detailed design of such a structure is out of the scope of this paper. Balanced Spin Wave Strength: It was noticed that the controls and data inputs contribute differently to the outputs. This is related to the fact that the control inputs have a larger contribution to the outputs than the data inputs as they have a direct straight path to the output, while the data inputs have bent region at the edges. Therefore, C 1 and C 2 must be excited at lower energy than I 1 and I 2 to balance the spin waves strength, and guarantee that the gate functions correctly. Furthermore, it was observed that all inputs C 1 , C 2 , I 1 and I 2 affect both outputs O 1 and O 2 . Thus, C 1 has an effect on O 2 , and C 2 has an effect on O 1 , which might create a problem when different gates are captured at both outputs O 1 and O 2 . Therefore, to guarantee a proper gate functioning correctly, it must be ensured that C 1 , I 1 and I 2 contribute more on output O 1 compared to C 2 , and that the contribution of C 2 , I 1 and I 2 on output O 2 is more than the contribution of C 1 .

Variability:
The main purpose of this paper has been to propose the concept and validate it by means of micromagnetic simulations under ideal conditions even if it is obvious that waveguide dimension variations, edge roughness, and spin wave strength variation might affect the gate functionality. However, given the actual development of the SW technology such aspects cannot be investigated for the time being but we certainly consider them as future work when relevant technology data became available.
Thermal Noise: Generally speaking the thermal noise is a circuit design crucial issue.
However, for spin wave technology, the Curie temperature, which is the temperature at which the magnetic properties of the material are changing, is high for the ferromagnetic materials, e.g., Curie temperature for CoFeB=1000 K 19 ). So, it is expected that limited temperature variations over the room temperature do not fundamentally affect the gate behaviour. However, further investigations on the thermal impact are part of planned future work. 801055.