{'fraction_non_alphanumeric': 0.031799163179916316, 'fraction_numerical': 0.010878661087866108, 'mean_word_length': 5.328042328042328, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
VLSI implementation of a CDMA blind adaptive interference-mitigating detector

This paper presents the design and the main performance results of a single-ASIC implementation of the recently proposed extended complex-valued blind anchored interference-mitigating detector (EC-BAID) for code division multiple access (CDMA) transmission. Such a detector, which exhibits a remarkable robustness to multiple access interference, operates in blind mode, i.e., it only requires knowledge of the timing of the wanted user's signature code, and it is therefore very well-suited for integration into handheld single-user terminal demodulators. The implementation of the interference-mitigating detector is based on a patented optimized architecture which leads, in 0.25-/spl mu/m CMOS technology, to a roughly 25 Kgate plus 23-Kbit RAM single-chip ASIC supporting chip rates up to 4 Mchip/s with a maximum internal clock frequency of 32.768 MHz. The main design drivers are thoroughly discussed, and the relevant performance results are compared to the theoretical behavior. A possible extension to multirate CDMA systems adopting orthogonal variable spreading factor (OVSF) sequences is also addressed.