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High speed single-ended pseudo differential current sense amplifier for SRAM cell

With reducing feature sizes, SRAM stability has become a major concern for future technologies. This critical issue can be solved by using highly stable separate bit-line read SRAM cell, but access time improvement becomes critical, since differential sense amplifier cannot be used for single bit-line read operation. In this paper, a novel pseudo differential single ended current mode sense amplifier is proposed. We demonstrate that this design can deliver a performance similar to that of conventional current mode differential amplifier without using dual bit-line for read operation. The overall read operation delay of the proposed single-ended design is almost 60% less than conventional single-ended design in 90 nm CMOS technology. The proposed design consumes 51.6% less energy than conventional design counterpart.