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Exploiting network redundancy for low-cost neural network realizations

A method is presented to optimize a trained neural network for physical realization styles. Target architectures are embedded microcontrollers or standard cell based ASIC designs. The approach exploits the redundancy in the network, required for successful training, to replace the synaptic weighting and the neuron transfer functions by ones that can be implemented with smaller cost. Redundancy indices are used to identify the network elements that are candidates for optimization to be performed by the judicious application of local, behaviour-invariant transformations. The usefulness of the presented approach is illustrated by a image processing application realized in our lab.