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Fault Detection and Modification of Substitution Box In Advanced Encryption Standard

The faults that accidently or maliciously occur in the hardware implementations of the Advanced Encryption Standard (AES) may cause erroneous encrypted/decrypted output. The use of appropriate fault detection schemes for the AES makes it robust to internal defects and fault attacks. In this paper a lightweight concurrent fault detection scheme is presented for the AES. In the proposed approach, the composite field S-box and inverse S-box are divided into blocks and the predicted parities of these blocks are obtained. Through exhaustive searches among all available composite fields, it is found the optimum solutions for the least overhead parity-based fault detection structures. Moreover, through the error injection simulations for one S-box (respectively inverse S-box), and show that the total error coverage of almost 100% for 16 S-boxes (respectively inverse S-boxes) can be achieved. Finally, it is shown that both the application-specific integrated circuit (ASIC) and field-programmable gate-array (FPGA) implementations of the fault detection structures using the obtained optimum composite fields, have better hardware and time complexities compared to their counterparts.