{'fraction_non_alphanumeric': 0.021493212669683258, 'fraction_numerical': 0.006787330316742082, 'mean_word_length': 4.6369426751592355, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design and implementation of a power and speed efficient carry select adder on FPGA

Adders are one of the most common unit in digital systems. The speed, power and area occupied by an adder play a vital role in Digital Signal Processing system, Image Processing system, etc. Hence, they play an important role in deciding the time period of the clock, the place and route of various units comprising of the system and total power consumed by the system. In this paper, we propose a new architecture for a modified sequential high speed carry select adder. We have given emphasis on optimizing the time period of the clock and power consumed, by using the carry ahead generation technique of Carry Look Ahead Adder (CLAA) and multiplexing technique of Carry Select Adder (CSA). The proposed CSA was implemented on Virtex-7 and results were calculated using Vivado Design Suite 2014.4.