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Nanophotonic On-Chip Interconnection Networks for Energy-Performance Optimized Computing

1. Introduction Much recent progress in silicon nanophotonic technology has enabled the prospect of high-performance nano-photonic networks-on-chip (NoCs), which have become very attractive solutions to the growing bandwidth and power consumption challenges of future high-performance chip multiprocessors [1–4]. The design of our high-performance nanophotonic NoC commences at the individual silicon nanophotonic device and produces a full-scale on-chip optical interconnection network. Nanophotonic NoCs introduce a logical solution to the challenges of interconnecting chip multiprocessors since (1) photonic links provide very large bandwidths, methodically scalable with the wavelength parallelism of the optical domain, and (2) photonic messages can be routed in a highly energy-efficient manner. Moreover, the equivalent power consumption of on-and off-chip photonic signaling makes the on-chip photonic communications infrastructure also beneficial for off-chip memory accesses. Significant advancements in CMOS-compatible silicon nanophotonic technologies have provided a viable path toward the realization of nanophotonic NoCs, due to mature processing capabilities and high index contrast, which affords dense photonic integration. Today, all of the necessary components for constructing simple nanophotonic NoCs (e.g. modulators [5], switches [6–8], photodetectors [9]) have been demonstrated, and designers currently strive toward obtaining performance improvements and increasing the level of device integration [7].