{'fraction_non_alphanumeric': 0.04326530612244898, 'fraction_numerical': 0.013877551020408163, 'mean_word_length': 4.980487804878049, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Ultrathin Ge-on-Insulator Metal Source/Drain p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated By Low-Temperature Molecular-Beam Epitaxy

We demonstrate the enhancement of hole mobility in an ultrathin Si/Ge/Si-on-insulator (SOI) channel metal–oxide–semiconductor field-effect transistor (MOSFET) with a metal source and drain (S/D). The ultrathin Si/Ge structure is fabricated on a SOI substrate by low-temperature molecular-beam epitaxy (LTMBE). We examined the impact of the Si/Ge/Si structural parameters and the crystal quality on the electrical characteristics of MOSFETs, particularly from the viewpoints of the Ge thickness and the annealing temperature. As a result, the hole mobility of the fabricated Ge-on-insulator (GOI)-pMOSFETs after annealing at 600 °C was found to be 1.2 times larger than the Si universal hole mobility. For the Ge thickness dependence of hole mobility, the MOSFETs with the Ge thicknesses of 8, 12, and 16 nm had almost the same mobility. On the other hand, the sample with 4 nm Ge thickness had lower mobility. For the annealing temperature dependence, the hole mobility had a maximum value at 600 °C and decreased with increasing annealing temperature above 700 °C.