{'fraction_non_alphanumeric': 0.027422303473491772, 'fraction_numerical': 0.0, 'mean_word_length': 4.5353535353535355, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
New fast-lock PLL for mobile GSM GPRS applications

This paper presents a new Fast-Lock synthesizer for the recent GSM evolution GPRS, HSCSD and EDGE. The concept provides half the lock-in time of a common integer-N PLL with state-of-the-art phase noise and improved spurious suppression. Measurements of a high integrated GSM transceiver using the Fast-Lock concept show a sufficient lock-in time for the new standards. The PLL functional block can easily be used in large scale integrated GSM-transceivers for the next generation of GSM mobiles.