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Spur-free all-digital PLL in 65nm for mobile phones

After the first-ever all-digital PLL (ADPLL) [1] for Bluetooth radios has proven benefits of CMOS scaling and integration, demonstrators for more challenging wireless standards have emerged [2–6]. In the ADPLL, however, the digitally-controlled oscillator (DCO) and time-to-digital converter (TDC) quantize the time and frequency tuning functions, respectively, which can lead to spurious tones and phase noise increase. As such, finite TDC resolution can distort data modulation and spectral mask at near integer-N channels, while finite DCO step size can add far-out spurs and phase noise. Also, a major underreported issue is an injection pulling of the DCO due to harmonics of the digital activity at closely-spaced frequencies, which can also create spurs. This work addresses all these problems and demonstrates RF performance matching that of the best-in-class traditional approaches.