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Reconfigurable signal processing ASIC architecture for high speed data communications

A flexible and reconfigurable signal processing ASIC architecture has been developed, simulated and synthesized. The proposed architecture can be used to realize any one of several functional blocks needed for the physical layer implementation of high speed data communication systems operating at symbol rates over 60 Msamples/sec. In fact, multiple instances of a chip based on this architecture each operating in a different mode can be used to realize the entire physical layer of high speed data communication systems. The architecture features the following modes (functions); real and complex FIR/IIR filtering, least mean square (LMS) based adaptive filtering, Discrete Fourier Transforms (DFT), and direct digital frequency synthesis (DDFS) at up to 60 Msamples/sec. All of the modes are mapped onto a common, regular datapath with minimal configuration logic and routing. Multiple chips operating in the same mode can be cascaded to allow for larger blocks.