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A Parallel Architecture for the Self-Sorting FFT Algorithm

Abstract The self-sorting (SS) algorithm is a highly efficient version of the fast Fourier transform (FFT), because, unlike the generally used algorithms, it does not require shuffling the sequence to be transformed (digit reversal), In this work, we propose a parallel architecture that implements the SS radix r (r ≥ 2) algorithm. The data flow of the algorithm is decomposed, in a natural way, into two sections that are implemented by means of FIFO queues located in the processors and an interprocessor connection network (perfect unshuffle). The resulting design is regular and modular, and, whenever possible, presents constant geometry. The total processing time required is nN/rQ cycles for a transform of size N = rn computed using Q = rq processors. Consequently, there are no cycle losses.