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AVOIDING ILLEGAL STATES IN PSEUDORANDOM TESTING OF DIGITAL CIRCUITS

Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of logic values in digital circuits and two techniques for preventing them from damaging the circuit or corrupting test results. Our techniques require minimal change to the design and impose almost negligible delay overhead. Simulation results show that the area overhead of our techniques is less than 1% for applying the techniques with on-chip hardware. The techniques can be applied from an external tester with one bit per pattern overhead. Unlike previous techniques, the fault coverage of the legal test patterns in a given test set is not sacrificed with our techniques. Furthermore, our techniques are applicable during IC production test, BIST, board-level tests and system-level tests. Funding: This work was supported in part by King Fahd University of Petroleum and Minerals, by DARPA under contract No. DABT63-97-C-0024 (ROAR project), and by NSF under contract number CSLFY00-28.