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Shift-aware racetrack memory

In this work, we exploit racetrack memory for L2 cache in GPGPUs. Racetrack memory is a memory technology in which several bits of data are packed into the domains of a ferromagnetic wire. While racetrack memory reduces power consumption compared to CMOS technology, it increases access time. To read or write a memory bit, memory cells should be shifted serially until the requested bit reaches to an access port. This increases latency of L2 cache and hurts performance. To address this challenge, we use address predictors to pre-shift memory cells ahead of time. Our evaluations using a set of GPGPU applications reveal that our speculative approach is effective and is able to reduce performance penalty of racetrack memory.