{'fraction_non_alphanumeric': 0.02631578947368421, 'fraction_numerical': 0.0, 'mean_word_length': 5.237704918032787, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Performance and Communication Driven Hardware Synthesis: Problem Formulation and Theory Review

In this paper we frame and propose a step-by-step methodology for building complicated microarchitectural implementations of ISA’s (Instruction Set Architectures). This methodology uses incremental refinement, abstraction, and mapping. We review the current state of the art theory as well as the work that we plan on leveraging. Few have created tools for optimally scheduling or synthesizing pipelines for in-order non-floating point processors, but, to our knowledge, no one has extended this to processors with floating point instructions and out-of-order execution. We lay out the steps of our methodology and present a simple example of how it might be used.