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A Low-voltage low-power programmable 5 GHz frequency synthesizer in standard 0.18 µm CMOS process

A low-voltage programmable frequency synthesizer with 12.5  mW power consumption is designed for wireless communications. This synthesizer is implemented using Taiwan Semiconductor Manufacture Company (TSMC) 0.18 µm 1P6M triple-well technology, with an operating voltage of 1.5 volts, and an output frequency range from 4.58 GHz to 5.20 GHz. Based on the structure of phase-locked loop, we developed this fully integrated frequency synthesizer using the phase-locked (PLL) loop structure, consisting of a phase/frequency detector (PFD), a charge pump, a low-pass filter, a voltage-controlled oscillator, and a frequency divider. The PFD is composed of dynamic two-phase master-slave pass-transistor flip-flops. Only single-edge clocks are used to minimize clock skew. To reduce the charge sharing and clock feed-through problems a novel charge pump structure is designed. A three-order low-pass filter is used to filter out the high-frequency alias of charge pump circuit. The voltage-controlled oscillator adopts a novel differential Colpitts oscillator structure to increase the oscillator frequency to 5 GHz. An injection-locked frequency divider is used in the PLL feedback path to reduce the overall power consumption.