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Enhancing the efficiency and accuracy of cell-aware testing to reach zero defects

As semiconductor content penetrates deeper into our everyday lives, the quality of the electronic components that surrounds us becomes ever more important, particularly for those involved in safety-critical applications such as automated vehicles and healthcare. For integrated circuits (IC), cell-aware testing (CAT) is the latest advancement in the drive towards zero end-user defects. CAT targets physical defects such as bridges and opens at the transistor level inside standard logic cells used to construct the IC. A fairly onerous process involving extensive analog simulation is used to characterize cell behavior in the presence of defects, and create fault models to guide the generation of chip-level test patterns that can detect these physical defects. Assuming use of a single analog simulator license, cell-aware fault modeling (CAFM) for a library of standard cells can take up to weeks to months of computation. Moreover, for certain types of defects, stand-alone library-based CAFM fails to account for strong interactions with the cell's surrounding design context on an instance basis. As a result, the created fault model may fall short in generating the optimal chip-level test patterns for defect detection and accurate failure diagnosis. In this talk, we propose the idea of “in-situ” CAFM to properly account for cell instance design context. To realize in-situ CAFM in practice, drastic improvements in efficiency and performance of the characterization process is needed. We show how a transistor switch-based approach involving switch-level fault proxies and test generation can achieve the required performance gain by eliminating much unnecessary analog simulation. Early experimental data demonstrates CAFM can be improved by two orders-of-magnitude using our approach.