{'fraction_non_alphanumeric': 0.04231830726770929, 'fraction_numerical': 0.01839926402943882, 'mean_word_length': 5.044444444444444, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design of a Fully Integrated Two-Stage Watt-Level Power Amplifier Using 28-nm CMOS Technology

We present a linear two-stage power amplifier (PA) for UMTS terrestrial radio access (UTRA) applications. The PA has been designed using a standard 28-nm complementary metal-oxide-semiconductor process. It includes an on-chip input matching network, a predriver stage, and an on-chip output matching network. Additional process-voltage-temperature compensation circuits and electrostatic discharge protection have been implemented on-chip. A differential triple-stack transistor array acts as transconductance circuit and generates watt-level RF output power. Measured saturated output power is more than 31 dBm and peak power-added efficiency is 33% for sinusoidal operation at 1.8 GHz. When applying memoryless digital predistortion (DPD) for 3rd Generation Partnership Project (3GPP) UTRA test vectors, an adjacent-channel leakage ratio of ≤ -33 dBc at ±5 MHz for 26.5-dBm output power is achieved. A corresponding error-vector magnitude of ≤1.7% can be measured when using memoryless DPD.