{'fraction_non_alphanumeric': 0.018700787401574805, 'fraction_numerical': 0.003937007874015748, 'mean_word_length': 4.844827586206897, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
SIC-TPG for path delay fault detection in VLSI circuits using scan insertion method

The advent of deep submicron technology led to growing complexity of circuits and an increase in the design speed, making delay testing necessary for determining correct circuit behavior. Observation of path delay faults requires propagation of transitions in a circuit which is done by application of pair of patterns. This paper proposes a single input change test pattern generator (SIC- TPG) that creates SIC pairs and hence can be used for path delay fault detection. The same TPG also senses stuck-at faults in circuits. A path definition file is specified for benchmark circuit and mentor graphics fastscan tool is used to obtain the fault coverage. For the purpose of area overhead comparison, the TPG is coded in verilog and simulated by Xilinx ISE simulator and improved results are observed. Experiments conducted on ISCAS-85 and ISCAS-89 benchmarks show high stuck-at fault coverage and Path Delay Fault (PDF) coverage.