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Investigation of the induced gate noise of nanoscale MOSFETs in the very high frequency region

In this paper, we investigated the induced gate current noise of nanoscale N/PMOS devices. To analyze the induced gate noise, the induced gate current noise source model was analytically derived. By using the proposed model, the induced gate noise source was compared with other noise sources, and its impact on noise parameters was also analyzed in long-channel and nanoscale N/PMOS devices in the very high frequency region (>100 GHz). The results showed that the induced gate noise of sub-40 nm CMOS technology is negligible, even in the design of very high frequency circuits.