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Reducing power consumption in FPGA routing

One of the major drawbacks of field programmable gate arrays is their poor energy efficiency. This paper focuses on the routing phase of FPGA design and attempts to optimize dynamic power consumption in FPGA interconnect. Power optimization is performed with small side effects on circuit performance and area. Our enhancements to the VPR timing driven algorithm reduced the FPGA routing power by about 10% with negligible loss in circuit performance.