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Ways to Reduce FPGA Power Supply by Software Methods

The paper is devoted to solving the problem of reducing the power consumption of programmable logic integrated circuits (hereinafter FPGAs) by software methods. The solution of this issue is especially relevant for various types of radio engineering systems, which include autonomous and portable stations. At the beginning of the paper, the theoretical foundations of FPGA consumption are given: types of consumption (static and dynamic) and influencing parameters (switching logic, the physical foundations of the integrated circuit and other internal resources). The work is explained and methodological guidelines are given for the specialized built-in PowerAnalyzer utility of the Quartus II software development environment, the main indicators with which the utility works are explained: toggle rate (switching frequency) and static probability (the probability of finding a signal in a stable state "0" or "1"). The following is a Pipelinning method for eliminating the racing effect (the effect in which signals passing through an element/crystal reach the destination point with different time delays). The essence of the method is that a register is set at the output of the element that creates the delay. The register stores the value at the input at the CLK clock frequency, so random switching of the previous circuit element will be ignored. This eliminates the effect of racing and reduces the dynamic consumption of the circuit. At the end of the paper, the results of reducing energy consumption using the above methods are presented. The greatest gain is observed when minimizing consumption, when a large number of logic elements on the FPGA chip are involved, as well as when high-frequency operation occurs. This is due to the fact that when using the methods of switching off the clock frequency, we get rid of a large number of switches between the states of logic elements (the higher the frequency, the more such state switches per unit of time). If the number of occupied elements is more than 50%, we get a reduction in power consumption of more than 5%, and if the number of occupied elements is 75%, then we get a gain of about 14%.