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A temporal coding hardware implementation for spiking neural networks

Spiking Neural Networks (SNNs) models have been explored in recent years due to its biological plausibility where temporal coding plays an important role. Biological arguments and computational experiments suggest than some perceptual tasks (vision and olfaction for instance) are well performed by these models. Moreover, some other applications such as machine learning might be benefited from this approach. However, efficient simulation and implementation of SNNs still remain an open challenge. There are several issues that must be addressed, being one of them the temporal coding of real-value data itself. In order to study the possibilities of embedded real-time implementations of large scale SNNs, we have first chosen to implement a well-known coding scheme based on Gaussian Receptive Fields (GRFs) to map real-value data into spike trains. This paper proposes a configurable parallel FPGA based accelerator for GRF-based temporal coding. The proposed architecture of the hardware implementation is described in detail and implementation results, both performance and resource utilization, when mapped to a Virtex-II Pro FPGA device are reported.