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Novel digit-serial systolic array implementation of Euclid's algorithm for division in GF(2/sup m/)

In this paper, a novel digit-serial systolic array for computing divisions in GF(2/sup m/) over the standard basis is presented. To the authors' knowledge, this is the very first digit-serial systolic divider for GF(2/sup m/). The proposed architecture possesses the features of regularity, modularity, and unidirectional data flow. Thus, it is well suited to be implemented using VLSI techniques with fault-tolerant design. One important feature of the proposed architecture is that different throughput performances can be easily achieved by varying the digit size. By choosing the digit size appropriately, the proposed digit-serial architecture can meet the throughput requirement of a certain application with minimum hardware.