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Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture

Silicon-photonic links have been proposed to replace electrical links for global on-chip communication in future many-core processors. Silicon-photonic links have the advantage of lower data-dependent power and higher bandwidth density, but the high laser power can more than offset these advantages. We propose a solution to manage laser power of silicon-photonic network-on-chip (NoC) in many-core system. We present a silicon-photonic multibus NoC architecture between private L1 caches and distributed L2 cache banks which uses weighted time-division multiplexing to distribute the laser power across multiple buses based on the runtime variations in the bandwidth requirements within and across applications to maximize energy efficiency. The multibus NoC architecture also harnesses the opportunities to switch OFF laser sources at runtime, during low-bandwidth requirements, to reduce laser power consumption. Using detailed system-level simulations, we evaluate the multibus NoC architecture and runtime laser power management technique on a 64-core system running NAS parallel benchmark suite. The silicon-photonic multibus NoC architecture provides more than two times better performance than silicon-photonic Clos and butterfly NoC architectures, while consuming the same laser power. Using runtime laser power management technique, the average laser power is reduced by more than 49% with minimal impact on the system performance.