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Understanding and addressing the impact of wiring congestion during technology mapping

Traditionally, interconnect effects are taken into account duringlogic synthesis via wireload models, but their ineffectiveness forDSM technologies has been demonstrated and various physicalsynthesis approaches have been spawned to address the problem. Ofparticular interest is that logic block size is no longer dictatedexclusively by total cell area, yet synthesis optimizationobjectives are aimed specifically at minimizing the number and sizeof cells. Methodologies that incorporate congestion within thelogic synthesis objective function have been proposed in[9][10][11] and [15]; however, as we will demonstrate, predictingthe true congestion prior to layout is not possible, and theefficacy of any approach can only be evaluated after routing iscompleted within the fixed die size. In this paper we propose apractical, complete methodology which first performscongestion-aware technology mapping using a global weighting factorfor the cost function [15], and then applies incremental localizedunmapping and remapping on congested areas. This complete approachaddresses the problem that one global factor is not ideally suitedfor all regions of the designs. Most importantly, through theapplication of this methodology to industrial examples we will showthat any attempt at a purely top-down single-pass congestion-awaretechnology mapping is merely wishful thinking.