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Ultra-Fast Error Correction and Detection for Low-Latency Storage Applications with Emerging Memories

Emerging memory technologies (like PCM, MRAM and 3D XPoint) can make data storage as fast as the rest of the system. But to cope with the reliability targets of storage applications, error correcting codes (ECCs) able to correct many errors might be needed anyway. Hierarchical codes, ECCs enabling two levels of correction, can be good candidates to satisfy these reliability targets, without impacting (on average) the low-latency characteristics of these technologies. In particular, an Ultra-Fast (UF) ECC can be used as first trial as long as it is able to flag its failures with high probability and low latency. In this paper we design an UF-ECC able to produce a check for incorrect decoding with probability lower than the typical target uncorrectable bit-error rate (UBER) of storage applications (e.g. 1e-15) and with a latency comparable with the UF-ECC correction process.