{'fraction_non_alphanumeric': 0.02594142259414226, 'fraction_numerical': 0.0066945606694560665, 'mean_word_length': 5.39572192513369, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A cost-efficient self-checking register architecture for radiation hardened designs

The rapid development of CMOS technology has significantly increased the susceptibility of electronic systems to radiation-induced soft errors. Conventional error-tolerant techniques typically use redundancies to mitigate soft errors and increase system immunity. However they do not have self-checking capabilities, and therefore are still vulnerable to the errors in the redundant circuitry added for error-tolerance. This paper proposes a novel self-checking soft error-tolerant register based on SETTOFF, a Soft Error and Timing error Tolerant Flip-Flop. The register significantly improves the error-tolerant capability over previous techniques since it has a self-checking capability, which allows the register to tolerate both the errors in the original flip-flops and the redundant circuitry. In addition, the register can also tolerate both soft errors (SETs and SEUs) and timing errors. Compared with other previous techniques such as TMR, the proposed register reduces the power consumption overhead by 81%, and the delay overhead by 54% in 65nm technology; The area overhead is also reduced by 25%.