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Design of Architecture and Instruction-set of RASIP for SDR

In this paper, a novel methodology has been presented for designing the architecture and its instruction-set for Reconfigurable Application Specific Instruction-set Processor (RASIP) for Software Defined Radio (SDR). We have described the architectural aspects by giving complete functionality of different modules present in the architecture. Instruction set design for the RASIP for achieving SDR functionality has been described and modeled for proposed architecture. We have introduced new concept of the user-defined instructions that are used for upgradation and modification of existing instruction set after designing the RASIP to incorporate new functionality. This flexibility is essential for any SDR to incorporate new standards in future. The complete system has been modeled in SystemC, which will allow simulation of hardware and software in a single environment. Simulated results of partial instructions of Instruction-Set and complete architecture are presented.