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Three-phase magnitude-phased-locked loop using FPGA

A novel three-phase magnitude-phase-locked-loop system (3MPLL) which is implemented in the field programmable gate array (FPGA) for use in the general area of three-phase (power, energy and power electronic) systems is introduced. The 3MPLL is used as a three-phase nonlinear anti-aliasing filter with no phase-shift and no amplitude bias. Three unique features of such a filter are frequency adaptivity, unbalance mitigation, and structural simplicity or robustness. The paper presents the Hardware Implementation of the 3MPLL in SPARTAN-3 FPGAs. Characteristics of the 3MPLL including its mathematical equations as well as steady-state and dynamic responses are also discussed in this paper. From experimental results it can be concluded that the proposed 3MPLL suppresses the noise and distortion from the input signal, mitigates the unbalance, and synthesizes the instantaneous positive-sequence component of the input signal; thus it operates as a nonlinear adaptive notch (or band-pass) filter. The 3MPLL also adaptively tracks and estimates the magnitude, phase angle, and frequency of the input signal; thus its operates as a nonlinear state estimator. Structural simplicity and robustness of the 3MPLL system are its further features which make it desirable. The proposed 3MPLL has applications which require smooth and adaptive synthesis of the instantaneous symmetrical components.