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DFM reality in sub-nanometer IC design

The impact of sub-nanometer (below 90nm) effects on IC designs needs to be clearly understood to ensure that (1) manufacturing variations are considered during design to avoid catastrophic failures, and (2) the expected performance simulated in design is actually realized on silicon to avoid parametric failures. This paper discusses design for manufacturing solutions that enable designers to predict systematic manufacturing variations during design to detect and repair catastrophic and parametric failures. This paper presents real examples of design sensitivities to sub-nanometer manufacturing variations and the need to correctly analyze, optimize and verify the design before manufacturing by using appropriate EDA solutions which bring the effects of manufacturing variations in the design flow.