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FPGA Implentation of JPEG Image Compression

Image compression is important in various applications such as video networking, medical images, and multimedia applications where a large amount of data transmission, storage is necessary. The main aim of the Image Compression technique is to reduce the redundant data so that it can be transmitted and stored efficiently and there is no significant change in the quality of the image. This paper introduces the design of the JPEG image compression and decompression algorithm and its simulation using the software Model Composer. Each block of the JPEG Algorithm was coded and designed as IPs. These IPs were integrated into a complete system along with some built-in blocks in Model composer. Performance of the system is measured using parameters Peak Signal to Noise ratio (PSNR), Compression Ratio (CR) based on file size and data rate. These parameters are recorded and compared with images of different sizes and formats.