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Ultra Low Power Digital Front-End for Single Lead ECG Acquisition

A low power single lead electrocardiogram front end acquisition system in 0.18um CMOS process with supply voltage 0.5V is presented in this paper. The analog blocks in Low Noise Amplifier (LNA), filters and passive elements that performs amplification, DC offset cancellation is replaced by a Moving Average Voltage to Time Converter (MA-VTC) to get amplification and alias removal in the time domain. A digital feedback algorithm is used to cancel out the DC offset. The front-end structure is designed in the subthreshold region of MOS to reduce the power consumption in the circuit. The proposed architecture consumes 50nW of power with a gain of 670us/V.