{'fraction_non_alphanumeric': 0.02348993288590604, 'fraction_numerical': 0.0, 'mean_word_length': 4.811688311688312, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
An FPGA Hardware Trojan Detection Approach Based on Multiple Parameter Analysis

In this paper an FPGA Hardware Trojan (HT) detection approach based on multiple parameter analysis is proposed. In this direction, we apply a logic testing method, a run-time method and a side-channel analysis method. Logic testing and side-channel analysis methods are non-invasive while the run-time method is invasive in the sense that on-chip digital sensors are used to detect unexpected differentiations in the layout of the IC. The introduced methods do not rely on the presence of a "Golden chip" for detecting the HT. The proposed approach is implemented and evaluated on an actual FPGA board, providing practical results that validate our assumptions. To the best of our knowledge this is the first attempt for combining three different parameter analysis for HT detection in an of-the-shelf FPGA board.