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A hardware-in-the-loop system to evaluate the performance of small-world cellular automata

This paper presents the realisation of a hardware-in-the-loop system to investigate the performance of different cellular automata (CA) structures. The system is applied to regular lattice CAs and to small-world CAs, which are expected to expose better characteristics than lattice automata due to their nature-inspired structure. CA functionality is evolved using a genetic algorithm (GA) implemented as a distributed Java program running on a host computer. The performance evaluation of whole generations of individual automata is transferred to a specialised hardware architecture on an FPGA-board in order to speed up this process. For this, a customisable version of an automaton is residing on the board and personalisation data can be downloaded to it. The objective of the approach is to gather qualitative and quantitative data on the differences between the two types of CAs. We discuss two CA implementations, one of a lattice CA and one of a small-world CA. Their properties are characterised and their integration into the overall evaluation system is described.