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Design of Leakage Resilient and DPA Attack Immune Architecture of S BOX

Electronic gadgets such as mobile phones, laptops, IPad, home appliances and other gaming gadgets have become a part and parcel of our life and they have made the human life most comfortable. With the shirking of technology the gadgets have become handy and security of the devices is taken care by the field of cryptography. One of the best Cryptographic algorithm secured the data is Advanced Encryption Standard (AES) which is a combination of various steps. One of the major action involved in making the encryption is by Substitution of data with the help of Substitution box called as S Box. The threat on to the chips fabricated is Side Channel Attacks (SCA) and the popular SCA attacks are Differential Power Analysis (DPA). In cryptographic systems such are Smart cards, RFID tags, military applications and E-commerce applications cryptography plays a vital role. In this paper a Low power adiabatic logic with attack immunity is used to construct a Sub Byte transformation called as S Box of AES. It is implemented and found that the energy dissipated is reduced by 26% and 44% against the NDDPL and PFSAL Techniques. The efficiency of the proposed Dual Rail Single Clock Positive Feedback Adiabatic Logic (Dual Rail SCPFAL) S Box is verified by comparing it with the PFSAL based Rijndael S-Box. The DPA attack immunity is verified with the help of an efficiency factor called Coefficient of Deviation (CoD) or ∊ and is improved by 32% and 48% against NDDPL and PFSAL logic. The proposal is implemented and results are verified in Cadence Virtuoso 45nm technology and the power and current traces are compared at different temperature.