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Pipeline Defects in Flash Devices Associated with Ring OSF

Pipeline defects were known to occur in both bipolar and CMOS devices. It is reported that a possible physical correlation exists between a type of etch pit pairs (EPP) and pipeline defects on an EEPROM device. The density of EPPs, and the density of pipeline defects, was found to be significantly reduced by a 900°C anneal in nitrogen prior to N+ oxidation, and lower arsenic dose and thinner nitride in LOCOS for field isolation. In this article, we report for the first time a strong correlation observed between pipeline defects and the presence of V/I boundary in Czochralski-grown silicon substrate on a flash memory device. In our development of a flash product, pipeline defects shorting the cell source and drain were identified to be one of the major causes of yield loss. We report for the first time a strong correlation between pipeline defects and the presence of OSF ring in wafer with V/I boundary. We found that by changing the wafer substrate type to one with no V/I boundary and optimizing the pre-LOCOS thermal cycle, we were able to eliminate the pipeline defects without negative impact on device performance. INTRODUCTION Pipeline defects have long been reported to cause emittercollector shorts in bipolar devices [1]. Recently, pipeline defects have also been found in CMOS processes, causing source to drain shorts [2, 3]. Wang et al [2] suggested that the formation of pipeline defects was caused by stress generated during side wall mask isolation (SWAMI) etch at island corners. Belgal et al [3] found the correlation between pipeline defects and implant-induced damage in silicon. They eliminated the defects by introducing a low-temperature recrystallization step in an inert ambient. Soh et al [4] reported a possible physical correlation between a type of etch pit pairs (EPP) and pipeline defects on a EEPROM device. The density of EPPs, hence the density of pipeline defects, was found to be significantly reduced by a 900°C anneal in nitrogen prior to N+ oxidation, lower arsenic dose and thinner nitride in LOCOS for field isolation. DEVICE FAILURE ANALYSIS A 1Mb flash memory device with double diffused drain (DDD) is fabricated with P-type <100> substrate using LOCOS process. One of the major failure mode is bitline erase failure, where all the 64 bit cells along the failed bitline are classified as failed bits under erase test. A typical bit map picture is shown in Figure 1. The total number of the failed bitlines is quite random, ranging from 1 to about 20. In our case, “Erase” is defined as high Vt state. This means if a cell is classified as failed cell after erasing, there is still large current flowing out of the bitline when read biasing condition is applied. The read condition is illustrated in Figure 2. It can be seen that the unexpectedly large current can be from the cell under read mode, or any other cells along the same bitline with gate voltage set at 0. Since all the cells on the same bitline are failed, there can be two possibilities: 1) None of the cell is erased to a Vt which is high enough to suppress large current flow when Vcg_read is applied to the gate of the selected cell; or 2) One or some of the By changing the wafer substrate type to one with no V/I boundary and optimizing the pre-LOCOS thermal cycle, we were able to eliminate the pipeline defects without negative impact on device performance. cells are very leaky even when gate bias is set to 0 so no matter which cell is being read there will always be large current flowing out of the failed bitline. A 250 Kbit cell array test structure shows that the leakage current path is from cell source to cell drain, as shown in Figure 3. This indicates a direct short between cell source and drain exists. In addition to the electrical signature, the wafer map shows that the failed parts are distributed in a ring-like pattern near the edge of the wafer, as seen in Figure 4. Further failure analysis revealed the existence of a pipeline defect running across several bits along the failed sub-bit line (see Figure 5). As suggested by Wang et al [2], a direct short between source and drain, possibly due to enhanced phosphorus diffusion, is believed to cause the large leakage current observed during erase test. While very short time Wright Etch reveals the pipeline defects, longer time Wright Etch shows the existence of large amount of line shape OSF (oxidation-induced stacking fault) oriented along [110] direction. Although the OSF lines are not located exactly at the failure bits, the distribution of these stacking faults nicely overlaps the wafer map for the failed devices, i.e. ring-like distribution (see Figure 6). Further substrate analysis shows that high BMD (bulk micro-defects) density exists under the OSF ring. It is, therefore, believed that the OSF nucleate at bulk oxygen precipitates in a ring-like band pattern. PROCESS AND SUBSTRATE MODIFICATIONS While the formation of pipeline defects is yet to be understood, its ring-like distribution similar to OSF indicates that these two types of defects could be closely related. From our experience with previous flash processes, we have never observed any pipeline defects or ring OSF, although we used the same wafer substrates. So our approach is to eliminate the OSF ring and check whether pipeline defects are still there. It is well known that radial position of the ring OSF depends exclusively on the growth conditions, i.e. ratio of the pull rate (v) to the interfacial axial temperature gradient at the melt/crystal interface (g) [5]. In addition, the region enclosed by the ring is known to be vacancy rich, while the 146 S E M I C O N D U C T O R M A N U F A C T U R I N G ■ D E C E M B E R 2 0 0 3 T E C H N O L O G Y