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WAVELET PACKET TRANSFORM BASED ECG SIGNAL FILTERING IMPLEMENTED IN RECONFIGURABLE HARDWARE STRUCTURE

This work describes an implementation of a digital signal processing module for filtering ECG signals in a reconfigurable hardware structure (FPGA). The filtering structure, a Wavelet Packet decomposition based decomposition is implemented in Simulink with Xilinx blocksets. The used structure is a Diligent’s Xilinx University Program Virtex-II Pro Development System. The integrated Xilinx ISE software provides automatic generation of HDL code directly from the System Generator blocks that is then mapped to the Xilinx FPGA. This code is synthesized and implemented in a Xilinx FPGA in order to perform a hardware co-simulation. In order to evaluate the filtering procedure signal to noise ratio and root mean squared error are measured.