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Precision fault injection method based on correspondence between configuration bitstream and architecture (abstract only)

SRAM-based FPGAs are increasingly being used; however they are susceptible to SEUs. To emulate the effects of SEUs, a variety of fault injection techniques have been studied. As fault injection process helps little to SEU mechanism study. For further study, a novel Automated Precision Fault Injection System (APFIS) has been developed by Beijing Microelectronics Technology Institute (BMTI), which is engaged in the design, test, package, failure analysis of the Large-scale integration (LSI) and Very Large Scale Integration (VLSI). However, the APFIS is not precise enough. As a result, a more accurate precision fault injection method is studied in this paper. The Automated Precision Fault Injection System-II (APFIS-II) based on this method is made. As early Xilinx devices are still used in special applications without such useful tools, which allowing users to optimize their design conveniently. In this paper, APFIS-II is implemented with Virtex device to improve the reliability of system which contains early devices. The detailed information about the FPGA architecture and configuration bitstream is analyzed. After that, the correspondence between the FPGA resources on-chip and the configuration bitstream is drawn. According to the corresponding relationship, the bitstream is divided into several segments. By APFIS-II, faults are accurately injected into a certain segment instead of the entire bitstream. As a result, faults are able to be injected into a certain resource on-chip. Through this method, the fault injection process is more effective and more targeted, which helps a lot to the study of SEU mechanism and the mitigation techniques.