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Low Power and Area efficient Forward Error correction code for SRAM in FPGAs

As submicron technology scales, SRAM bitcell density increases on the chip. This results in an increase of soft errors due to radiation induced multiple-bits upsets (MBUs). SRAM uses SEC-DED [Single Error Correct – Double Error Detect] code along with word interleaving or column muxing to mitigate these soft errors. The number of SRAMs in FPGA is of the order of 1000. Each SRAM uses SEC-DED code to mitigate soft errors due to MBUs. Optimizing the ECC will save considerable amount of area and power for larger FPGAs. We propose a technique where area and power of the ECC can be reduced by 50%.