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A hysteretic comparator's influence on a current-mode ADC

A low-voltage low-power CMOS switched-current analog-to-digital converter is presented. The influences of a hysteretic comparator on the performance of the ADC are studied with the help of SPICE simulations. SPICE BSIM4 models are used to study the behavior of the overall circuit. The hysteretic comparator is devised to minimize the errors caused by current spikes at the input to the comparator. The current-mode A/D converter implements a multiply-by-2 scheme. The A/D converter starts converting for the most significant bit (MSB) of an input current. The input is multiplied by two using MOS transistors. The comparator then senses the current imbalance and then determines if the signal 2Iin is greater than Iref. The remaining bits are converted in the same manner. The aim of this study is to use such an ADC in the CMOS imagers to be realized in a low-cost standard digital process technology. Another aim of this study is to utilize a hysteretic comparator to quantize the full-scale range of signals (MSB to LSB) independent of the resolution. The proposed design allows users to easily set the hysteresis width of the comparator for a predetermined resolution without causing any performance degradation.