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Efficacy of Satisfiability Based Attacks in the Presence of Circuit Reverse Engineering Errors

Intellectual Property (IP) theft is a serious concern for the integrated circuit (IC) industry. To address this concern, logic locking countermeasure transforms a logic circuit to a different one to obfuscate its inner details. The transformation caused by obfuscation is reversed only upon application of the programmed secret key, thus preserving the circuit's original function. This technique is known to be vulnerable to Satisfiability (SAT)-based attacks. But in order to succeed, SAT-based attacks implicitly assume a perfectly reverse-engineered circuit, which is difficult to achieve in practice due to reverse engineering (RE) errors caused by automated circuit extraction. In this paper, we analyze the effects of random circuit RE-errors on the success of SAT-based attacks. Empirical evaluation on ISCAS, MCNC benchmarks as well as a fully-fledged RISC-V CPU reveals that the attack success degrades exponentially with increase in the number of random RE-errors. Therefore, the adversaries either have to equip RE-tools with near perfection or propose better SAT-based attacks that can work with RE-imperfections.

I. INTRODUCTION Logic locking has been proposed to mitigate hardware IPtheft, which is a serious concern for the IC industry [1]- [18]. Logic locking is, unfortunately, known to be vulnerable to Satisfiability (SAT)-based attacks [19]- [29]. But all SATbased attacks assume a perfectly reverse-engineered circuit. This assumption may be invalid if the adversary purchases the IC from the open market, captures images and uses machine learning for automated circuit extraction, which is error prone [30]- [32]. There is, however, no prior work on evaluating the impact of reverse-engineering (RE) errors on attack accuracy. In this paper, for the first time, we analyze and quantify the effect of such errors. The primary contributions of the paper are as follows: • We propose an error model for RE and evaluate the attack accuracy for single as well as multiple random error scenarios.
• We identify different error scenarios which can and cannot be canceled out by applying the suitable key.
• Using benchmarks as well as a RISC-V CPU, we quantify the impact of RE-errors on the attack accuracy.
• Surprisingly, we unveil that in the presence of errors, increasing logic locking amount can reduce the security. Our research reveals that SAT-attacks can fail even if there is a single RE-error, but there may be cases of attack success with a reasonably high error count. The conclusions of our paper is threefold. First, the RE tools typically need high accuracy for attacking logic locking. Second, end-user adversary needs better SAT attacks to work with RE-errors. Third, in majority of the cases adding more locks to the circuit increases attack success (reduces the security-level) in the presence of errors.
II. SATISFIABILITY-BASED ATTACK SAT-solvers find the inputs to a Boolean expression such that the expression evaluates to true. The adversary can thus formulate the locked circuit obtained through RE as a Boolean expression and use Boolean SAT-solvers to find a secret key for the given input-output pairs. The fundamental challenge is, however, to extract the secret key by observing a limited set of input-output pairs. Therefore, straightforward SAT-solver usage is ineffective-although it returns a key, the key may only satisfy the limited set and not guaranteed to satisfy inputoutput pairs outside this set. SAT-attack solves this problem by two intuitions.
First, unlike cryptographic constructions, the secret key itself may not be unique, causing multiple keys to form equivalence-classes that would generate identical input-output pairs. Second, a wrong-key equivalence-class can be pruned off by determining the distinguishing input pattern (DIP), a certain input pattern which produces different outputs for two keys from two different equivalence classes. As a result, the attack aims to perform a brute-force search on key equivalenceclasses, which is more efficient than performing brute-force search on individual keys.
The attack at a high-level works as follows. The adversary reconstructs the locked netlist through RE and formulates the circuit as a SAT-instance to find the DIPs. The adversary then gets an activated chip from the market that can generate valid input-output pairs. This chip is referred to as the oracle. The adversary applies the DIP to the oracle and records the output. The DIP-output pair is used to prune-off wrong equivalence class(es) of keys by updating the SAT-instance. The process continues until there is only one equivalence class left, which has to be the equivalence class of the correct keys. Now we formally describe the attack. Let the reverseengineered locked circuit be C( X, K, Y ), which has input vector X and output vector Y , and which is locked with key Algorithm 1: SAT-based Logic Decryption Algorithm [19] Input: C and eval Result: K c i := 1; vector K. Let the locked circuit has M input bits and L gates. Algorithm 1 shows the SAT-attack in detail, where i signifies the iteration number. F 1 is the initial SAT-instance and F i is the SAT-instance in the i th iteration. Each step of the algorithm is defined as follows: Step 2: Formulates the SAT-instance as two copies of the locked circuit C( X, K 1 , Y 1 ) and C( X, K 2 , Y 2 ) with same input X but different keys K 1 , K 2 and different outputs Y 1 , Y 2 . In the next step, this formulation is exploited to generate different keys that produce different outputs.
Step 3: Checks if the there are at least two different equivalence classes that satisfy the current SAT-instance. If this condition is satisfied, it enters the loop, otherwise terminates the loop; Step 4: Runs the SAT-solver on the current SAT-instance. From the returned SAT assignment { X, K 1 , Y 1 , K 2 , Y 2 }, this step also extracts the DIP for i th iteration, denoted as X d i , Step 5: Evaluates the oracle output for X d i , denoted as Y d i .
Step 6: Adds corresponding DIP-output constraints to the to eliminate wrong-key equivalence-class(es) for the i th iteration.
Step 9: Executes the SAT-solver on the SAT-instance after loop termination and extracts K 1 from the returned SATassignment { X, K 1 , Y 1 , K 2 , Y 2 }. Since the while condition in line 3 fails if and only if there is a single equivalence class left, K 1 is guaranteed to be functionally correct, i.e., K c = K 1 . This is a unique property of SAT-attack, which preempts verification. Otherwise even if the attacker finds the correct key, the verification step needs checking outputs for all possible 2 M input patterns, which is computationally infeasible for large circuits.

III. ANALYZING THE IMPACT OF RE-ERRORS
The errors in the circuit RE can cause decryption to return the wrong keys, that is otherwise guaranteed to return the correct ones. This section analyzes the effects of the RE errors by describing the SAT-instance formulation by using a toy example.  SAT-solvers require inputs organized in a special format, called the conjunctive normal form (CNF), such that the expression evaluates to true. Table I shows an example for the CNF formulation of or, and, nand, and xor gates. Figure 1 (a) shows a 2-bit input 1-bit output sample circuit. This Boolean function takes a, b as inputs and computes c = a.b. Figure 1 (b) shows the corresponding locked version with random insertion [1] of 1 xor-type key-gate (shown in red). Note that the correct key in this case is '1'. Equations 1 and 2 show the conversion of the locked circuit to SAT-instances C( X, K 1 , Y 1 ) and C( X, K 2 , Y 2 ) respectively using Table I, where C(.), the portion in black corresponds to the and gate and the portion in red corresponds to the xor key-gate.
Equations 1 and 2 are used to generate F 1 in step 2 of the algorithm. Subsequently, in the first iteration, step 4 of the algorithm returns {a, b, k 1 , k 2 , c 1 , c 2 }={000101}, thus the first DIP is X d 1 ={a, b}=00 and the corresponding oracle response is Y d 1 =0.0=1. Substituting X d 1 and Y d 1 in step 6 yields: .
Using equation 3 in second iteration, the while loop in step 3 fails, because F 2 ∧ (c 1 = c 2 ) is unsatisfiable. Thus, the loop terminates and running the SAT-solver on F 2 (step 9) gives K c =1, which makes the locked circuit's Boolean function (a.b) ⊕ K c =(a.b) ⊕ 1=a.b. Thus, K c is functionally correct, in the absence of RE-errors. The SAT-attack is able to find the correct key with just one DIP for this toy circuit.

A. RE-Error Model
In this paper, we assume only RE-errors for 2-input logic gates. Since the possibilities are xor, xnor, nand, nor, and and or, we consider the possible RE-errors as the possible interpretation errors between the candidate choices within this list. For example, a 2-input nand gate within original netlist could be erroneously reverse-engineered as one of the candidates within the list {nor, xor, xnor, and, or}. If, e.g., it was erroneously reverse-engineered as and, we refer to it as nand → and type RE-error. To cover all possible cases, we also assume that the errors can occur randomly.
Even with RE-errors, the attack can return a functionally correct key. We term them as "RE-errors not improving the security". By contrast, for certain RE-errors (1) the attack can return a functionally incorrect key; or (2) the SAT-instance could be unsatisfiable (the SAT-solver returns UNSAT). We term them as "RE-errors improving the security". Next, we discuss each of these categories in more detail.

B. RE-errors not improving the security
Case 1: Figure 1 (c) shows a locked circuit with and → nand type of RE-error with the faulty gate shown in blue. For this case, all the steps explained in the absence of error remains the same, except that in the last step, the algorithm returns K c =0, which makes the locked circuit Boolean function (a.b) ⊕ K c =(a.b) ⊕ 0=(a.b). Thus, K c is functionally correct and the RE-error is absorbed by the key, thus making the attack successful despite the error. This is an example of REerror that does not improve the security.
C. RE-errors improving the security Case 2: Figure 1 (d) shows a locked circuit with and → or type of RE-error, with the faulty gate shown in blue. In this case, Using equation 4 in the first iteration, step 4 of the algorithm returns {a, b, k 1 , k 2 , c 1 , c 2 }=000101, thus the first DIP is X d 1 ={a, b}=00 and corresponding oracle output is Y d 1 =0.0=1. Substituting X d 1 and Y d 1 in step 6 yields: . Fig. 2. Flow-chart for attack simulation with multiple-errors Using equation 5 in the second iteration, the while loop in step 3 of the algorithm fails, because F 2 ∧ (c 1 = c 2 ) is unsatisfiable. Thus, the loop terminates and running SATsolver on F 2 (step 9) gives K c =1, which makes the locked circuit's Boolean function (a+b)⊕ K c =(a+b)⊕1=a + b =a.b. Thus, K c is functionally incorrect. This is an example of RE-error that improves the security.
Case 3: Figure 1 (e) shows and → xor type of RE-error, with the faulty gate shown in blue. In this case, the SAT-attack returns UNSAT. The while loop in logic decryption algorithm terminates after first iteration because there is no key that satisfies both the original circuit as well as the DIP. This is another example of an RE-error that improves the security, because the attacker is unable to decipher the correct key.

D. The Causes of the Different Cases
The causes for different cases (correct-key, incorrect-key, UN-SAT) for the attack with RE-errors is three-fold: • The DIPs ( X d i ) are generated for the locked circuit, which is erroneous; • The Outputs ( Y i ) are evaluated on the oracle, which provides correct outputs; and • The locked (erroneous) circuit is constrained to satisfy the { X d i , Y d i } pairs. Because of these contradictory constraints, unlike the noerror case, in the erroneous case the algorithm is not guaranteed to return functionally correct key. As a result, in some cases it returns UNSAT and in some cases functionally incorrect key. This motivates us to understand the likelihood of the attack success, in terms of the number of cases in which the attack fails than otherwise, in single as well as multiple error scenarios. We therefore perform extensive experiments to evaluate the attack accuracy for wide range of error scenarios. Figure 2 shows the flow used to simulate SAT-attack. The only difference between conventional flow and this flow is the replacement of perfectly reverse-engineered circuit with erroneous reverse-engineered circuit. If the circuit has L gates, then by definition we are allowed to inject at most L errors. We inject N ≤ L random RE-errors (multiple-error scenario), run the SAT-attack and subsequently perform formal-equivalencechecking if the result is satisfiable). The SAT-attack is recorded as failed for the cases when the result is UNSAT or when satisfiable but the decrypted key makes the locked circuit formally different from the original circuit. Otherwise it is recorded as successful. We run this procedure for K random multiple-error scenarios and record the statistics.

A. Evaluation Strategy for Single and Multiple Errors
To systematically understand the impact of errors on the attack accuracy, we first begin with single reverse-engineering errors. We exhaustively try all gates as candidate choices, since the total simulation time is linear in the circuit size.
Coming to multiple-errors, it is not possible to exhaust all possibilities because given an L-gate circuit, total number of possible multiple-error scenarios (combinations) is Since this function grows exponentially with L, it is not practically feasible to exhaustively evaluate all possible multiple-error scenarios for large industrial-strength circuits. Thus, we evaluate attack accuracy on a subset of random multiple-error scenarios.

B. Evaluation Results
IBM BladeCenter ® High-Performance Cluster (HPC) dualcore nodes with 8GB memory, single-threaded execution and abort limit of 1 week, are used for all the runs. For each value of N (#RE − errors), the experiments took 1 week. We have tried for 8 values of N (2,3,4,5,6,7,8,16), so it took altogether 8 weeks of compute time on the HPC. Table II shows the exhaustive results for single RE-errors for 8 different types of RE-errors based on the error-model described in Section III-A. We define % Attack Success as #insecure cases #secure cases+# insecure cases .  apex2  apex4  i4  i7  i8  i9  seq  k2  ex5  ex1010  dalu  des  c432  c499  c880  c1355  c1908 c3540 c5315   This table shows that the attack success is a function of the type of RE-error. For e.g: for xor → xnor type RE-error, attack success is 100% for most benchmarks, because the only manifestations in those cases were xor-type key gates, which the SAT-solver tolerates by flipping the corresponding key-bit (which is not possible for the remaining 7 types of RE-errors). On the contrary, for nand → nor and and → or types of REerrors, attack success was close to 0% for most benchmarks. For remaining types of RE-errors, the attack success was somewhere in between these two extremes. Figure 3 illustrates the attack success for the different values of N (X-axis) with 25% logic-locking and K = 1000. This plot shows exponential degradation in attack success with linear increase in N . The 25% logic-locking of RISC-V CPU using sle software [33] itself exceeds the abort limit, hence not reported. Figure 4 shows the attack success as a function of %logic locking. Although there is no clear trend, there is a general increase in attack success with increase in key-size. This is counter-intuitive, because we expect the attack success to degrade with increase in the key-size.

C. Evaluating the Error-Removal Attack
Attack failure is registered if the SAT-instance if unsatisfiable or if satisfiable but the decrypted key verified incorrect through functional execution. In either case, the attacker's next step would be to remove RE-errors and reconstruct the original circuit. However, the attacker is unaware of the number/locations/error-scenario, so he is forced to perform brute-force checking. If there are m possible error choices for each gate and k RE errors, the number of possibile locations is L k .(m k ). Coming to the number of errors, k can range from 1 to L. So, total number of possibilities is L k=1 L k .(m k ). We know that L k=1 L k = O(2 L ), hence the complexity of L k=1 m k . L k is either similar or better than this. Thus errorremoval and reconstruction is infeasible for large circuits.

V. CONCLUSIONS
In the logic-locking threat model, the adversary may not be the foundry itself but an end-user purchasing the IC from the open market. This paper analyzes such an end-user adversary, who needs to deal with errors when doing RE of the IC. We quantify the efficacy of SAT-based attack in the presence of RE-errors and identify the underlying reasons as to why it can/cannot succeed. Empirical results suggest dependence of the attack success on the type of RE-error and exponential degradation of attack success with error count. Surprisingly, in most cases the attack success increases with increase in key-size.