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An estimation technique to guide low power resynthesis algorithms

Existing resynthesis procedures used for reducing power consumption in CMOS networks have produced poor results as they select nodes for resynthesis based upon local circuit properties. In this paper, a technique is presented for optimizing the choice of regions used in resynthesis. The cost function which is developed is able to predict the amount of global improvement in power expected through the resynthesis of network nodes under both zero as well as arbitrary delay assumptions. A series of empirical tests have been completed which demonstrate the need for a global approach to the estimation of optimality. The tests results demonstrate that there are often a significant number of nodes which are highly non-optimal in a global sense which would not usually be selected for resynthesis using existing techniques. The estimator predicts these cases with a high degree of accuracy.