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VLSI circuits degradation due to ESD stress below ESD rating voltage

This paper examines low level damage due to ESD stress below ESD rating on one-micron n-well CMOS VLSI circuits and on an NMOSFET. Different VLSI products with different ESD protection circuits were tested using a new method, proposed for latency phenomenon investigation. It is clearly ascertained that ESD stress below ESD rating causes latency damage in VLSI circuits independent of the ESD protection circuit performance. The results obtained on an NMOSFET allow to explain many in-circuits degradations caused by low-level ESD events.