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Design and implementation of a Costas loop down converter in FPGA

This paper presents the the design of a digital down converter (DDC) using a digital Costas loop in a field programmable gate array (FPGA). The designed DDC is one of the modules in the receiver of the base station in a wireless local positioning systems (WLPS). WLPS is capable of localization in the GPS-denied environments such as indoor and underground. The final results and performance measures are quantified and discussed. At the bit error rate (BER) of 10−4 our fixed point implementation of the demodulator using the Costas loop performs only 0.125 dB worst than the theoretical limit.