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AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA Design

With the emerging applications such as AI/ML, exploring the FPGA design space for the optimal performance becomes important and also challenging. The popular tool COFFE was built on an academic architecture and cannot be applied directly to modern FPGA chips with GRM (general routing matrix) architecture. In this work, we present our recently developed fully Automated Transistor-level Efficient and Accurate tool, AutoTEA, which features accurate area and delay models, and a fast solution space exploration method for GRM FPGA circuit optimization. The results show that AutoTEA is able to improve a previously manually optimized design (on the tape-out FPGA chip) by 11%.