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The Nanoscale Silicon Accumulation-Mode MOSFET—A Comprehensive Numerical Study

Recently, we proposed and experimentally demonstrated a very simply structured unipolar accumulation-type field- effect transistor (FET) using silicon nanowires (NWs). In this paper, we present an extensive numerical study of this accumulation metal-oxide-semiconductor FET (AMOSFET). This single-doping-type ohmically contacted structure relies on having a nanoscale dimension normal to the gate, thereby forcing the current path through an accumulated (ON-state) or depleted (OFF-state) region. It also relies on having contact-barrier and doping-dependent minimum source and drain lengths as well as minimum gate lengths to insure unipolar transistor action. The comprehensive report presented extends our previous examination of the device's operation by using extensive numerical simulations to offer a greater understanding of the origins of transistor operation. We explore a wide range of structural and material parameters to study their effects on the linear, saturation, and OFF-state currents. We also delve deeper into the uniquely weak dependence on gate capacitance. This paper establishes that this extremely simple accumulation-mode transistor structure offers its best performance for the more highly doped thinnest devices, giving, for example, for a 1017-cm-3 (doping) and 20-nm device a leakage current of ~40-17 A/mum, a subthreshold swing of 65 mV/dec, and an on-off ratio approximately 1010. This paper also shows that such results should be attainable for AMOSFETs fabricated using NWs and nanoribbons, as well as nanoscale thin-film materials.