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Characterization of the HDP-CVD oxide as interlayer dielectric material for sub-quarter micron CMOS

The characteristics and process optimization of high density plasma (HDP) CVD oxide as a wordline to bitline interlayer dielectric (ILD) material in sub-quarter micron CMOS DRAM were investigated. To enhance the gap-filling capability, multi-step deposition of HDP CVD oxide was developed. A self-aligned contact (SAC) scheme could be used with HDP CVD oxide ILD with wide process margin and low thermal budget as compared to conventional methods such as O/sub 3/-TEOS undoped silicate glass (USG) and borophosphosilicate glass (BPSG) reflow. Better or comparable performance was obtained with HDP CVD oxide compared to BPSG-reflow due to the low thermal budget.