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Evaluation of Area-Oriented Register Cache

Register file is one of the most costly units in recent superscalar processor. In this paper, we evaluate Area-oriented Register Cache which we previously proposed. Conventional register cache aims at reducing access latency and shortening pipeline. Area-oriented Register Cache, on the other hand, aims at reducing area and does not reduce latency. The evaluation shows that Area-oriented Register Cache can reduce number of ports of main register file to 4 without performance penalty and downsize circuit area to roughly 1/9.