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A tunnel FET compact model including non-idealities with verilogy implementation

We present a compact model for Tunnel Field Effect Transistors (TFET), that captures sev- eral non-idealities such as the Trap Assisted Tunneling (TAT) originating from interface traps (Dit), along with Verilog-A implementation. We show that the TAT, together with band edge non-abruptness known as the Urbach tail, sets the lower limit of the sub-threshold swing and the minimum achievable current at a given temperature. Presence of charged trap states also contributes to reduced gate efficiency. We show that we can decouple the contribution of each of these processes and extract the intrinsic sub-threshold swing from a given experimental data. We derive closed form expressions of channel potential, electric field and effective tunnel energy window to accurately capture the essential device physics of TFETs. We test the model against recently published exper- imental data, and simulate simple TFET circuits using the Verilog-A model. The compact model provides a framework for TFET technology projections with improved device metrics such as better electrostatic design, reduced TAT, material with better transport properties etc.


I. INTRODUCTION
Tunnel Field Effect Transistors are promising candidates for low power logic applications [1]. They have the potential to reduce energy dissipation by relying on Band To Band Tunneling (BTBT) for carrier injection, achieve steep turn-ON and thus reduce the supply voltage. Under ideal conditions, device simulations consistently reported switching at sub-thermal rates [2][3][4][5][6][7][8]. Even though the output current from TFET may be low, a sub-thermal sub-threshold swing has the potential to drastically reduce power dissipation and therefore it is attractive for low power applications. Many compact models have been developed in the past to facilitate circuit simulation in Spice [9][10][11][12][13]. However, in most cases the models are tested against results from device simulators instead of experimental devices [9,11,[14][15][16][17][18]. This is likely due to the fact that most experimental results deviate substantially from ideal device simulations and do not produce sub-thermal switching behavior. Therefore there is a clear disconnect between experimental results and compact models and the realistic potential of TFET based circuits is still unknown.
In this paper, we address this disconnect by developing a physics based compact model that 1) fits experimental data, 2) explains the physics of non-idealities with compact expressions and 3) describes circuit performance for different levels of non-idealities and therefore lays a pathway for studying low power circuits based on TFETs. The main reasons of non-ideal switching behavior in TFETs is the existence of interface traps and non-abrupt density of states (Urbach tail) at the band edges. In the past we developed numerical models explaining the impact of trap assisted tunneling (TAT) [19] and how, combined with non-abrupt Urbach tail, it increases the sub-threshold swing of TFETs. In this paper, we present compact expressions of TAT based on Shockley-Read-Hall formalism. We also present simple expressions of channel potential and electric field and explain how they capture the details of TFET device We consider the interface traps between the gate oxide and the channel. Although traps exist throughout the interface, substantial trap assisted tunneling (TAT) takes place only in the region where the electric field is high (source-channel junction). TAT can be of any combination of thermal emission (vertical transition along energy axis) and tunneling (horizontal spatial transition) as shown.
physics such as the TFET quantum capacitance, superlinear output current and current saturation mechanism. We implement the model in Verilog-A and present TFET based inverter and oscillator circuit performance based on existing TFET data. The paper is organized as follows: Section II gives a brief overview of the impacts of TAT and the compact expressions of current from TAT. Section III describes the electrostatic model and Section IV describes the BTBT model that includes the Urbach tail. In Section V, we provide model fits to experimental data. The final Section (VI) describes the circuit simulation results using the compact model in Verilog-A. Fig. 1 shows the device structure of a top-gate TFET and the position of the traps. The trap assisted tunneling is only strong where the electric field is high, in this case the source-channel junction. Below the threshold voltage, V t (when BTBT is triggered), electron excitation by arXiv:1807.00272v1 [cond-mat.mes-hall] 1 Jul 2018 a phonon from the valence band to a trap state followed by tunneling into the conduction band (Fig. 1b) can give rise to leakage current. The problem is to find how much is the leakage floor compared to the BTBT current and how the overall sub-threshold swing is affected. From the SRH formalism, the electron generation rate from a trap to the conduction band can be written as, e n0 = 1 σv th Dit , where σ is the carrier capture cross section, v th is the thermal velocity and D it is the density of traps. Under high electric field, we have substantial band bending and in addition to thermal emission, electrons can partially be excited by phonons and then tunnel into the conduction band via tunneling. The overall process can be quantified by the original transition rate times an enhancement factor due to tunneling. The new rate becomes, e n = e n0 × Γ, where Γ accounts for the tunneling process. At energy E, the emission probability is enhanced since electrons are emitted into a lower energy level (E c ) than they would normally emit to. The emission rate is therefore enhanced to e n0 exp((E c − E)/(k B T )) [20]. Accounting for the transmission probability (T r) through the triangular barrier (from x to x ) and integrating over the energy range ∆E, Γ is calculated as [21], (1) E is the energy to which the electron (or hole) is tunneling to (Fig. 1b). It can be shown,

II. TRAP ASSISTED TUNNELING MODEL
where K n,p = 4 3 √ 2m * n,p ∆E 3 n,p qhE , ∆E n,p defines the range of energy to which the electron (or hole) can tunnel to and from the trap. The subscript (n,p) indicates that the equations are equally applicable to both electron and holes.
Once Γ is calculated, the current can be obtained from the net generation rate following the same method as the conventional SRH formalism, where n i is the intrinsic carrier concentration, n and p are the electron and hole densities. With Γ = 0, Eq. 3 reduces to the conventional SRH formalism.

A. Compact expression of TAT
Eq. 2 involves integration and therefore is not suitable for circuit simulation. Assuming that lifetimes and electric field enhancement factors are the same for electron and hole, and that the channel is depleted of free carriers (n = p = 0) near the source-channel junction where most of the generation takes place, and constant generation rate over a length d gen , we can simplify the above formalism into a compact form as below, The integration over energy is eliminated because only the midgap traps contribute significantly to the TAT. Typical channel electric field in TFETs vary around 1 MV/cm. In this high electric field regime (K < 2/3∆E/k B T ), the Γ expression can be simplified as following, where F is a fitting parameter. Thus Γ depends on the temperature T , electric field E, and the material parameters effective mass (m * ), bandgap (E g ). Fig. 2 shows the comparison of the calculation of Γ from Eqs. 2 and 6 at room temperature, assuming ∆E = 0.4 eV, m * = 0.04m 0 . The compact expression (Eq. 6) shows good agreement with the exact numerical calculation (Eq. 2) above E = 2 × 10 7 V/m with F = 2. However, Γ in Eq. 6 represents an average enhancement factor over the entire generation volume (where the TAT takes place) and thus ∆E loses its direct physical meaning.

III. ELECTROSTATICS MODEL
The TFET surface potential is strongly influenced by the drain voltage since the channel is primarily populated In a TFET the channel is populated only by the injection from the drain. For low drain bias the drain-channel barrier is small therefore the resulting high carrier injection and quantum capacitance pins the electrostatic potential of the channel. At high drain bias, the injection from drain is low and the channel potential changes according to the gate voltage.
FIG. 4. Depending on the magnitude of the quantum capacitance, the channel potential changes with drain bias. The quantum capacitance parameters (φ and ξ) are used to capture the change of ψ with VDS. φ0 is the zero bias surface potential, ξ sets the rate of change of ψ with VDS and ζ changes the smoothness of ψ.
with drain injected carriers. At low drain bias, the carrier injection is high and therefore the channel potential is pinned due to high quantum capacitance. At the high drain bias limit, the injection is low and the potential is controlled primarily by the gate voltage (Fig. 3). We capture the surface potential including these effects with the following empirical compact expression, where φ = φ 0 + ξV DS and φ 0 sets the zero bias (V DS = 0) surface potential. ξ sets the rate of change of surface potential with V DS . We show that this is a powerful expression that can capture the details of TFET transport, such as the transconductance, output resistance, superlinear drain current at low V DS etc. The fitting parameters for the potential are the zero-bias maximum potential φ 0 , the smoothness parameter ζ and the bias control Therefore φ 0 essentially sets the maximum potential that can be achieved in the device at low drain bias (high carrier injection). If the device is initially in p-i-n regime, φ 0 is roughly equal to half of the bandgap. Such drain bias dependence of the channel potential does not originate from any short channel effects and it is intrinsic to TFET. The parameter ξ reflects the control of drain bias on the channel potential. The surface potential saturates roughly at φ 0 plus the drain bias (ξ=1), however, materials with low quantum capacitance will have lower values of ξ. Fig. 4 shows how the channel potential varies with drain bias for different values of the fitting parameters used in ψ. For instance, as the smoothness parameter ζ is increased, ψ changes more slowly and smoothly. For smaller and smaller values of ξ, ψ changes more slowly with the drain bias. Finally, as φ 0 is increased, the initial value (zero bias) of ψ increases. We will later show how these parameters affect the current-voltage characteristics. The electric field in the channel can be expressed as, where E 0 is the initial electric field (at zero gate voltage, set to E g /2λ for an intrinsic channel) and λ is the characteristic scaling length, which is a function of semiconductor and oxide thicknesses. The internal gate voltage is found (V GS,internal = η t V GS ) after accounting for the gate efficiency limited by charged traps, valid for positively charged donor trap states, where f s is the Fermi-Dirac distribution function [22].

IV. BAND TO BAND TUNNELING MODEL
From Kane's model for tunneling [23] where A, B, P are material fitting parameters. V R is the effective bias controlled by both gate and drain biases by V R = F sat E TW /q. F sat (shown below) captures the superlinearity in I DS − V DS and controls V R when V DS is lower than the tunneling energy window, E TW . From the Landauer formalism and using F sat = I DS (V DS )/I DSmax , where µ s is the source Fermi energy, and E vs and E cch are the source valence and channel conduction band edges respectively. The above expression works for both degenerately and non-degenerately doped sources and for all gate voltages. For a non-degenerate source (E vs − µ s < 0), the drain current does not initiate until the Fermi window (µ s − µ d ) is large enough to penetrate the valence band of the source. As a result the output current is non-linear for small drain bias (black curve in Fig. 5). For degenerate source, the Fermi window is already inside the tunnel window (at zero drain bias) and therefore the output current increases linearly. Transport for all such conditions is captured with the above F sat function. However, the denominator, which is a normalizing factor, µ s − E cch in the expression of F sat is valid for above threshold only (V GS > V t ) and therefore for V GS < V t , the above expression of F sat predicts an incorrectly low value. Below V t , the tunnel window is extremely small and therefore F sat should be 1 for all practical purposes. We solve this problem by introducing a function F F which is 1 below threshold and 0 above threshold and take the weighted average as below, where U t is of the order of a few k B T , fitted to get the correct transition. The combined function along with the original F sat is shown in Fig. 6. The tunnel energy window can be found from U 0 is a parameter that defines the sharpness of the band edge (Urbach tail times the geometric gate efficiency). In principle, U 0 should be temperature dependent, however previous studies on Urbach tail reveals weak temperature dependence [24,25]. We use U 0 = K B T 0 /γ t , where T 0 = 300 K, and γ t = γ(T 0 /T ) β , where γ and β are fitting parameters. Before the bands FIG. 7. As the TFET goes from OFF to ON state, the energy tunnel window ETW changes from an exponential function (Urbach-tail-limited) to a linear function at voltages above threshold, Vt.
are overlapped (at V GS = V t ), it can be assumed that the tunnel window increases exponentially, instead of an abrupt turn-ON (at V GS = V t ) at , as a result of the exponentially decaying states above the valence band in the source (for an n-channel TFET). Above V t , the window increases linearly, which is captured by Eq. 15, as expected (Fig. 7). For a material with low quantum capacitance (such as the III-V semiconductors), it is possible to have a tunnel window E TW larger than V DS (Fig.  7). From low to high bias, F sat obtains the correct fraction of the E TW that contributes to current (through V R in Eq. 11). With negative drain bias, the surface potential decreases due to increased quantum capacitance resulting in decrease in the tunnel window and negative differential resistance.
Once we know the TAT and BTBT contributions from Eqs. 5 and 11, we add the two components to find the total current. Figs. 8 and 9 show the impact of some of the fitting parameters on the current-voltage characteristics. Together with ξ, φ 0 controls the super-linearity of the output characteristics and the maximum ON current. The output characteristics is shown in Fig. 8 for different values of φ 0 and ξ. When ξ = 1, a smaller value of φ 0 leads to super-linear output characteristics since ψ changes strongly with drain bias (inset). This is a result of TFETs inherent DIBL and another mechanism, in addition to the the lack of source degeneracy (discussed earlier), that may cause super-linear output characteristics.  8. Impact of the quantum capacitance parameters on the output characteristics. When ψ at low bias is low (low φ0), a high value of ξ makes the surface potential very sensitive to the drain bias. Therefore, it leads to a non-linear output characteristics. For low values of ξ, φ0 changes the surface potential (Eq. 7) and the energy tunnel window (Eq. 15) substantially, leading to the change in ON current.
For materials with high density of states (such as silicon), φ 0 will be lower, resulting in stronger super-linear behavior. The super-linearity can diminish if φ 0 is already high at small drain bias and therefore ψ changes little as bias is increased. The super-linear behavior can also diminish if the value of ξ is sufficiently low (ξ = 0.1 in Fig. 8), regardless of φ 0 . However in this case φ 0 strongly influences the energy tunnel window (Eqs. 7, 15); above V t , E TW,highVDS = ψ highVDS − V t , and therefore change of φ 0 changes the ON current.
Since φ 0 changes the energy tunnel window and the current, the transconductance is also dependent upon this parameter. Fig. 9 shows the transfer characteristics for various φ 0 values and two different drain biases. Higher values of φ 0 lead to higher transconductance and the low drain bias transconductance is always lower than the higher bias. This is because of the higher quantum capacitance at low drain bias and the slow increase of ψ with V GS (Fig. 3). Since the carrier density is a function of temperature, the parameter φ 0 is also temperature dependent. Fig. 10 shows the experimental transfer characteristics along with the model fits for an InGaAs/GaAsSb quantum well vertical TFET [26]. The fitting procedure is summarized as following. The bandgap, effective mass and carrier capture cross-section due to the traps are adopted from the literature for the particular channel material (Table I) Tables I and II. are varied to fit the leakage current of the device at different temperatures. The extracted interface trap density is found to be D it = 3 × 10 11 /cm 2 -eV, which signifies the interface trap density between the GaAsSb source and In-GaAs channel. The interface between the two epitaxially grown structures defect density is lower than the oxide -III-V interface. The intrinsic band steepness parameters (γ, β) are then varied to match the sub-threshold swing at different temperatures. The electrostatic parameters (t semi , ξ, ζ, φ 0 ) are tuned to match the current magnitudes in the ON state and the transconductance. The model parameters to fit the data shown in Fig. 10 are shown in Tables I and II. With the extracted BTBT parameters (γ, β), we extract the intrinsic sub-threshold swing as a function of temperature as shown in Fig. 10c. As discussed earlier, the TAT contribution obscures the intrinsic, steep BTBT as evident from Fig. 10. The intrinsic BTBT is found to be around 50 mV/dec (in the sub-threshold regime, be- In order to make sure the model can simultaneously fit both transfer and output characteristics, we have fitted data at T = 94 K as shown in Fig. 11. The model deviates from the data for this particular device for low V G values due to possible other leakage paths that were not included in the model.

VI. VERILOG-A MODEL AND CIRCUIT SIMULATION
In this section, we demonstrate a Verilog-A implementation of our compact model in Advanced Design System (ADS) circuit simulator.
In Fig.12, we show TFET-based inverters using the N-TFET devices and symmetric P-TFETs. We implement the model described in this work in Verilog-A and calibrate against measured DC-currents shown in Fig.11, along with capacitances. We perform the inverter simulations in ADS. The resulting voltagetransfer-characteristics of the inverter are shown in the figure along with terminal current as a function of input voltage. The simulations show the convergence robustness of the Verilog-A model.
The inverter is used as a building block to simulate a 21-stage ring oscillator (RO) whose output voltage waveforms are shown in Fig.13. TFET shown in Fig. 11, the baseline TFET at T = 300 K, shows oscillation frequency of about 500 MHz at V DS = 1 V. The low frequency (or transit-time) in the baseline TFET is because of low ON-current and high OFF-current (limited by the TAT). Better electrostatic design along with a reduction in D it yields improved SS. Use of channel material that can provide lower bandgap and carrier-effective mass can boost ON-current. The model that incorporates these improvements at the device-level can yield a reduction in transittime and an increase of 30% in oscillation frequency (solid line in Fig. 13). The Verilog-A model developed in this work can thus provide a tool-guide for innovative device FIG. 13. We simulate a 21-stage Ring Oscillator (RO) using the model fitted to the expermental data that is used as baseline and the model whose parameters are projected for improved device performance. The output time-domain waveforms show the oscillation frequency which improves with better device design compared to the baseline. The frequency boost is about 30%. design for desired system performance.

VII. CONCLUSION
We present a compact model with the inclusion of trap assisted tunneling allowing studies of surface trap effects on TFET circuit performance. The model captures the structural and material parameters that influence TAT. We provide compact expressions of channel potential and electric field that accurately capture the TFET quantum capacitance. The model can also be used to extract intrinsic sub-threshold swing from a given experimental data. We implement the model in Verilog-A and present simulation of simple circuits based on TFETs. The model for the first time evaluates the impact of non-idealities on TFET circuit performance.

ACKNOWLEDGMENT
This work was supported by NSF -E3S center, Award 0939514, and the NCN-NEEDS Program, Grant 1227020-EEC, supported by Semiconductor Research Corporation.