{'fraction_non_alphanumeric': 0.046995505742662154, 'fraction_numerical': 0.03617599733673639, 'mean_word_length': 4.136506127101739, 'pattern_counts': {'":': 0, '<': 11, '<?xml version=': 0, '>': 5, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Circuit Structure and Control Method to Reduce Size and Harmonic Distortion of Interleaved Dual Buck Inverter

A new circuit structure and control method for a high power interleaved dual-buck inverter are proposed. The proposed inverter consists of six switches, four diodes and two inductors, uses a dual-buck structure to eliminate zero-cross distortion, and operates in an interleaved mode to reduce the current stress of switch. To reduce the total harmonic distortion at low output power, the inverter is controlled using discontinuous-current-mode control combined with continuous-current-mode control. The experimental inverter had a power-conversion efficiency of 98.5% at output power = 1300 W and 98.3% at output power = 2 kW, when the inverter was operated at an input voltage of 400 VDC, output voltage of 220 VAC/60 Hz, and switching frequency of 20 kHz. The total harmonic distortion was < 0.66%, which demonstrates that the inverter is suitable for high-power dc-ac power conversion.


Introduction
The full-bridge inverter (FBI, Figure 1a) is widely used for dc-ac power conversion because of its simple structure and easy control [1]. An FBI uses sinusoidal modulation of the switching duty to produce an alternating output voltage. The FBI has a shoot-through problem [2], which occurs when the high side and low side switches (S1 and S4, or S3 and S2) are turned on at the same time; this problem can cause serious circuit damage. The shoot-through problem can be solved by inserting a dead-time between the gate pulses of the high and low side switches, but inserting a dead-time changes the effective switching duty ratio and increases zero-cross distortion (ZCD) [3]. The FBI has the other disadvantage of requiring high-rated switches and large output filters [4,5].
Various dual-buck inverters [6][7][8][9][10][11][12][13][14][15] have been proposed to remedy the disadvantages of the FBI. The dual-buck inverters use freewheeling diodes to solve the shoot-through problem but have high output current ripple. The interleaved dual-buck inverter (IDBI) in [9], as shown in Figure 1b, is basically a parallel connection of four buck converters. In this inverter, SU1 and SU2 operate to generate positive sinusoidal voltage, SD1 and SD2 operate to generate negative sinusoidal voltage, and the switching-phase differences between SU1 and SU2 and between SD1 and SD2 are set to 180°. Thus, the current of SU1 is interleaved with that of SU2, and the current of SD1 is interleaved with that of SD2. Using an interleaved mode reduces conduction losses, output current ripple, and current stress in switches and diodes. IDBI requires four inductors, so it is expensive and bulky. When IDBI uses typical sinusoidal pulse width control and operates at a low output power Po, IDBI has much higher total harmonic distortion (THD) of the output current than that of the FBI.
The inverter proposed in this paper ( Figure 2) is a modified IDBI. This inverter inherits the IDBI's advantages but uses two reverse-current-protection diodes DD3 and DU3 to reduce the number of inductors and a new control method to reduce the THD of the output current. The proposed inverter operates in discontinuous conduction mode (DCM) [16] when the output current is below the threshold; otherwise, it operates in continuous conduction mode (CCM). The circuit structure and principle of operation are described in Section 2, experimental results and discussions are given in Section 3, and a conclusion is given in Section 4.

Circuit Structure and Principle of Operation
The proposed inverter ( Figure 2) uses two dual-buck legs (leg 1: SU1, DU1; leg 2: SU2, DU2) to generate Vgrid ≥ 0 V, two dual-buck legs (leg 3: SD1, DD1; leg 4: SD2, DD2) to generate Vgrid < 0 V, two blocking diodes (DU3, DD3) to prevent the current flowing through the body diode of switch during freewheeling mode, and two unfolding switches (SU3, SD3) to determine the polarity of the output current. Legs 1 and 4 are connected to L1, and legs 2 and 3 are connected to L2. Therefore, the proposed inverter requires two inductors, unlike interleaved dual-buck inverters, which have four legs and one inductor per leg. The proposed inverter works with the switching states and leg voltages VAN_on and VAN_off in Table I. Leg switches SU1, SU2, SD1, and SD2 operate at a fixed switching frequency fs = 1/Ts, where Ts is the switching period. The switching duty D is varied to produce a sinusoidal output voltage The simplified gate signals ( Figure 3) for the proposed inverter show that legs 1 and 2 operate for Vgrid > 0 V and legs 3 and 4 operate for Vgrid < 0 V. SU3 turns for Vgrid ≥ 0 V and SD3 turns on for Vgrid < 0 V. To obtain interleaved dual-buck operation, the switching phase differences between SU1 and SU2 and between SD1 and SD2 are set to Ts/2. The difference in switching phases reduces ZCD and prevents shoot-through without inserting dead time between switching pulses (Table 1).  When Vgrid > 0 V, the current iL1 and voltage VL1 waveforms of the inductor L1 ( Figure 4a) consist of three operating modes: Mode 1 during which the input energy is delivered to L1 and the load; Mode 2 during which the stored energy in L1 is delivered to the load; and Mode 3 during which the stored energy in L1 = 0; Mode 3 occurs only when the inverter operates in DCM.
Mode 1 starts at by turning on SU1 (Figure 4b), where the integer n is a switching sequence number. During this mode, the output voltage AN V of leg 1 is in V . The inductor current Mode 2 starts at Mode 3 starts at , when DU1 is turned off ( Figure 4d). This mode is skipped when 1   , i.e., when the inverter is operating in CCM. During this mode, The voltage AN V of node A with respect to node N equals to ) . The switching states (Table I) (3) SU1 operates with a switching duty of D = DSU1.
avg AN V _ can also be expressed as because VAN = Vin in Mode 1, VAN = 0 V in Mode 2, and VAN = Vgrid in Mode 3. Solving for  using (3) and (4) yields is calculated using Equations (1) and (2) as To achieve a power factor of 1, the time average of output current . The inverter has L L L   2 1 and operates in interleaved dual-buck mode, so . When the inverter operates in DCM,  (6), When the inverter is operating in CCM, The DCM interval during which the inverter operates in DCM is calculated using Equations (5), (7), and when Vgrid increases, and when Vgrid decreases. The condition for operating the inverter only in CCM is obtained by setting the argument of arcsine in Equations (9) and (10) less than 0, and is given as and the condition for operating the inverter only in DCM is obtained by setting the argument of arcsine in Equations (9) and (10) greater than 1, and is given as The waveforms iL2 and VL2 of the inductor L2 for Vgrid > 0 V are the same as iL1 and VL1 except that they are delayed by Ts/2.

Design Constraint for L1 and L2
The inverter must operate at for 0 < D < 1/2 and    for 1/2 < D < 1; the highest kHz (this condition corresponds to THD < 3%), the lower bound of L is obtained using Equations (15) and (16) as mH was used in the experimental inverters to minimize the inductor size.

Controller Design
The controller ( Figure 5) was designed using Texas Instrument's TMS320F28335 digital signal processor (DSP). This controller inputs Vgrid, io_avg, and Vin and uses the D-Q axis control method [17] to produce gating signals SU1 − SU3 and SD1 − SD3 that can generate a sinusoidal io_avg. The controller consists of a phase-locked loop (PLL), a D-Q axis controller, and a gate pulse generator. The DSP operates at a clock frequency fclk = 1/Tclk = 150 MHz and the sampling frequency is the same as the switching frequency fs = 1/Ts = 20 kHz. Thus, the sampling sequence number n is in the range of 0 ≤ n ≤ 332 when the grid frequency f = 2 = 60 Hz, and clock sequence number j is in the range of 0 ≤ j ≤ 7499.
can be calculated using Equations (20) and (21). The PLL loop filter for a proportional-integral (PI) control produces This equation is equivalent to in the s-domain, where s is the complex frequency. The final value theory For given I0_d and Io_q, the circuit topology results in the D-Q components of VAN in the synchronous reference frame as and the D-Q components of the switching duty as . Then, the controller generates the D-Q components of the switching duty for CCM operation:  To operate the inverter with a power factor of 1, the reference inputs must be Io_d_ref = Io = 2Po/Vg and Io_q_ref = 0; therefore, Io_d  Io_d_ref = Io and Io_q  Io_q_ref = 0 under steady state. Thus, the inverse D-Q transform produces the switching duty DCCM for CCM operation as that is given in Equation (8).
The duty compensator inputs Vin from the inverter, ˆ and Vg from the PLL, and Io_d_ref from CCM duty-calculator. Then, the compensator uses in Equations (7) and (8) to calculate the steadystate duty difference D between the switching duties for CCM and DCM operations. D is given by The time fraction in Equation (5) This equation shows that the switching duty in Equation (7) for DCM operation is always smaller than the one in Equation (8)

Experimental Results and Discussions
The proposed inverter (Figure 9a, Table 3) was designed to operate at Vin = 400 VDC, Vgrid = 220 VAC/60 Hz and 150 W ≤ Po ≤ 2 kW, and it was fabricated and tested using the calculated circuit parameters. An IDBI [9] (Figure 9b, Table 3) and an FBI [1] (Figure 9c, Table 3) were also fabricated and tested for comparison; the circuit elements for these inverters were the same as those for the proposed inverter. The control circuits for all experimental inverters were implemented using the TMS320F28335 digital signal processor (DSP) from Texas Instruments.  The proposed inverter uses two inductors, whereas the IDBI uses four inductors, and the proposed inverter uses a small inductor core (EER6062), whereas the FBI uses a large inductor core. The fabricated inverters had a circuit volume of 160mm × 250 mm × 43.9 mm for the proposed inverter, 450 mm × 550 mm × 43.9 mm for the IDBI, and 380mm × 550 mm × 78.0 mm for the FBI; the proposed inverter reduced 83.8% of the circuit volume compared with the IDBI, and 89.3% compared with the FBI. The circuit cost was $71.04 for the proposed inverter, $77.74 for the IDBI, and $73.9 for the FBI; the proposed inverter saved 8.62% of the circuit cost compared with the IDBI, and 3.87% compared with FBI.
To verify operation of the proposed inverter, the waveforms of switch-control pulses ( Figure  10a) were measured at Vin = 400 VDC, Vgrid = 220 VAC/60 Hz, Po = 2 kW, and fs = 20 kHz. These waveforms show that the switches operated according to the switching states in Table I; when Vgrid > 0 V, SU1 and SU2 operated in PWM mode, SU3 stayed ON and other switches stayed OFF; when Vgrid < 0 V, SD1 and SD2 operated in PWM mode, SD3 stayed ON and other switches stayed OFF. The inductor currents iL1 and iL2, and the leg voltages VGS_SU1 and VGS_SU2 (Figure 10b) show that the inverter operated in an interleaved mode; the phase differences between iL1 and iL2, and between VGS_SU1 and VGS_SU2 were Ts/2. These switching states produced the sinusoidal leg voltage VAN (Figure 10c). = 99.2% at Po = 500 W when PDSP was excluded.) The FBI does not use the interleaved buck inversion; hence, the switching and conduction losses in the current path were higher in the FBI than in the proposed inverter; as a result, the FBI had the lowest e  among the inverters tested. The IDBI has a circuit structure similar to the proposed inverter and operates in interleaved mode, so e  of the IDBI was very close to that of the proposed inverter. However, the proposed inverter requires two inductors to operate the inverter in interleaved mode, while the IDBI requires four inductors; hence, the proposed inverter can be implemented in a smaller size.    SD3) in the proposed inverter, ~54 °C (SU1, SU2, SD1, SD2) and ~58 °C (SU3, SD3) in the IDBI, and at ~110 °C in FBI. PSW at Po = 2 kW were 13.2 W for proposed, 13.89W for IDBI, and 29.71 W for FBI; therefore, Tsw of the proposed inverter and IDBI was half that of FBI.
THD of o i vs. Po (Figure 14) was also measured at Vin = 400 VDC, Vgrid = 220 VAC/60 Hz, Po = 150 W ~ 2 kW, and fs = 20 kHz. THD at Po = 2 kW was 0.66% for proposed and IDBI and 3.25% for FBI; FBI had the highest THD because this inverter produced a ZCD during the dead-time period. THD at Po = 150 W was 16.6% for IDBI and the proposed inverter when the switching duties for the inverters were controlled using the CCM control (given in (8)). At a low Po, the proposed inverter operated in DCM for some time-interval of sinusoidal Vgrid, as discussed in Section 2.2. This operation produced a distortion in Io when the inverters were operated under CCM control only. When the switching duties for IDBI and the inverters were controlled using the proposed DCM+CCM control (a combination of the CCM control and the DCM control given in Equation (7)), the THD at Po = 150 W was reduced to 4.1% because the combined DCM+CCM control reduced the distortion in Io significantly.
When fs was increased to 40 kHz, THD of io at Po = 2 kW was 0.63% for proposed and IDBI and 7.24% for FBI. The FBI nearly doubled the THD at fs = 40 kHz compared to the value at fs = 20 kHz, because the change increased the effect of dead-time on the switching duty. The THD at Po = 150 W was 7.41% for the proposed inverter using CCM control, 3.98% for the proposed inverter using DCM+CCM control, and 3.51% for FBI. The DCM operating time was reduced at higher fs (Equations (9) and (10)); hence, THD of the proposed inverter decreased as fs increased; a DCM control near the zero crossing point increased iL. In contrast, the THD for FBI increased as fs increased because the impact of dead-time on the switching duty increased.
The waveforms of io and io_avg for the experimental inverters ( Figure 15) were measured at Vin = 400 VDC, Vgrid = 220 VAC/60 Hz, fs = 20 kHz, Po = 150 W, Qo = 0 VAR, and Io = 0.95 A. The cutoff frequency of the low-pass filter for io_avg measurement was 2 kHz (=fs/10). The inverters were controlled using CCM or DCM+CCM control. The waveforms of io show that the proposed inverter had the lowest switching ripple of io, and the waveforms of io_avg show that the DCM+CCM control of the proposed inverter achieved the best sinusoidal waveform. The harmonic components of io ( Figure 16) show that harmonics of io of FBI were slightly higher than those of the proposed inverter because the proposed inverter operated as an interleaved dual buck inverter. The dynamic responses of the proposed inverter ( Figure 17) were measured for a step change of Po from 2 kW to 1 kW and a step change of Po from 1 kW to 2 kW; the operating conditions for this measurement were Vin = 400 VDC, Vgrid = 220 VAC/60 Hz, fs = 20 kHz, and Qo = 0 VAR. For both Po changes, the output current io did not overshoot, and the transient time of io was < 2 ms, which is ~1/8 of the sinusoidal period at 60 Hz. PF, THD, and io of the proposed inverter were measured for Po = 666.6 W, 1.333 kW, and 2 kW at Vin = 400 VDC, Vgrid = 220 VAC/60 Hz, fs = 20 kHz, and line impedance Z = 0.4 + j0.25 Ω. The measured PF was 0.9973 at Po = 666.6 W (33% of the rated power), 0.9985 at Po = 1.333 kW (66% of the rated power), and 0.9992 at Po = 2 kW (100% of the rated power). The measured THD of io was 4.20% at Po = 666.6 W, 3.68% at Po = 1.333 kW, and 3.43% at Po = 2 kW. These results fulfill most grid-connected inverter standards for renewable energy [19][20][21][22]. Comparisons (Table 4) of the circuit parameters and experimental results demonstrate the superiority of the proposed inverter. The proposed inverter has the following advantages: 1) proposed inverter requires two inductors, whereas IDBI requires four inductors; hence, the proposed inverter can be implemented with lower cost and smaller volume than IDBI; 2) it uses interleaved operation, which reduces the current stress of the switch by 1/2 of that in FBI; 3) the number of switching for one period of Vgrid in the proposed inverter is 1/2 of that in FBI; hence, the switching loss is reduced; and 4) e  at o P = 2 kW is as high as 98.3%, compared to 95.0% for FBI. These advantages indicate that the proposed inverter is useful for high-power dc-ac power conversion.

Conclusion
This paper proposes an inverter that can achieve high power conversion efficiency ηe at high output power Po. The inverter uses a dual-buck structure to eliminate zero-cross distortion, operates in an interleaved mode to reduce the current stress of switch, and uses DCM + CCM combined control to reduce the output current distortion at low output power. The size and weight of the circuit are reduced by decreasing the number of inductors and by using blocking diodes; the proposed inverter could reduce 83.8% of the circuit volume compared with IDBI and 89.3% compared with FBI, and it could save 8.62% of the circuit cost compared with IDBI and 3.87% compared with FBI. When the experimental inverter was operated at an input voltage of 400 VDC, an output voltage of 220 VAC/60 Hz, and switching frequency of 20 kHz, ηe was > 94% at 150 W ≤ Po ≤ 2 kW, 98.5% at Po = 1300 W, and 98.3% at Po = 2 kW. The total harmonic distortion was 0.66% at Po = 2kW. The proposed inverter is well-suited for high power dc-ac power conversion.   High-side freewheeling diodes of the proposed inverter and IDBI [9].  Estimation error of ˆ in the phased locked loop (rad).
clk clk T f , Clock frequency (Hz), and period (s) of TMS320F28335 digital signal processor.
s s T f , Switching frequency (Hz) and period (s).     Control coefficients for the phased locked loop.    Low-side high frequency switches of the proposed inverter and IDBI [9].

D S
Low-side unfolding switch of the proposed inverter and IDBI [9]. 2

, U U S S
High-side high frequency switches of the proposed inverter and IDBI [9].

U S
High-side unfolding switch of the proposed inverter and IDBI [9].