{'fraction_non_alphanumeric': 0.01756440281030445, 'fraction_numerical': 0.001756440281030445, 'mean_word_length': 5.400749063670412, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework

Embedded SRAM based memory sub-systems are an integral part of SoCs and have a large area footprint in modern SoCs today. Huge memory requirements are typically met by using an array of SRAM instances and optimal selection of these memory instances becomes imperative for SoC designers. We propose a framework based on the following approach: pre-sort a list of most suitable SRAM instances; create a memory assembly using one of these SRAM instances; calculate total assembly area, power and performance of the resultant sub-system using estimation models; iterate through this process to find out the optimal memory assembly possible that conforms to the user-defined PPA criteria. This automated framework assists SoC designers to select an optimal SRAM instance from the potentially large number of combinations possible through generic memory compilers. Through this paper, we also demonstrate that the optimal memory solution can actually lie in using a combination of distinct memory instances, their characteristics varying on the type of optimization desired. We refer to this approach as approach of heterogeneous memory assemblies. These heterogeneous memory assemblies can potentially achieve even better performance than what can be achieved by homogeneity, whatever be the scope of optimization, viz. area, dynamic power or leakage optimization. Through our advanced memory sub-system exploration framework (MSSEF), we demonstrate that for a 4 M-bit memory requirement, we can achieve area savings up to 11 % by using a combination of heterogeneous memory instances instead of homogeneous assemblies.