{'fraction_non_alphanumeric': 0.033566433566433566, 'fraction_numerical': 0.023076923076923078, 'mean_word_length': 4.6117647058823525, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A High-Resolution and Low Offset Delta-Sigma Analog to Digital Converter for Detecting Photoplethysmography Signal


 A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.