{'fraction_non_alphanumeric': 0.026785714285714284, 'fraction_numerical': 0.017857142857142856, 'mean_word_length': 4.95575221238938, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Background calibration algorithm for 3-stage pipelined-SAR ADCs

This paper presents a digital background calibration algorithm for the inter-stage gain error of the pipelined-SAR ADC. The background calibration estimates dynamic inter-stage gain variation by an update equation based on LMS algorithm. Gain errors are then corrected by the reconstruction logic. In addition, the residue saturation in pipeline ADC has been analyzed and solved. Simulation results are presented for a 13b 3-stage pipelined-SAR ADC. Without calibration, ADC's dynamic performance SNDR is 46dB and SFDR is 58dB. After the calibration, SNDR is increased to 70dB and SFDR is increased to 77dB.