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VLSI Implementation of Area and Power Efficient Digital Control Circuit for HF RFID Tag Chip

A fully integrated area efficient digital control circuit based on the ISO/IEC 15693 protocol is proposed for high frequency RFID tag chip. The proposed circuit is mainly composed of pulse position modulation decoder, Manchester encoder, anticonllision, low power circuit and other control logic. It supports six different data rates, namely, low or high data rate with one subcarrier (6.62 or 26.48 Kbit/s), low or high data rate with two subcarriers (6.67 or 26.69 Kbit/s), fast data rate with one subcarrier (13.24 or 52.97 Kbit/s). The proposed digital control circuit was integrated in an RFID tag IC and was fabricated using a 0.18-µm 2P6M CMOS process with an area of 306µm by 326µm which is smaller than the existing designs. Besides of small area, the circuit has an advantage of low power with a power consumption of less than 50µW.