{'fraction_non_alphanumeric': 0.04698972099853157, 'fraction_numerical': 0.048458149779735685, 'mean_word_length': 4.206106870229007, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A High-Efficiency D-Band Frequency Doubler in 22-nm FDSOI CMOS

This paper presents a high-efficiency D-band push-push frequency doubler implemented in 22-nm FDSOI CMOS technology. A 2nd harmonic load-pull approach is followed, and a maximum output power of 4.1 dBm is achieved at 135 GHz while the circuit consumes only 24.7 mW from a 800 mV supply. The conversion gain peaks at -3.8 dB with a 3-dB bandwidth of 125–145 GHz (14.9%). The measured peak DC-to-RF efficiency and total efficiency values are 11.8 % and 9.1% respectively, which presents to the authors' best knowledge a leading-edge performance among the reported active CMOS frequency doublers at this frequency range.