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VLSI implementation of Ogg Vorbis decoder for embedded applications

In this paper, a novel VLSI architecture of an Ogg Vorbis decoder is proposed, dedicated for embedded applications. Aimed at the use of the decoder in portable audio appliances, first, the computational cost in a series of decoding processes is analyzed. As a result, the LSP (line spectrum pair) process is detected as a bottleneck to achieving realtime decoding by an embedded processor. Thus, the proposed architecture devises a specific hardware LSP module so as to be integrated into a single chip together with an ARM7TDMI processor. Moreover, our decoder employs fixed point arithmetic, rather than floating point arithmetic, by optimizing the calculation accuracy according to audio quality distortion analysis. The proposed LSP module has been implemented with 9,740 gates, and operates at 58.8 MHz, with the total CPU load reduced by 57%. Audio quality assessment indicated that the use of the fixed point arithmetic does not incur any significant sound distortion.