{'fraction_non_alphanumeric': 0.01490757304710793, 'fraction_numerical': 0.0035778175313059034, 'mean_word_length': 5.101818181818182, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A High Speed Vision System for Robots Using FPGA Technology

High speed image and video processing is becoming increasingly important in many applications, especially in robotics. A high speed vision system involves grabbing image frames from a single or multiple sensors and processing of the data in a limited time. Therefore, the requirement of real-time processing of the images is the key problem in dealing with such applications. Moreover, to obtain the best performance, it is vital that algorithms and hardware of a vision system be reconfigurable and flexible. A FPGA-based system was devoted to the design of vision system for robots. It offers the required features for robots' vision system such as; parallel processing of the video images, good computational power, low cost and reconfigurable hardware. The image processing component of the proposed vision system consists of one core processor for implementing the software part and up to eight functional units for the hardware implementation part. The core processor controls and communicates with the functional units. The mixed hardware/software method utilises the advantages of both hardware and software techniques. The implementation of a normal filter with a coefficient matrix of 3 times 3 as applied to a 64 times 64 image is chosen as an example. It can be verified that the multiplication operations for implementing such filter are independent and therefore can be run simultaneously. The addition operations can be done when the multiplication results are available. Therefore, the core processor can perform all parallel operations in order to minimise the total number of implementation stages.