{'fraction_non_alphanumeric': 0.019801980198019802, 'fraction_numerical': 0.011315417256011316, 'mean_word_length': 5.616822429906542, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
An on-chip delay measurements module for nanostructures characterization

Exploring nanoelectronic devices requires extensive physical testing of several new materials to determine their electronic characteristics as stated by P.J. Burke (2003). In particular, circuit designers need to characterize delays introduced by nanostructures. This paper proposes on-chip frequency measurement units (MU) designed for measuring delays across nanoelectronic devices. Extensive calculations and simulations show that the structure presented in this paper can measure delays as small as 7 picoseconds. The MU is part of a test platform for nanostructures designed in 180 nm TSMC CMOS that is currently in fabrication.