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Design for ESD protection at its limits

While CMOS downscaling approaches its limits, ESD protection design is facing significant challenges. Technology measures which facilitate further technology scaling enhance the sensitivity of the devices against ESD stress. At the same time demanding performance requirements more and more limit the options of circuit solutions for ESD protection. In consequence ESD qualification goals for ICs had to be reviewed and adjusted. However, the need of ESD robust systems cannot be compromised. To balance and match IC level protection and PCB protection measures the concept of system efficient ESD design (SEED) has recently been introduced.