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Current skimming-based CMOS readout architectures for Quantum Well Infrared Photodetectors

Cost-effective high-performance IR imaging cameras based on Quantum Well Infrared Photodetectors (QWIP) need CMOS readout structures which allow effective operation at temperatures compatible with inexpensive long-life coolers. At such high temperatures (around 72 K), the QWIP suffers from large background and dark currents (Fig. 1), which have a tendency to saturate the integrating capacitor in the readout cell. The present research focuses on evaluating per-pixel current suppression (skimming) concepts, in order to make possible the use of small integration capacitors and avoid their saturation, thereby increasing the dynamic range (Fig. 2) and signal-to-noise ratio of the detector-readout assembly. Such circuits enable per-pixel Adaptive SensitivityTM operation to further enhance the dynamic range. The approach investigated in this paper is based on externally controlled partial current skimming (Fig. 3). This scheme consists of a conventional Direct Injection (DI) structure with an additional skimming transistor (M2) incorporated in each pixel. The input transistor (M1) ensures high injection efficiency and isolates the detector from the integrating node (A). Both skimming and input transistors are operating in subthreshold. An external voltage (adjust) determines the amount of drain current flowing through M3 and subtracted from the total input current. By adjusting the skimming current to a value close to the sum of background and dark currents, the resulting signal can be reduced close to the interesting ac component (Fig. 2). This technique has the advantage of simplicity and it can be easily incorporated in a small area pixel (Fig. 5). Because the integration current is reduced significantly, Cint can be decreased without saturating it. In the framework of this research, two readout techniques were analyzed and compared: a voltage-readout structure employing a source-follower output stage for driving a per-column sample-and-hold block (Fig. 3) and a current-readout configuration with an output selection transistor interfacing with a per-column integrator stage (Fig. 4). The following points have been observed: 1. Design complexity: For the current-readout approach, the reset operation is “builtin” the readout process thus no reset switch is necessary; also, the output stage comprises only a single transistor while the voltage readout implies an additional transistor. These two observations translate into about 10% lower pixel area for the current-readout structure.