{'fraction_non_alphanumeric': 0.023047375160051217, 'fraction_numerical': 0.008962868117797696, 'mean_word_length': 5.409836065573771, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Paralleled SiC MOSFET Half-bridge Unit With Distributed Arrangement of DC Capacitors

Discrete silicon carbide (SiC) MOSFETs are often connected in parallel to reach high current capabilities. However, the unequal switching losses and transient current overshoots can limit the maximum switching frequency and current capability of the paralleled unit. In this paper, a paralleled half-bridge unit with the distributed arrangement of dc capacitors and the auxiliary gate-source connections is presented. The layout mismatches are analyzed and optimized by the AnsysEM simulation techniques. Compared to the traditional paralleled unit, the differences in the transient current overshoots for the low-side paralleled SiC MOSFETs are decreased significantly from 14.37 % to 2.78 %.