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An iterative heuristic for state justification in sequential Automatic Test Pattern Generation

State justification is one of the most time-consuming tasks in sequential Automatic Test Pattern Generation (ATPG). For states that are difficult to justify, deterministic algorithms take significant CPU time without much success most of the time. In this work, we adopt a hybrid approach for state justification. A new method based on Genetic Algorithms is proposed, in which we engineer state justification sequences vector by-vector. The proposed method is compared with previous GA-based approaches. Significant improvements have been obtained for ISCAS benchmark circuits in terms of state coverage and CPU time.