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Layout Extraction of 3D Models for Interconnect and Substrate Parasitics

In modern VLSI design it is of vital importance to know the influence of parasitics on the behaviour of the circuit. The most important parasitics are the interconnect resistances, the interconnect (ground and coupling) capacitances and substrate cross-talk. In this paper we present new methods to model these parasitics directly from the layout of a circuit. All methods are implemented in a layout-to-circuit extractor, Space. Space scans the IC layout and during this process a netlist of the circuit is produced. This netlist can be simulated with a circuit simulator, after appropriate stimuli have been added. Thus it can be decided whether the design specifications are met or not. The layout-to-circuit extractor, Space, is suitable for MOS, bipolar and BiCMOS processes. It is capable of recognizing all common active and passive devices. Furthermore it encorporates several methods to model parasitic effects, including substrate cross-talk, both in a heuristic and a fundamental approach. In this paper we only discuss the fundamental, physics-based methods to obtain 3D models of the interconnect parasitics and the substrate cross-talk. Basically we use principles from numerical methods and network theory to obtain a reduced, accurate electrical network describing the parasitics. After the introduction of the methods, we illustrate the use of the proposed methods on practical examples for device characterization and detailed circuit verification. We show that a good agreement with measurements is obtained.