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Development of Wafer Level Process for the Fabrication of Advanced Capacitive Fingerprint Sensors Using Embedded Silicon Fan-Out (eSiFO(R)) Technology

Typical wafer level chip scale package (WLCSP) is a standard fan-in structure. As the increase of I/O numbers, it can’t provide enough area to redistribution layer (RDL). In recent years, an emerging technology of an embedded package with a fan-out area around the chip has been developed showing many advantages of higher I/O numbers, low cost, integration flexibilities and small form factor. Usually fan-out wafer level package (FOWLP) uses epoxy mold compound (EMC) materials, which faces lots of technical challenges such as warpage, CTE mismatch between each layer, expensive cost. In this paper, a completely new wafer level embedded silicon fan-out, named eSiFO® technology was reported to accomplish a capacitive finger print sensor packaging. In this innovative integrated device, an ASIC die with size of ~6mm2 was thinned to 90um and then embedded into the silicon cavity to reconstruct a new wafer. In the whole processes, the warpage was less than 2 mm although more than 80% package area was covered by metal. For the wafer level process, ten masks were used and a yield of 98% was achieved. The device passed standard reliability test, including Pre-Con, TCT, uHAST and HTST.