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Analysis of read disturbance mechanism in retention of sub-20 nm NAND flash memory

We observed an increase of Vth by read disturbance mechanism at programmed threshold voltage state (PV1) and erase state (ERS) states in retention characteristics of sub-20 nm NAND flash main-chip. We also confirmed that the charge gain behavior by read disturbance has dependency on the number of read and cycling operations. As a result, we quantitatively modeled read disturbance mechanism by the amount of final ΔVth and deterioration coefficient α which is related to the number of read operation times. It was also observed that those parameters increase with increasing cycling times and have larger value at ERS state than that at PV1 state.