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A Complement to Enhanced Instruction Register File against Embedded Software Falsification

Instruction set randomization (ISR), which modifies or enhances instruction coding of processors, is one of the cost-effective techniques to obfuscate embedded software. Using an Instruction Register File (IRF) for ISR was proposed and explored, while the existing technique lacked a protection against falsification of software. This study presents a complementary table to the IRF named Instruction Rejection Register File (IRRF). It forces the processors to use some of the enhanced instruction codes given by the IRF, which are incomprehensible to attackers, rather than their original codes. According to our evaluation, a 512-entry IRRF covered up to 52.5% of the execution and its cost was additional 1.7% of logic and three RAM elements with 15% performance overhead.