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On-Line Single Event Upset Detection and Correction in Field Programmable Gate Array Configuration Memories

Larger field programmable gate array (FPGA) configuration memories and shrinking design rules have raised concerns about single event upsets (SEUs), especially for highreliability, high-availability systems that use FPGAs. We present a design for the on-line detection and correction of SEUs in the configuration memory of Xilinx Virtex-4 and Virtex-5 FPGAs. The design corrects all single-bit errors and detects all double-bit errors in the configuration memory at maximum speed and with minimal overhead and power dissipation. A method for SEU emulation in the configuration memory of FPGAs is presented which enables the experimental verification of the approach. The results of SEU emulation in Xilinx FPGAs are discussed. 1