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Research on Real-time Implementation of Spaceborn Viterbi Decoder

In order to meet requirements of BER of satellite-to-ground and satellite-to-satellite communication in space TT&C communication system, this paper investigates the FPGA real-time implementation technology of space-borne Viterbi decoder algorithm. A novel method based on dual-port RAM is proposed as the survivor path management solution. Besides, a series of methods, such as path-cutting, parallelized Adding-Comparison-Selection computing and soft-decision, are adopted to further improve the performance of Viterbi decoding. Compared to the conventional decoder, the Viterbi decoder based on XC2V6000-4 FPGA has advantages of short delay, good real-time performance and low hardware complexity with the speed of maximum output data rate to 116Mbps.