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Dynamic Low-Density Parity Check Codes for Fault-tolerant Nanoscale Memory

New bottom-up techniques can build silicon nanowires (dimension < 10 nm) that exhibit remarkable electronic properties, but with current assembly techniques yield very high defect and fault rates. Nanodevices built using these nanowires have static errors that can be addressed at fabrication time by testing and reconfiguration, but soft errors are problematic, with arrival rates expected to vary over the lifetime of a part. In this paper, we propose using a special variant of low-density parity codes (LDPCs) — Euclidean Geometry LDPC (EG-LDPC) codes — to enable dynamic changes in level of fault tolerance. Apart from high error correcting ability and sparsity, a special property of EG-LDPC codes enables us to dynamically adjust the error correcting capacity for improved system performance (e.g., lower power consumption) during periods of expected low fault arrival rate. We present a system architecture for nanomemory based on nanoPLA building blocks using EG-LDPCs, and an analysis of its fault detection and correction capabilities.