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Verification of the PalmDSPCore Using Pseudo Random Techniques

The advanced variable size scalable architecture has many features that present significant verification challenges to ensure correct implementation. This paper describes a functional verification system and methodology to address the requirements of correct verification of the PalmDSPCore. In particular, the paper presents an efficient tool and methodology to generate random assembly tests, in accordance with the dynamic change of the processor’s states. It describes both random and pseudo-random scenarios and describes how to feedback this process to be sure that the Device Under Test (DUT) was adequately tested.