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Combined-Hardware-in-the-Loop system and its test-bench verification

Hardware in the Loop (HiL) supports development processes in many types of applications. Power electronic systems with switching frequencies up to several kilo hertz constitute some of the most demanding applications for the quantization time of the HiL. The non-avoidable delay forces very short calculation periods which lead to high effort in hardware and software implementation. For PWM based controllers it is possible to synchronize the HiL model to the control cycle and the PWM and so reduce the simulation effort to one calculation per control cycle. Simultaneously the usually unavoidable delay of the HiL calculation time is eliminated by implementing a special digital interface between control system and HIL system. Because of this interface the pulse patterns themselves are not needed by the HiL. Additional precise pulse pattern verification becomes viable. The concept is realized on a FPGA-ARM-SoC control platform and verified against measurement results from a physical test bench.