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Joint scheduling and allocation for low power

In this paper, we propose a joint scheduling and allocation scheme for synthesizing low power VLSI architecture from behavioral descriptions. Sibling operations are defined and hardware sharing between them is enabled during the integrated scheduling and allocation phase. Combined with data movement minimization in register allocation and idle cycle enforcement in controller synthesis, VLSI architecture with low power consumption is achieved. The framework of a behavioral synthesis program implementing these techniques has been described and estimation of power saving factor is given.