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Virtual Power Management simulation framework for computer systems

We developed a Virtual Power Management (VPM) simulation methodology for pre-silicon design and validation of power management hardware and firmware. VPM integrates a realistic hardware interface with high-level workload and power models to achieve fast and effective system-wide simulation. VPM models are used independently for algorithmic and architectural exploration, and in conjunction with the Simics simulation environment to execute real firmware for verification. In this paper, we present an overview of the VPM architecture and results from two studies using the simulation framework.