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Efficient event-driven approach using synchrony processing for hardware spiking neural networks

Current digital hardware implementations of spiking neural networks usually focus on a time-driven architecture to process the large number of events that occur during a typical simulation. While this type of implementation is practical for simulating biologically accurate neurons, most systems using a simpler neuron model can benefit from an event-driven architecture. In such cases, significant performance improvements are theoretically possible. In practice, however, such implementations do not maximize the available computational power because finding the next event often involves serializing computations. In this paper, a hardware architecture that offers the efficiency of an event-driven algorithm while allowing parallel computations is developed. The architecture uses multiple pipelined processing elements to compute spikes in parallel and a novel comparator tree structure to find the next event in a large network efficiently. The resulting system can implement up to 131 072 neurons on a single FPGA (Xilinx Virtex-6 XC6VLX240T) and processes approximately 70 million spikes per second when using a 4-bank architecture clocked at 100 MHz.