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Implementing a Functional / Timing Partitioned Microprocessor Simulator with an FPGA

When creating a microarchitectural simulator, one desires three things: confidence in correctness, speed of design, and speed of simulation. The first requirement is necessary for accurate experimentation. The second impacts the architect’s ability to perform microarchitectural exploration by rapidly describing a range of systems. The third affects the number of simulations that can be profitably run for a particular systems, and thus the statistical confidence in our evaluation results. One approach is to divide the simulator into two partitions: a functional partition and a timing partition. The functional partition is essentially a pipelined abstract execution engine, which allows dataflow-valid executions through an idealized pipeline. The timing partition, on the other hand, is responsible for modeling microarchitectural details such as operation timing and branch predictor accuracy. The timing partition is responsible for directing when instructions should be executed, but does not need to concern itself how. ASim is a software simulator which makes use of this partitioned organization [6]. ASim’s functional partition is an infinitely-renamed, infinitely-buffered pipeline. The functional partition does not perform instructions immediately upon fetch (the ”execute-on-fetch” simulator model) but progresses the instruction through various pipeline stages (Decode, Execute, Commit, etc) upon direction from the timing partition. This multi-staged approach allows the simulator to model processors which are superscalar, speculative, or out-of-order, solely by altering the timing partition. This split organization increases confidence in simulator correctness, as verification effort is focused on the functional partition. Similarly it reduces implementation effort, as the functional partition can be reused across multiple timingpartition implementations. However this approach incurs a communication overhead which can degrade simulation performance. Since the timing model and the functional model move in lockstep, opportunities for parallelism in a software simulator are limited [2]. One approach as in the FAST simulator [4] is to decouple the partitions as much as possible, thus minimizing communication overhead and increasing opportunities for parallelisation. In this paper we present HASim (pronounced HAY-sim), an alternative approach to this problem. In HASim the timing and functional partitions are tightly coupled, and are jointly implemented in hardware, rather than software. The intent is to place the resulting design onto an FPGA, thus allowing us to improve overall simulator performance. We will use this project to explore optimizing the sequential lock-step movement of a partitioned simulator into an optimized parallel hardware structure. Currently HASim implements a toy ISA as a proof-ofconcept. In the future we hope to expand the framework to realistic ISAs and architectures.