{'fraction_non_alphanumeric': 0.0265748031496063, 'fraction_numerical': 0.024606299212598427, 'mean_word_length': 4.878612716763006, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
FPGA implementation of an optimized 8-bit AES architecture: A masked S-Box and pipelined approach

In this paper, we present a new pipelined 8-bit architecture for Advanced Encryption Standard (AES) encryption. The new architecture supports encryption with 128-bit keys with 10 rounds of Byte Substitution, Shift Rows, Mix Columns and Add Round Key operations. We emphasized on optimizing a single round by using an 8-bit architecture instead of 128-bit architecture which resulted into overall optimization and increase in bit security of the system. We have also proposed a new architecture for Key Expansion Unit and S-Box (Substitution Box) using a more secure key expansion algorithm and high order masking respectively, hence making the overall architecture of AES more secure and less prone to Differential Power Analysis (DPA) attacks. The proposed architecture was implemented on Virtex-7 working at a maximum clock frequency of 191.42 MHz with a throughput of 94.24 Mbps and a power consumption of 0.694 W.