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Energy-efficient hardware/software co-synthesis for a class of applications on reconfigurable SoCs

There are many different ways that an application is executed on a Reconfigurable System-on-a-Chip (RSoC). They can significantly impact the overall system energy dissipation. In this paper, we propose a three-step design process for application synthesis using RSoCs. We develop (a) a performance model to abstract a general class of RSoC architectures for application development, (b) a mathematical formulation of the energy-efficient synthesis problem for a class of applications and (c) a dynamic programming algorithm that minimises the system energy dissipation. Using the proposed design process, reduction in energy dissipation ranging from 41% to 54% is observed in our experiments.