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A practical logic BIST for ASIC designs

Increasing number of pins or gates in the latest LSIs requires a lot of testing resources. The conventional scan-based testing requires a costly tester (ATE) equipped with a lot of pin electronics. Since reducing the testing cost is a crucial issue in industry, we have introduced an approach using scan-based logic BIST to solve this problem. The logic BIST has been applied to many ASIC design chips, which have up to several million gates.