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Design and Implementation of MP3 Player Based on FPGA

The paper adopts a method of a low speed processer and FPGA based hardware accelerator SOC units to develop the MP3 player, added with some peripheral devices. The experimental results show that the system has implemented the basic functions of the MP3 player, having its own advantage on increasing the decoding speed and reducing the system consumption. The system is convenient to redesign for more function in the future because its designed based on FPGA. In conclusion, it has a wide application prospect.