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A Unified Page Walk Buffer and Page Walk Cache

GPU enables shared virtual memory (SVM) to eliminate complex data transfer in GPU programming for programmers. However, SVM bring the expensive overhead of address translation due to the large number of address translation requests which are generated simultaneously in the GPU. GPU Memory Management Unit (MMU) is designed to handle the address translation. However, the page walk buffer (PWB) and page walk cache (PWC) have lots of redundant information and have limited improvement for address translation performance. To address these problems, we propose a unified PWB and PWC. Unified PWB and PWC abandon the traditional linear table structure and adopt tree structure to eliminate the redundant information. Additionally, unified PWB and PWC adopt similar structure to enable PWB and PWC can interplay with each other. We evaluate the unified PWB and PWC in simulation with real-world benchmarks. Results show that our scheme can improve the 42.6% performance of address translation restricted GPU applications with a 30.2% less space overhead.