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CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in Multicore

Voltage scaling to reduce power consumption for ensuring longer battery life expedites SRAM cell failures due to process variations. Cache, holding significant chip area, encounters these cell failures exponentially with voltage reduction. Several voltage reduction techniques have been proposed by tolerating faults at the cost of sacrificial cache portions affecting effective cache capacity. On this outset, this work attempts to minimize power below threshold by handling faults without affecting effective cache capacity. Words under priority blocks addressed on faulty cache portions are remapped in non-functional blocks to avoid cache pollution. Blocks are prioritized considering their coherence states and reusability. Non-reusable clean copies are invalidated to ensure adequate space for remapping and maintaining effective cache capacity. This work achieves minimum Vdd 325 mV with 7.77% area overhead with 6.7% leakage power and 0.5% dynamic power overhead in 90nm processor.