{'fraction_non_alphanumeric': 0.018528321863419798, 'fraction_numerical': 0.0021175224986765486, 'mean_word_length': 5.494845360824742, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Novel Spacer Process for Sub-10-nm-Thick Vertical MOS and Its Integration With Planar MOS Device

We demonstrate vertical capacitors using a novel spacer process capable of fin thickness down to 5 nm. We also integrate this process compatibly with planar devices on the same die using minimal additional mask steps. Various implant conditions, order of implant step, and starting substrate dopings are studied and best conditions identified through TSUPREM4 simulations and later through experiments to ensure process robustness and dopant tunability for the vertical devices as well as to ensure comparable performance for planar and vertical devices. In anticipation of usage of this process in a high-density environment, the impact of isolation density on the leakage characteristics of vertical capacitors is also studied. After simultaneously fabricating planar and vertical structures, electrical characterization using capacitance-voltage (C-V) and current-voltage (I-V) measurements is performed. Functional capacitors for both types of devices are obtained. Oxide thickness is backtracked using I-V, C-V, and TEM and yield consistent results. The leakage current shows expected trends with voltage and is successfully fitted using prevalent tunneling models. The vertical structures are found to suffer from two problems: a larger leakage current and an additional planar parasitic capacitance due to a finite polysilicon gate thickness. The larger leakage is attributed to thin corners as confirmed by higher leakage in structures having a larger fraction of corner area (higher isolation density structures). A modified novel vertical device process circumventing both these problems by yielding thicker bottom and corner oxides is proposed and experimentally demonstrated. Finally, a path to extending this process for vertical transistor fabrication is shown in simulations