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A generic reconfigurable array specification and programming environment (GRASPER)

Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays (FPAAs). With the component density of these devices, small analog circuits as well as larger analog systems can be synthesized and tested in a shorter time and at a lower cost compared to the full design cycle. However, automated development platforms and CAD tools for these devices are far fewer than the physical synthesis tools for their digital counterparts. One of the major reasons for this is the considerably higher impact of interconnect parasitics on circuit functionality in the analog domain; therefore, performance metrics must be monitored closely. Our goal in this paper is to present a physical synthesis framework with a generic architecture specification interface and a parasitic extractor for verification of the synthesis results. Our synthesis tool can support a wide range of FPAA architectures and our simulations can successfully predict the performance metrics.