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Custom Precision Method of Floating-Point Operations of FFT Processing for Optimized Area and Delay Performance

The design of a system that involves hardware implementation of signal processing algorithms poses various challenges. One such challenge is delay optimization. Typical signal processing involves various transforms for subsequent analysis in floating point representation. Fast Fourier Transform (FFT) is one of the basic transformers used for signal analysis. Hardware implementation of transforms or algorithms has been essential for the design of smart or autonomous systems. In this work, an approach of custom precision of 12 - bit has been proposed for the FFT implementation for hardware design. From the simulation results, it was observed that the proposed method has been efficient in terms of reduced delay and area for the given set of inputs. Verilog code has been considered for simulation and the obtained results were verified theoretically using Matlab. Design synthesis for delay and area has been carried out using Xilinx ISE. The proposed method has been successfully verified for better results of reduced delay of 8.191ns with the reduced number of LUTs of 3149.