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Design & Implementation of Low Power 4-Bit Full Adder Using XNOR Logic by Gate Diffusion Input ( GDI ) Technique with Header and Footer Sleep Transistors

The basis of numerous operations such as counting, multiplication, filtering are done with the full adder. Adders are heart of computational circuits and many compound arithmetic circuits on the basis of addition. The vast uses of this operation in arithmetic functions attract a lot of researcher’s attention for mobile applications. Nowadays, various adder implementations are available in order to realize the speed or density requirements in which adder’s optimization is paramount factor. This paper describes GDI based XNOR logic 4-bit full adder. It uses added logic in the design which results area overhead but since our concern is power so we have to compromise upon the area. This 4-Bit Full adder will be analysed with incursion of both header and footer switches. The proposed technique uses extra transistor logic (a P-type and an N-type) within the gate, in which the gate terminal of each Leakage Control Transistor is controlled by the source of the other. The proposed circuit offers less average power and time delay. Simulations have been carried out by Tanner EDA tool.