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Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDX

An optimized calibration methodology for high-speed comparators is proposed. The key features of this methodology are the offset extraction technique and the body-biasing calibration. The offset extraction technique uses a fast and accurate smart resettable successive approximation register (SR-SAR) algorithm to calculate the offset voltage (Vos). The body-biasing calibration is a simple iterative loop, where the body bias of the comparator's differential input pair is monotonically increased or decreased to counter balance the extracted offset voltage at each iteration. A study case using a strong ARM comparator implemented in 22nm FDX technology achieves a σVOSreduction by a factor of 12. The simulation time is reduced by a factor of 64 compared to the traditional linear approach showing the advantage of this methodology.