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Design of two Low DC-Power High-Efficiency D-Band Power Amplifiers in 22 nm FDSOI

This paper presents two low DC-power D-band power amplifiers (PAs) integrated into a 22 nm fully-depleted silicon-on-insulator (FDSOI) technology. Both amplifiers use the capacitive neutralization technique for gain-boosting and stability enhancement. The design procedure for transformer-based (TB) and line-based (LB) matching networks and the advantages and disadvantages of both architectures are discussed. The PA implementation focuses on low DC-power consumption, high efficiency, and compact device realization. The fabricated TB-and LB-PA show high maximum power-added-efficiency (PAE) of 9 and 8 % consuming 46 and 52mW respectively at a supply voltage of only 0.8 V. The saturated output powers Psat reach 6.8 dBm and 6.5 dBm while achieving small-signal gains of 24.2 and 23.4 dB with 3-dB-bandwidths of 23 and 26 GHz.