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A 0.18 pJ/Conversion Step Hybrid Structure based ADC

This paper presents the hybrid design of 8 bit ADC incorporating binary search ADC for area saving and flash ADC for higher speed operation. This ADC architecture is divided into two stages: the first stage is designed using binary search topology while the second stage is designed using flash architecture. The binary search stage is set to generate only 6 bits and flash stage is set to generate remaining 2 bits. With this hybrid configuration, the ADC consumes 12.8mW of power and sampling rate of 533 MSPS when operated at 1.8V.