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Variations in Nanometer CMOS Flip-Flops: Part II—Energy Variability and Impact of Other Sources of Variations

In this paper, the impact of variations on single-edge triggered flip-flops (FFs) is evaluated for a wide range of topologies. In particular, this Part II explicitly considers sources of variations such as voltage, temperature and variations induced by the clock network. The effect of variations on the energy and its tradeoff with performance is also investigated. This paper complements the previous Part I, which is focused on process variations and flip-flop timing. From a design perspective, the presented results provide well-defined guidelines for variation-aware selection of the flip-flop topologies, and for early budgeting of variations before detailed circuit design. Results are put into the technology scaling perspective through comparison of results at 65 and 28 nm. The results show that the technology scaling does not affect either the main findings of this analysis or the ranking of the considered topologies.