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Cyclostationarity Detectors for Cognitive Radio: Architectural Tradeoffs

Cyclostationarity detectors have been studied in the past few years as an efficient means for signal detection under low-SNR conditions. On the other hand, some knowledge about the signal is needed at the detector. This is typically the case in Cognitive Radio spectrum secondary usage, where the primary system is known. This paper focuses on two hardware architectures of cyclostationarity detectors for OFDM signals. The first architecture aims at secondary ISM band use, considering IEEE802.11a/g as the primary system. In this scenario, low latency is required. The second architecture targets TV band secondary usage, where DVB-T signals must be detected at very low SNR. The paper focuses on the architectural tradeoffs that the designer has to face, and how his/her choices will influence either performance or complexity. Hardware complexity evaluation on FPGA is provided for detectors that have been tested in the laboratory under real conditions.