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Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits Considering Process Variations

This paper presents a novel circuit optimization technique to reduce soft error rates (SER) of combinational logic circuits in the presence of process variations. We take advantage of gate sizing technique which has been shown to be one of the most effective methods for SER mitigation in digital circuits. A statistical SER (SSER) estimation approach is proposed to be used to prune the circuit graph into a smaller set of candidate gates. Then, we perform incremental statistical sensitivity computations to determine the resizing step that are the largest improvement to circuit SER. The proposed algorithm trades off SER reduction and area overhead. Experimental results on a variety of benchmarks show SER reductions of 67.3% with gate sizing approach, with 5.5% area overheads and delay improvement of 3.2%, on average. The runtimes for the optimization algorithms are on the order of 10 minutes.