{'fraction_non_alphanumeric': 0.023131672597864767, 'fraction_numerical': 0.0026690391459074734, 'mean_word_length': 5.048387096774194, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Ar Annealing for Suppression of Gate Oxide Thinning at Shallow Trench Isolation Edge

We investigated the effects of high-temperature N2 and Ar annealing after sacrificial oxidation on the rounding of the top corners in shallow trench isolation (STI). With the N2 and Ar annealing, the corners were rounded, and the gate oxide thinning was suppressed, indicating that high-temperature annealing in an inert gas ambient is effective for rounding the corners and increasing the gate oxide thickness. With the N2 annealing, however, the hump in the Id-Vg curve increased, and the time-dependent dielectric breakdown (TDDB) characteristics were degraded. The possible reason is that the suppression of gate oxidation and/or the oxide quality change occurs at the local spots at the top corners due to the introduction of nitrogen. With the Ar annealing, there was no hump, and the TDDB characteristics improved. It is presumed that the Ar did not accumulate at the sacrificial oxide/substrate interface. Therefore, Ar annealing after gap filling is promising in improving the performance and reliability of transistors with STI.