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Low-cost gate drive for enhancement mode SiC JFET devices

The main objective of this work is to develop a low cost gate drive circuit for the enhancement mode SiC JFET device with a comparable switching performance as those of commercial ones. To achieve this low cost requirement, the gate drive circuit design needs to use only components which are widely available. In this paper, the proposed SiC JFET gate drive circuit design is described and its switching performance is experimentally verified. The targeted cost per gate drive circuit is made to be less than US$10, which is a sizeable cost reduction in comparison to a commercially available gate drive.