{'fraction_non_alphanumeric': 0.00945945945945946, 'fraction_numerical': 0.002702702702702703, 'mean_word_length': 5.557522123893805, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Incremental Logic Synthesis through Gate Logic Structure Identification

This paper describes incremental logic synthesis for supporting function logic changes in the physical design stage of digital systems. The incremental logic synthesis is distinguished from logic synthesis in the respect that it updates only gate logic components, which must be changed due to the function logic changes, in the physically optimized gate logic structure. For making the incremental logic synthesis feasible, a gate logic structure identification and editing system has been developed with a corresponding gate matrix method as its core. This system has greatly contributed to the increase in design efficiency of the very large computer series M68XH.