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Toward implementation of associative model in real time for character recognition: A hardware architecture proposal for embedded systems

This paper presents an algorithm with low computational complexity for classifying and recognizing characters based on a random sampling and high‐dimensional binary spaces for the development of real‐time applications. Character classification is performed using uniform random sampling as the feature selection process, subsequently performing encoding as binary strings. Associative memories are commonly used as general classifiers with linear criteria to discriminate between data points. In most classifiers, the ability to efficiently detect class membership depends entirely on the expressiveness of the attributes used to encode the data. Each binary pattern encodes the distinct characteristics of several glyphs. Character features are represented as elements of a high‐dimensional binary space, where a criterion of the cluster is defined under the L1 metric. The reduction in computational complexity is analyzed. The reduction in the number of character features through random sampling techniques makes it feasible to manage all the character information in physical architectures; therefore, this approach might use resources on a hardware platform with integer operators typically implemented at the hardware‐register level. Finally, this approach is implemented in a parallel architecture Field‐Programmable Gate Array (FPGA) and tested using a Database (DB) of different fonts, including distortions, therein showing that the efficiency is comparable to the other well‐known approaches.