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Implementation of a Memory-Efficient Stereo Vision Algorithm Based on 1-D Guided Filtering

This paper presents an FPGA implementation of a memory-efficient stereo vision algorithm. Recently, a hardwareoriented stereo vision algorithm using 1-D guided filtering was proposed [1]. Our architecture is based on this algorithm and calculates the depth map in 1-D space, and therefore, the required amount of memory is significantly reduced. To realize high speed processing, we apply a full-pipeline and highly parallel structure. Implemented on FPGA, our design uses an 89 kb memory and achieves a 188 frame per second rate for 384×288 stereo images. The accuracy of the disparity map is not satisfactory; however, it can be improved by a small amount of software processing (8.6 ms) [1]. This result shows that the proposed architecture is highly efficient in terms of the required memory, and its processing speed and accuracy is the same as that of other methods.