{'fraction_non_alphanumeric': 0.016918967052537846, 'fraction_numerical': 0.0, 'mean_word_length': 5.690476190476191, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Hardware-driven prefetching for pointer data references

Effectiveness of a data prefetch mechanism lies in the exploration of regular access patterns found in the memory reference address sequence. Previous research shows that selective prefetch schemes are effective for linearly accessed memory references, including instructions and data array accesses with constant strides. Extending them to pointer accesses limits their effectiveness because such linear function nor highly accurate probabilistic model is difficult to find. In this paper, a fresh look into data access regularity and predictability from the runtime selfmodification of register values is proposed. Then, a hardware driven prefetch scheme, called the Reference Value Prediction Caching (RVPC), is proposed to realize this predictability model. This RVPC scheme is based on the detection of self-modifying instructions in loops and the use of self-modifying registers in data references. Simulation result shows that significant reduction in memory latency can be obtained, especially in non-pointer data structures including linked lists and trees.