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Anvil: Best in Class Multiprocessor Coherency Verification Tool

ARM is the Architecture for a Smarter World, and today we can find ARM cores ubiquitously in mobile phones. Soon, we will find them in data centers and server farms. At the heart of these, is an SoC that contains multiple clusters of ARM A-class application processors. Verification of a multi-core system is a big challenge, as the bugs are difficult to find and often found late in the design cycle. Coverage closure is an intensive process as well. There are different approaches to multicore verification, but top-level RTL simulation is where coherency issues are more pertinent and easier to debug. We introduce Anvil, a Random Instruction Stream (RIS) generator for next-generation mobile and server-class processors, developed by Arm’s own Architecture & Technology Group. Anvil uses a constrainedrandom top-level testing approach to target memory subsystem components critical to multicore functionality, such as Cache and Memory Hierarchy, cross-core coherency transactions, and the Load Store pipeline. In this paper, we explore Anvil’s features, its core competencies in Memory subsystem verification, and the flexibility it provides to the user to direct what his/her regression targets in the multiprocessor environment.