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Three-Dimensional Ultrasound Imaging Utilizing Hardware Accelerator Based on FPGA

We have developed a 3D ultrasound imaging system involving computations for use in medical diagnostic applications [1,2]. This system enables us to observe 3D images of moving objects for each transmission. Therefore, we can acquire a 3D image sequence at a high frame rate. Fig. 1 shows a 3D image reconstructed by our 3D ultrasound imaging system. In the pork block, a needle is inserted as a marker. In the present system, a 3D image reconstruction algorithm is implemented by using the C language software (SW). When processing is performed by a personal computer (PC) with Pentium 4 2.53 [GHz] CPU and DDR512 [MB] memory, the latency for generating a 3D image is approximately 40 s. As apparent from the above latency value, it would be difficult to realize high-speed image reconstruction by employing a SW implementation approach. Reduction in the processing time is one of the most important issues in practical applications. As a solution to this issue, we have investigated the HW implementation of the algorithm.