{'fraction_non_alphanumeric': 0.02532617037605526, 'fraction_numerical': 0.0, 'mean_word_length': 5.009216589861751, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A modified space vector modulation scheme to reduce common mode voltage for cascaded NPC/H-bridge inverter

Common-mode voltage (CMV) exists widely in a three phase inverter and it is particularly obvious and more serious harm in high voltage inverter system. This paper proposes a modified space vector pulse width modulation (SVPWM) strategy to reduce CMV for a five-level neutral-point-clamped (NPC) /H-bridge inverter. A five-level NPC/H inverter will be equivalent to two three-level NPC inverters using the proposed concept of equivalent inverter and the space vector plane will be simplified to two three-level planes. In order to modulate the two equivalent three-level NPC inverters for resynthesizing the original reference voltage, the reference voltage will be simplified to two reference voltages. Therefore, a five-level SVPWM with high complexity can be accomplished briefly by two separate three-level SVPWM. Besides, one equivalent inverter always operates with zero common mode voltage to suppress CMV and the other one operates with conventional three-level SVPWM. Theoretical analysis on dc supply voltage utilization and maximum amplitude of CMV is carried out. Simulation results show that the CMV is effectively mitigated and it almost has no affect on the maximum output voltage.