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A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC

This paper analyzes the impact of clock skew between comparators in a flash ADC, showing that the SNDR penalty introduced by this effect can become significant at high frequencies. To address this issue, a passive resonant clock network is proposed to distribute the clock to the comparators in a flash ADC. The inductive termination of this network serves to resonate out the parasitic and input capacitances of the ADC, allowing for a 2.5-GHz clock signal to be conveyed to a load of 256 comparators while consuming less power than traditional clock networks due to the reduced number of active clock buffers required. This clock network produces little timing skew at the resonant frequency, thereby obviating the need for a track-and-hold amplifier, which further reduces the power requirements of the ADC. This clock network was implemented in a 5-bit flash ADC designed in 65 nm CMOS, with a measured SNDR of 26 dB.