{'fraction_non_alphanumeric': 0.031408308004052685, 'fraction_numerical': 0.0, 'mean_word_length': 5.543046357615894, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
SpinalFuzz: Coverage-Guided Fuzzing for SpinalHDL Designs

Boosting hardware design productivity is a major plus of SpinalHDL, a Scala-based Hardware Description Language (HDL). SpinalHDL achieves this by providing object oriented programming, functional programming, and meta-hardware description finally enabling the generation of Verilog code. Despite all the advantages of SpinalHDL, verification is the biggest challenge here as well.In this paper, we bring Coverage-Guided Fuzzing (CGF), a well-established software testing technique, to the SpinalHDL design flow. We have implemented our approach SpinalFuzz on top of the fuzzer AFL++. We leverage Scala-features to automate as many tasks as possible and ease the integration of fuzzing in SpinalHDL. In the experiments we demonstrate the effectiveness of SpinalFuzz in comparison to Constrained Random Verification (CRV). For a wide range of SpinalHDL designs we show that SpinalFuzz outperforms CRV and reaches coverage-closure.