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A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time

Process variation in deep nanometer technologies causes read, write and retention failures in SRAM and results in yield loss. Although using larger transistors and higher supply voltages helps to mitigate these failures and improve the yield, they come at the cost of more power consumption, more area overhead and performance degradation. Reconfigurable control-signal circuits in SRAM not only help to reduce the failure rates, but also allow calibration after fabrication to improve the yield, reduce the power consumption and upgrade the performance. In this paper, a reconfigurable replica bitline scheme for sense amplifier set time is proposed to reduce the read failures and provide a wide operating-voltage range for SRAM. The proposed reconfigurable replica bitline also allows recalibration when SRAM performance deteriorates due to device aging degradation. Monte Carlo simulation results for a 64 kb SRAM array show that the proposed technique can reduce the access time by 20% compared to conventional replica bitline design in IBM/Global Foundries (GF) cmos32soi 32nm technology at 0.9 V with no area overhead.