{'fraction_non_alphanumeric': 0.02631578947368421, 'fraction_numerical': 0.0035087719298245615, 'mean_word_length': 4.947916666666667, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield

This work experimentally investigates the impact of line-edge roughness (LER) on the intrinsic transistor performance of the MOS transistor. Examined gate lengths range down to 50 nm. To emphasize the impact of LER, transistors with extra rough poly gates are created by e-beam lithography. Assumptions of models, that describe the effects of LER, are tested on transistors with sinusoidal gate-shapes. For the first time, the impact of LER on transistor yield is reported.