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Backoff hardware architecture for inter-FPGA traffic management

Multi-FPGA platforms are considered to be the most appropriate experimental way to emulate a large Multi-Processor System-on-Chip based on a Network-on-Chip. However, the use of a Network-on-Chip in several FPGAs requires inter-FPGA communication links to replace intra-FPGA links between routers. As the ratio of the logic capacity to the number of IOs only increases slowly with each generation of FPGA, IOs in FPGA are becoming a scare resource. And as there are more routers than IOs, using a Network-on-Chip requires sharing inter-FPGA links between routers, and sharing an external link can lead to bottlenecks. Here, we evaluate the inter-FPGA traffic management using a backoff algorithm. We compare the backoff architecture using different sizes of pseudo random number generators. This evaluation makes it possible to choose the best pseudo random number generator for the size of the Network-on-Chip to be deployed.