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Compact Grid Layouts of Some Multi-Level Networks

We consider the problem of generating layouts of multi-level networks, in particular , switching, sorting, and interconnection networks, as compactly as possible , that is, with minimum area, on VLSI grids. Besides traditional interest in these problems motivated by interconnection topologies in parallel computing and switching circuits in telecommunications, there is renewed interest in such layouts as routers in ATM (Asynchronous Transfer Mode) switches. Our results improve on the existing area bounds for these networks by factors of up to 3. At the core, they rely on a systematic, combinatorial approach that we develop for the layout of general permutation networks as well as certain special classes of permutations.