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Influence of Plugging DC Offset Estimation Integrator in Single-Phase EPLL and Alternative Scheme to Eliminate Effect of Input DC Offset and Harmonics

In this paper, the dynamic expressions of the amplitude and frequency estimated by the standard enhanced phase-locked loop (EPLL) and the ones with input dc offset estimation integrator (DCEI) are derived originally and reveal that the DCEI enlarges the amplitude of the periodic ripples caused by the dynamic disturbances and prolongs the dynamic process. To achieve correct estimation when the input signal contains dc offset and harmonics but without deteriorating the dynamic performance, an improved EPLL combined with delayed signal cancellation (DSC) is proposed. A DSC operator is employed to the input of the EPLL to eliminate dc offset and even-order harmonics. A cascaded DSC (CDSC) module is applied in both frequency and amplitude loops to remove the effect of most of the residual odd-order harmonics. The structure of the CDSC module and delay coefficients are designed in detail. Experimental results of all the three PLLs are presented and compared to validate the theoretical analysis results and the proposed EPLL.