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A placement algorithm for implementation of analog LSI/VLSI systems

Analog macro-cell placement by nature is an NP-complete (nondeterministic polynomial-time) problem. In this paper, we present an approach following the optimization flow of normal genetic algorithm (GA) controlled by the methodology of simulated annealing. The bit-matrix representation is employed to improve the search efficiency. Moreover, a cell-slide based flat placement style satisfying the symmetry constraints is developed to drastically reduce the configuration space without degrading search opportunities. Furthermore, the dedicated cost function covers the special requirements of analog integrated circuits, including area, net length, aspect ratio, proximity, parasitic effect, etc. the algorithm parameters are studied using fractional factorial experiments and a meta-GA approach. The proposed algorithm has been tested using several analog circuits, and appears superior to the simulated-annealing approaches mostly used for analog macro-cell placement nowadays.