{'fraction_non_alphanumeric': 0.01691542288557214, 'fraction_numerical': 0.001990049751243781, 'mean_word_length': 5.096969696969697, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Memory Access Analysis of Many-core System with Abundant Bandwidth

Many-core system is main architecture trend currently. One of the dominating challenges for on-chip manycore system is the memory wall. However traditional research primarily focus on the limited bandwidth. To solve this problem, many-core system is aided with large cache, and a lot of complex approaches about memory and cache are adopted aiming at relaxing the pressure of bandwidth and improving the efficiency of cache. All these methods generate much cost of area and power. In this paper, we are motivated by the feature of abundant bandwidth and low latency of optical interconnect. We analyze the characteristics of memory access on 64 cores system under the case of high bandwidth which can be assumed to benefit from optical interconnect, considering the sensibility with bandwidth and cache for different benchmarks. Finally, we discuss about promising basic frameworks suitable for manycore system with optical interconnect.