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DFM-aware structured ASIC design

In this paper, we present a new structured ASIC approach which utilizes an array of 2-input NAND gates. Our NAND2 array based circuit implementation reduces manufacturing costs, and design turn-around times because different designs can share the same masks up to the poly layer. The regular layout structure of our NAND2 array also helps in reducing systematic variations. We compared the performance of our NAND2 array with the ASIC approach by implementing several benchmark circuits using both methods. The experimental results demonstrate that our approach has lower area overheads than previously reported structured ASIC approaches. Lithographical simulation results demonstrate that our approach has lower errors on the poly and the Metal1 layers compared to the ASIC approach.