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Design of blocks for a Field Programmable Mixed Array (FPMA)

In this work, we propose an architecture for a Field Programmable Mixed Array (FPMA), with focus on the basic building blocks used in the analog reconfigurable core. Although analog circuits do not benefit from technology scaling as much as their digital counterparts, analog designers cannot avoid using deep submicron fabrication processes because of System on a Chip integration requirements. Considering the increased negative effects of process variations in smaller feature sizes, reconfigurability can be of great use for compensation of process-related errors. Analog core of the proposed FPMA contains basic building blocks such as programmable operational transconductance amplifiers, wide input range operational amplifiers, dynamic comparators, and capacitor arrays. Digital core is based on the configurable logic cells of LUT-based FPGA architectures. Data converters are also implemented as interface between the analog and digital cores. All circuits were designed in a 130nm CMOS process with 1.2V single power supply.