{'fraction_non_alphanumeric': 0.02412280701754386, 'fraction_numerical': 0.006578947368421052, 'mean_word_length': 4.858974358974359, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
43.4: Address Time Reduction in PDPs by means of Partial Line Doubling

This paper describes a technique, called Partial Line Doubling (PLD), that reduces the over‐all addressing time of PDPs. This reduction goes at the cost of vertical resolution but the picture quality deterioration is minimised by using appropriate video processing algorithms. The resulting time gain can be used to increase the peak white level of the PDP and/or add extra subfields.