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The Influence of a Novel Contacted Polysilicon-Filled Deep Trench (DT) Biased Structure and Its Voltage Bias State on CMOS Latchup

The discrepancy between polysilicon-filled deep trench (DT) isolation and trench isolation (TI) CMOS latchup immunity is addressed; this paradox is analyzed using by electrically connecting the poly-silicon region of the deep trench (DT) structure. With the ability to electrically bias the poly-silicon region within the deep trench structure, CMOS latchup is analyzed for the state of high bias, floating and grounding of the trench isolation structure. The novel structure was implemented into a 0.13-mum BiCMOS technology with a 200 GHz fT  BiCMOS SiGeC HBT device. Experimental results show that CMOS latchup is modulated by the trench voltage bias state. Key latchup metrics, such as turn-on, trigger, and holding voltage will be shown. With trench voltage bias, CMOS latchup turn-on voltage remains unchanged, but the latchup trigger state varies from 40 V to 80 V. This has significant ramifications to CMOS latchup in BiCMOS Silicon Germanium technology, automotive applications, power electronics, as well as space applications