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A mini single-port instruction cache and its priority strategy for load-store conflict in a general purpose DSP

In a general purpose DSP which is based on a modified Harvard architecture, a small instruction cache is adopted to alleviate the resource conflict in the pipeline. It is accessed not in every clock cycle, but when conflicts happen in the pipeline. For the purpose of minimizing its area and power dissipation, the instruction cache has a single address port, which means in the same clock cycle only one operation of load or store can be realized. So some priority strategies should be applied if requests of reading and writing cache come at the same time. In this paper four strategies are presented and analyzed. According to the result of simulations under some benchmarks, the instruction cache using a certain strategy may achieve almost the same hit rate as a dual-port one.