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A multidimensional study on the feasibility of parallel switch-level circuit simulation

This paper presents the results of an experimental study to evaluate the effectiveness of multiple synchronization protocols and partitioning algorithms in reducing the execution time of switch-level models of VLSI circuits. Specific contributions of this paper include: parallelizing an existing switch-level simulator such that the model can be executed using conservative and optimistic simulation protocols with minor changes; evaluating effectiveness of several partitioning algorithms for parallel simulation; and demonstrating speedups with both conservative and optimistic simulation protocols for seven circuits, ranging in size from 3 K transistors to about 87 K transistors.