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Energy management techniques for ultra-small bio-medical implants

Trends in the medical industry have created a
growing demand for implantable medical devices. In particular, the
need to provide medical professionals a means to continuously
monitor bio-markers over long time scales with increased precision
is paramount to efficient healthcare. To make medical implants more
attractive, there is a need to reduce their size and power
consumption. Small medical implants would allow for less invasive
procedures and greater comfort for patients. The two primary
limitations to the size of small medical implants are the batteries
that provide energy to circuit and sensor components, and the
antennas that enable wireless communication to terminals outside of
the body. In this work we present energy management and low-power
techniques to help solve the engineering challenges posed by using
ultracapacitors for energy storage. A major problem with using any
capacitor as an energy source is the fact that its voltage drops
rapidly with decreasing charge. This leaves the circuit to cope
with a large supply variation and can lead to energy being left on
the capacitor when its voltage gets too low to supply a sufficient
supply voltage for operation. Rather than use a single
ultracapacitor, we demonstrate higher energy utilization by
splitting a single capacitor into an array of capacitors that are
progressively reconfigured as energy is drawn out. An energy
management IC fabricated in 180-nm CMOS implements a stacking
procedure that allows for more than 98% of the initial energy
stored in the ultracapacitors to be removed before the output
voltage drops unsuitably low for circuit operation. The second part
of this work develops techniques for wide-input-range energy
management. The first chip implementing stacking suffered an
efficiency penalty by using a switchedcapacitor voltage regulator
with only a single conversion ratio. In a second implementation, we
introduce a better solution that preserves efficiency performance
by using a multiple conversion ratio switched-capacitor voltage
regulator. At any given input voltage from an ultracapcitor array,
the switched-capacitor voltage regulator is configured to maximize
efficiency. Fabricated in a 180-nm CMOS process, the chip achieves
a peak efficiency of 90% and the efficiency does not fall below 70%
for input voltages between 1.25 and 3 V.