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Efficient DSP implementation of an LDPC decoder

We present a high performance implementation of a belief propagation decoder for decoding low-density parity-check (LDPC) codes on a fixed point digital signal processor. A simplified decoding algorithm was used and a stopping criteria for the iterative decoder was implemented to reduce the average number of required iterations. This leads to an implementation with increased throughput compared to other implementations of LDPC codes or turbo codes. This decoder is able to decode at 5.4 Mbps on a Texas Instruments TMS320C64xx DSP running at 600 MHz.