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Implementation of fixed DSP functions using the reduced coefficient multiplier

Distributed arithmetic (DA) has been successfully applied to the design of area efficient multipliers on FPGAs for DSP applications. Whilst DA is efficient in applications where the coefficients are fixed, there is little option for applications with a limited range of coefficient values. This paper describes a technique for developing area efficient multipliers for a range of DSP applications that fall into this category. This is accomplished by employing multiplexers at no extra cost to increase the functionality of existing fixed coefficient multipliers. The technique has been applied to a DCT FPGA implementation where an area decrease of up to 50% and a speed increase of 33% was achieved over the conventional route.