{'fraction_non_alphanumeric': 0.03423566878980892, 'fraction_numerical': 0.007961783439490446, 'mean_word_length': 4.792626728110599, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Fast Clustering-Based Min-Cut Placement Algorithm With Simulated-Annealing Performance

Placement is an important constrained optimization problem in the design of very large scale 
(VLSI) integrated circuits [1–4]. Simulated annealing [5] and min-cut placement [6] are two 
of the most successful approaches to the placement problem. Min-cut methods yield less 
congested and more routable placements at the expense of more wire-length, while simulated 
annealing methods tend to optimize more the total wire-length with little emphasis on the 
minimization of congestion. It is also well known that min-cut algorithms are substantially 
faster than simulated-annealing-based methods. In this paper, a fast min-cut algorithm 
(ROW-PLACE) for row-based placement is presented and is empirically shown to achieve 
simulated-annealing-quality wire-length on a number of benchmark circuits. In comparison 
with Timberwolf 6 [7], ROW-PLACE is at least 12 times faster in its normal mode and is at 
least 25 times faster in its faster mode. The good results of ROW-PLACE are achieved using 
a very effective clustering-based partitioning algorithm in combination with constructive 
methods that reduce the wire-length of nets involved in terminal propagation.