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Fractional phase divider PLL phase noise and spurious modeling

In this paper, we present the phase noise and spurious model for fractional phase divider (FPD) PLL architecture. This architecture, ideal for over-MHz bandwidth PLL, is composed of a low power ring oscillator (RO) used as voltage controlled oscillator (VCO), and a divider which reuses the RO phases to perform a quasi-perfect fractional division. We provide an implementation of this low area architecture, used as low power local oscillator (LO) for Internet of Things (IoT) and Bluetooth Low Energy (BLE). Additionally we propose four VCOs architectures phase noise measurements designed on FDSOI 28nm with extreme power optimization, planned to be used for this architecture.