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Design of a Simplified Fuzzy Inference Engine using FPGA

This paper presents the design of a simplified version of fuzzy inference engine (FIE) built on an Altera Flex 10K field programmable gate array (FPGA). This approach uses a modified center of area method. By introducing some constraints on the defined fuzzy subsets the computational speed of the FIE is made faster. The approach discussed in this paper removes the division bottleneck and keeps the fuzzy look-up tables small, thereby reducing the computational complexity of the FPGA. Parallelism is introduced in accessing the memory, thereby increasing the computational speed. A speed of 2.5 M FLIPS is achieved with a speed grade of 25 MHz.