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An algorithm and architecture for non-recursive pseudorandom sequence generation using sequence folding technique

In this paper, a new algorithm along with its first order hardware architecture is proposed to build the pseudorandom non-recursive binary sequence using sequence folding technique to protect the confidential information and data integrity in cryptography applications. Unlike the existing techniques to build the pseudorandom recursive sequence. The novelty of this proposed algorithm along with first order architecture is to generate non-recursive nibble of thirty one (O) from the input seed of four () bits. In the sequence folding technique, an arbitrary linear recursive binary sequence is folded to a minimum state by an empirical approach to build the non-linear Boolean function and realized using algebraic normal form. In this proposed first order architecture, the constructed non-linear Boolean functions are utilized to engender the pseudorandom binary non-recursive sequence. The proposed first order architecture is implemented using Verilog HDL and further prototyped on commercially available FPGA device ‘Spartan 3E xc3s500e-4fg320’. The realization of proposed architecture in this FPGA device accomplishes an improved data throughput, and efficiency (i.e. throughput/area) is compared to existing techniques. The generated binary sequence from the experiment is further analyzed briefly for sequence size, number of stages, correlation and verified for randomness by using NIST statistical test suites.