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An area-efficient asynchronous FPGA based on fine-grain power gating and time multiplexed dual rail encoding

A fundamental challenge in the IC manufacturing industry is high performance with minimized power, area and cost. Asynchronous FPGAs have the advantages of lower power consumption, lower electromagnetic interference, and better modularity in large systems. In this paper, we focus on the reduction of dynamic power consumption of FPGAs for which we use two techniques. Fine-grain power gating methods are employed to decrease the power consumption. In the implemented architecture, the granularity size of a power-gated domain is as fine as a single two-input and one-output lookup table. The proposed architecture can directly detect the activity of each look-up-table easily by exploiting the advantageous features of asynchronous architectures. Moreover, the arrival of data can be detected in advance and this prevents the increased delay required for the waking up of a logic block and the power consumption due to unnecessary switching. A comparison study between the existent and proposed dual rail encoding architectures shows that the newly implemented logic block with power gating and TM-LEDR encoding occupies lesser area as compared to the already existing conventional ones.