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Design of Gate‐Ground‐NMOS‐Based ESD Protection Circuits with Low Trigger Voltage, Low Leakage Current, and Fast Turn‐On

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate‐triggered NMOS and a gate‐substrate‐triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn‐on speed. The proposed ESD protection devices are designed using 0.13 μm CMOS technology. The experimental results show that the proposed substrate‐triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn‐on time of 37 ns. The proposed gate‐substrate‐triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.