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A study of CD budget in spacer patterning technology

We constructed CD budget for spacer patterning technology which is one of the strongest candidates in double patterning technologies for below 3x nm half pitch generations. In the CD budgeting, three patterning portions of grid patterns should be considered, namely, "line", "paired space" and "adjoined space", because they have individual process error sources that affect CD variations. Analysis of the patterning process flow revealed that the amount of CD variations for positive type spacer patterning technology was in the order of "adjoined space" > "paired space" > "line". Also, the experimental verifications in CD variations substantiated the constructed CD budget. From the viewpoint of design for manufacturability (DfM), these process features should be taken into account in the device engineering. Therefore, for the successful implementation of spacer patterning technology into high-end devices, we propose a cross- functional development scheme encompassing device technologies and process technologies using the constructed CD budget.