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Fractional Lambda Switching -node Design and Time-blocking Analysis - Viet-thang Nguyen

Streaming and real-time traffics are dramatically booming on the Inter-net. Innovative and successful business models (such as Skype, Youtube, IPTV and the forth coming Joost project) may bring new dimensions into revenues of dot-com and telecommunication industry; however, they also introduce a threat to ISPs and carriers in terms of scaling their networks so that they can handle traffic more efficiently and utilize the bandwidth provided by the DWDM transmission technology. Moreover, to ensure that customers who pay more get more priority for their traffic, QoS guarantees are vital parts of bandwidth management. When more real-time traffic is injecting in networks, handling bursty traffic and jitter is increasingly important. However, as pointed out in several researches, when 35% of link capacity is streaming traffic, current QoS Internet mechanisms start degrading network utilization. Since current QoS mechanisms do not fully address these issues, there is a need for new approaches to solve these problems. The thesis focuses on important aspects of Time Driven Switching (TDS)-Fractional Lambda Switching (FλS). TDS-FλS architecture provides guaranteed QoS, and it is highly scalable and compatible to the current In-ternet architecture. In TDS-FλS, a common time reference (CTR) and pipeline forwarding are used to deliver traffic flows end-to-end. Thus, the header processing overhead is eliminated and no or few buffers (for enabling scheduling delay) at switching nodes are required. TDS-FλS is a novel technology offering a networking paradigm with no congestion, no jitter, no packet loss, but many open issues still need investigations. In the first part of the thesis, we discuss the use of tunable laser and propose some related architectures to realize all-optical switches that enable sub-wavelength granularity switching. The design objective is minimizing node's hardware complexity while maximizing node's scheduling flexibility so that a designed node has a low or null space blocking. Notably, we prove that one design is strictly non-space blocking with hardware complexity (in terms of counting switching elements) equivalent to that of a Clos network, known to be the minimal complexity non blocking architecture. The remaining part of the theoretical work of this thesis is dedicated to the analysis of the blocking performance. Thought it has been conjectured that TDS-FλSs yield low blocking under high load conditions, no formal proof has been produced so far. The objective of this research track is a comprehensive blocking analysis under various contexts and dependent parameters such as load, hop-length, possible scheduling delay, time-cycle …