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Implementation of an on-chip bus bridge between heterogeneous buses with different clock frequencies

Recently, embedded systems design focuses on low-power dissipation and system-on-chip. Thus, ARM processor and AHB came to be popular in embedded systems. Whereas the bus has many advantages for high-performance modules, it has limitations on interfacing with low-speed devices. Therefore, a bridge is necessary between them. Although AHB-to-APB bridge is a standard in AMBA system, it is not useful because of the fixed interfacing speed. Moreover, it is difficult that the existing IP cores for the peripheral controllers are reused with APB. In this paper, we suggest more general and flexible bridge than the existing one for SoC.