{'fraction_non_alphanumeric': 0.03409090909090909, 'fraction_numerical': 0.0016233766233766235, 'mean_word_length': 5.295918367346939, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
High-Level verifiable data-path Synthesis for DSP systems

Field Programmable Gate Arrays (FPGAs) provides fast and low cost implementation of DSP systems. The increasing popularity of FPGAs and lack of experience of the DSP algorithm designers on HDLs, makes the High Level Synthesis tools vital for design, early performance estimation, prototyping, testing and verification. In this paper, we present a high-level design-time verifiable Register-Transfer Level (RTL) generator which is integrated to RH(+) framework, a delay and area estimation model of the generated circuit for the Xilinx Spartan 3 FPGA Family.