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EFFICIENT PEEC MODELING OF MULTI-LAYER BOARDS AND MULTI-CHIP MODULES

Multi-Chip Modules (MCM) for high speed digital applications use meshed planes between the signal layers for shielding and power supply. Both wave impedances of the signal lines and coupling behavior between different signal layers are influenced by the properties of these meshed planes. Together with the quick increase of operating frequency of high-speed integrated circuits (IC), this may cause problems such as dispersion, crosstalk, and packaging effects which must be investigated by means of simulations. The Partial Elements Equivalent Circuit (PEEC) method has proven to be suitable to deal with such systems, particularly to investigate ground bounce effects. For analysis of large interconnect and packaging structures, however, the computing time increases very rapidly with the system’s complexity. To reduce the costs of calculation, especially for inductance and capacitance calculation, a method is introduced that leads to both accurate and fast results. The validity of the modeling is verified with Sparameter calculations of blocking measures in a multilayer board and shall be used for investigations of multichip modules.