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Test generation for sequential circuits using parallel fault simulation with random inputs

This paper presents a simple test generation method for sequential circuits using a parallel simulator with random inputs. The proposed test generation method generates sequences by simulating as many states as possible, without using a cost function for a target fault. To generate effective test sequences, dynamic switching is done between I-Mode and S-Mode parallel simulators. Here the I-Mode simulates 32 patterns for one state in parallel and the S-Mode simulates 32 patterns for 32 states in parallel. Experimental results for ISCAS'89 benchmark sequential circuits show that our method achieves test sequences with high coverage in acceptable CPU time.