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Verification of electronic systems

The complexity of electronic systems is rapidly reaching a point where it will be impossible to verify correctness of the design without introducing a verification-aware discipline in the design process. Even though computers and design tools have made important advances, the use of these tools in the commonly practised design methodology is not enough to address the design correctness problem since verification is almost always an after-thought in the mind of the designer. A design methodology should on one hand put to good use all techniques and methods developed thus far for verification, from formal verification to simulation, from visualization to timing analysis, but should also have specific conceptual devices for dealing with correctness in the face of complexity. This paper is organized as follows: we review the available verification tools. Formalization is investigated in several contexts. Abstraction is presented with a set of examples. Decomposition is introduced. Finally a design methodology that includes all these aspects is proposed.