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Asynchronous Reversible Computing Unveiled Using Ballistic Shift Registers

Reversible logic can provide lower switching energy costs relative to all irreversible logic, including those developed by industry in semiconductor circuits, however, more research is needed to understand what is possible. Superconducting logic, an exemplary platform for both irreversible and reversible logic, uses flux quanta to represent bits, and the reversible implementation may switch state with low energy dissipation relative to the energy of a flux quantum. Here we simulate reversible shift register gates that are ballistic -- their operation is powered by the input bits alone. A storage loop is added relative to previous gates as a key innovation, which bestows an asynchronous property such that input bits can arrive at different times as long as their order is clearly preserved. The shift register represents bit states by flux polarity, both in the stored bit as well as the ballistic input and output bits. Its operation consists of the elastic swapping of flux between the stored and the moving bit. This is related to a famous irreversible shift register, developed prior to the advent of superconducting flux quanta logic (which used irreversible gates). In the base design of our ballistic shift register (BSR) there is one 1-input and 1-output port, but we find that we can make other asynchronous ballistic gates by extension. For example, we show that two BSRs operate in sequence without power added, giving a 2-bit sequential memory. We also show that a BSR with two input and two output ports allows a bit state to be set from one input port and then conveyed out on either output port. The gate constitutes the first asynchronous reversible 2-input gate. Finally, for a better insight into the dynamics, we introduce a collective coordinate model, where motion reduces to two coordinates and is subject to a potential determined by the input bit and initial stored flux quantum.


I. INTRODUCTION
Reversible logic promises the ultimate performance in high-efficiency digital computing at the gate level, and this has the potential to influence industry based computing which uses irreversible gates, but more research is needed on reversible circuits. Superconducting circuits provide an excellent platform for digital gate innovation, in both irreversible and reversible logic types, where both use single-flux quanta (SFQ). Irreversible superconducting logic has been developed since the 1980s, and has now grown to several families identified as RSFQ 1,2 , AQFP 3,4 , RQL 5 , and RSFQ descendants [6][7][8][9][10] . These logic types have demonstrated advanced 4-8 bit processing 4,[11][12][13] and one of them is used to realize a multi-band analogto-digital receiver 14 . In the irreversible superconducting gates, the energy efficiency is limited by the dissipative switching between bit states. The switching involves the damped 2π-transition between two potential minima of a current-biased and resistively-shunted JJ, comparable to the switching that occurs in a biased JJ of a SQUID. The energy dissipated per switching is approximately equal to the bias current times the superconducting flux quantum, and is on the same order as the energy barrier. Since bit energy and energy barriers are relatively high ( k B T ), the energy cost of an irreversible logic gate is generally much higher than the lower theoretical limit of ln(2)k B T , which is related to the reduction of entropy from bit erasure 15 .
Though reversible digital gates can avoid switching en-ergy costs in computing, and have the potential to impact the future outlook of digital computing, they are rarely explored. In superconducting logic, reversible gates are studied in the families named nSQUID [16][17][18] , Reversible QFP 19 , and RFL [20][21][22] . The former two rely on adiabatic clocking and power such that the circuit state always stays close to (the state of) the minimum in potential energy throughout the switching process. The dissipated (switching) energy is typically lowered in proportion to the clock speed. Even though these logic types are efficient at a multi-GHz speed, the adiabatically powered multi-phase clock adds complexity to the architecture and limits the practical clock speed relative to other superconducting logic such that an alternative should be studied. In contrast, the latter one is ballistic and could provide a relative advantage in speed or architecture. In reversible logic, the Josephson junctions are under-damped for energy-efficient switching 23 . If carefully designed, reversible gates allow for dissipation much smaller than the bit energy in an interesting set of reversible processes (dependent on the initial bit states). Logical reversibility, i.e. the bit-preserving and one-to-one mapping of the logic function, is a necessary condition for energy-efficiency but is insufficient by itself.
For historical context, we note that in an influential work prior to the 1980's development of modern irreversible logic 2 , the Bell-Labs team of Anderson, Dynes, and Fulton (ADF) proposed a "flux shuttle" 24 . The shuttle is based on long Josephson junctions (LJJs) and an SFQ which is advanced along the circuit by current pulses 25 -it acts as a shift register because the SFQ can be interpreted as a bit state according to its presence (or absence). As an aside, after the advent of SFQ logic, types were proposed where a bit was encoded with an SFQ in one of two locations to help address synchronousbit timing challenges [26][27][28] . Similar to most SFQ logic, the ADF flux shuttle is thermodynamically irreversible because its operation relies on resistive damping. In particular, a large fraction of the bit energy dissipates when the SFQ is stopped in a potential well for bit storage and energy is supplied again when shifting the bit forward to the next storage cell.
Recently, a helpful abstract model for asynchronous ballistic reversible computing was put forth 29 , which describes asynchronous ballistic reversible gate requirements and argues for their discovery. In the same group, a ballistic reversible memory cell was proposed 30 , which uses a single port for both input and output states. However, the cell is not obviously usable in currently known gate architectures. These architectures are "feedforward" because they require an input and output port allowing the output signal to be distinct and usable as an input to a subsequent gate.
The ballistic-reversible gates of RFL are by design multiport gates and include the fundamental 1-bit gates (NOT and ID), a 2-bit NSWAP 20 gate, and a 2-input IDSN 21 gate. However, the latter ones are 2-bit input gates that require synchronous inputs, which implies a strict timing requirement that is desirable to overcome. For background, previous (synchronous-input) ballistic RFL can be viewed as an advancement over the model of billiard ball computing 31,32 . The result of a billiard ball gate consists of the conditional presence of the bit on one of multiple possible paths. These paths have an error in a planar (2D) scattering processes related to the imprecision of the macroscopic hardware. On the other hand, RFL gates have bit lines consisting of input and output LJJ pairs, where an output bit is always carried on the same bit line as the input, independent of the bit state (assuming specified precision margins). These bit lines are 1D and thus guide the bit forward without error in state.
Here we propose ballistic shift registers (BSRs) -multiport ballistic gates which use memory. The circuits can store one bit of information in the form of a (static) SFQ in a storage cell. Similar to the ADF flux shuttle, a BSR uses fluxons moving in LJJs as input and output bits (for clarity, here and below we typically use the term fluxon for an SFQ within an LJJ). However, the BSR is ballistic because its operation is solely powered by the energy of the input bit. Unlike the 'asymmetric' bit-state encoding in the ADF flux shuttle (fluxon presence vs absence), the BSR uses the two degenerate flux states (1 and -1) to represent the bit states, both for the moving bit (at input and output) and the stored bit.
By combining the scattering-based reversible dynamics of RFL with an internal (stored) state, the BSR gates constitute the first set of asynchronous ballistic computing circuits. These gates are suitable for feed-forward computing, where the output port is separate from the input. Additionally, we found by using the storage loop that we could choose dynamics that are favorable in combination. For one half of the possible cases, the BSR uses dynamics that are similar to the NOT gate, which requires a resonance for polarity inversion 20 . In the other half of the cases, the BSR uses transmission dynamics, which are simpler than the previously known ID resonance gate 20 . This combination improves the parameter margins compared with the 2-bit synchronous IDSN gate 21 , which combines the NOT and ID dynamical cases. Another feature besides asynchronous input bits is the ability to have a logical depth of 2 -according to simulations, two of our gates can be combined in sequence directly, without external power. In addition, we show a 2-input BSR, the first 2-bit asynchronous ballistic gate circuit. It allows one to write a bit to the register and then transfer it to a second bit line using an input fluxon on a second bit line.
The BSR gates have wide parameter margins even for high efficiency. In the case studied, the gate efficiency is set to 86% such that with present-day Nb-fabrication, we estimate their energy cost at < 3.7 zJ. These asynchronous ballistic gates add functionality for practical SFQ logic. Similar to previous RFL gates, they have the potential to exploit naturally large JJ switching rates to realize high-throughput logic that is comparable to other SFQ logic.
This article is organized as follows: In Sec. II we present the 1-input BSR, analyze its steady states and discuss the operation of the BSR for both a 1-bit and a multi-bit serial shift register. The 2-input BSR is introduced in Sec. II E, and Sec. II F gives an overview of the operation margins. In the remaining section before the conclusion, Sec. III, we analyze the BSR dynamics by means of a collective coordinate model (CCM), which is shown to quantitatively describe the BSR dynamics and help with the interpretation of the gate dynamics. The end of Sec. II (II G not III) provides a discussion which includes technical findings on: energy efficiency, speed, energy-delay product, and logical depth.

II. BSR CIRCUIT AND OPERATION
The Anderson-Dynes-Fulton (ADF) flux shuttle is an important historical step in the development of SFQ digital electronics, because it interprets SFQ as bits and it is closely related to RSFQ shift registers even though it predates RSFQ by approximately a decade 33 . In the ADF flux shuttle, the SFQ can be localized in a potential well generated by device geometry or magnetic fields, and can be moved forward to the next potential well by current pulses 25 . In contrast, RSFQ shift registers use DC current bias and SFQ clock signals to forward the bits. To do this, RSFQ uses D Flip Flops (also called an RS Flip Flops) as shift register cells. In contrast, RSFQ shift registers require only dc currents. An SFQ repre-sents the logic 1-state, while the 0-state is represented by an absence of flux at the same position. When an SFQ arrives at a JJ of the RSFQ shift register, it adds to the existing dc-current bias, such that the JJ switches phase by 2π and thereby shifts the SFQ to the next circuit cell. This operation principle is used generally in RSFQ logic gates 2 as well as other SFQ logic gates. As the JJs in RSFQ circuits are critically damped and biased near their critical current I c , the 2π-phase switching is accompanied by an energy dissipation of ∼ I c Φ 0 , where Φ 0 is the flux quantum. This dissipated energy is of the same order of magnitude as the energy of the 1-state bit. For context, note that a fluxon bit in an LJJ can be related to the SFQ energy in a typical digital cell: the typical bit energy for an SFQ is ∼ J c d 2 Φ 0 with JJ critical current density J c and diameter d and that of a fluxon in a long Josephson junction is ∼ J c wλ J Φ 0 for a long junction with width w and Josephson penetration depth λ J , where the latter determines the fluxon length.
Reversible fluxon logic (RFL) represents the bit states 0 and 1 by the two possible polarities σ = ±1 of a fluxon, corresponding to the sign of its flux ±Φ 0 and denoted as fluxon (+) and antifluxon (−). Switching between the degenerate bit states (polarity inversion) and other logic operations may be achieved in ballistic gates 20,21,35 , which are undriven and solely powered by the energy of the input fluxon(s). Previous ballistic reversible gates of RFL had been designed without internal state memory, implying that the operation of a multi-bit gate requires synchronous input bits. Although specialized store-andlaunch gates 21,22 have been designed for the purpose of synchronization (and routing), others have advocated for 'asynchronous' ballistic reversible gates 29 .
Asynchronous multi-bit gates have the advantage that the timing of the input bits no longer needs to be precise. They merely have to arrive with a minimum delay time between them to allow quiescence before the next arrival. Asynchronous ballistic gates require an internal state, by which an interaction between subsequent input bits is mediated. In order to generate output that depends on the input of a previous scattering, the internal state has to: be changeable by an input bit, and determine the output state of the ballistic scattering.
The storage cell of the ballistic shift register (BSR) provides exactly such functionality, in that it can store a bit state in form of a flux quantum with positive or negative flux orientation S = ±1. As we describe below, the stored state S may change during the scattering dynamics, depending on the input fluxon state σ. The scattering type (output fluxon state) in turn depends on the current value of S, but is independent of the input timing, regardless of what input ports are used.

A. Circuit
The most basic BSR is the 2-port circuit shown in Fig. 1(a). It consists of a storage cell, one LJJ each for in- Circuit schematic for a 1-input BSR, consisting of one input and one output LJJ (3 cells shown for each) connected by a circuit interface, which is made from three capacitance-shunted JJs, where two of these are left and right 'termination JJs' with (ĈJ ,Îc) and the third is the 'rail JJ' with (C B J , I B c ). An inductor Ls in parallel with the rail JJ is made to store one SFQ, where a clockwise (counterclockwise) circulating current Is corresponds to flux state S = 1 (S = −1) and rail phase φ B ≈ 2πS. The parameters of the interface and storage cell are set to enable energy-efficient forward-scattering from one LJJ to the other for all combinations of stored flux state S = ±1 and input flux state σ = ±1, for a range of input velocities. External circuitry coupled inductively to Ls may be optionally used to assist initialization of the BSR (loading), giving |S| = 1. (b) Operation table for 1-input BSR characterized by SWAP-operation between stored and moving flux states: (S , σ )=SWAP(S, σ). Schematical illustration of BSR operation is shown for third row of table, with S = −1, σ = 1, and resulting S = 1, σ = −1. The LJJ trilayer is illustrated using grey for superconductor and blue for tunneling barrier. (c) Operation table for the pioneering ADF flux shuttle 24 , which is based on the presence of an SFQ as the bit state. Schematic illustration of the shuttle operation is shown for third row of table, where a fluxon settles as a static SFQ in a storage cell due to damping (shown as shunt resistors), and is subsequently released as a fluxon by application of a bias current I b .
put and output, and a special interface cell between them. The LJJs form a part of the gate and also serve as fluxon in-and output channels. The side arms of the interface cell are formed by two JJs with parameters (Ĉ J ,Î c ). Each of them terminates one of the LJJs and thus they are referred to as 'termination JJs'. The upper rails of the LJJs are joined by a negligible inductance (on the upper side of the interface cell), while the lower rails are connected by the so-called 'rail JJ' (of the interface cell), with parameters (C B J , I B c ). The rail JJ is also part of the storage cell which is closed by a parallel inductor L s . Given suitable parameters (2πL s I B c /Φ 0 5), the storage cell can store one bit of information in form of a steady circulating current. A clockwise (counterclockwise) circulating current corresponds to a positive (negative) flux orientation S = 1 (S = −1), and rail-JJ phase φ B ≈ 2πS.
Similar to the 1-bit ballistic RFL gates, the NOT or ID, the interface of the BSR is designed to enable forwardscattering, starting from a fluxon entering on one LJJ to a possibly newly created fluxon exiting on the other LJJ. The ballistic gates require specific parameter values in the interface to achieve the operation. The ballistic scattering involves the temporary breaking of the fluxon at the gate interface and a short oscillation of an interface mode. In previous 1-bit ballistic RFL gates, i.e., the NOT and ID, the polarity of the exiting fluxon is determined by the polarity of the incoming fluxon alone. In contrast, the output bit of the BSR is also dependent on the stored bit state S. The ballistic scattering dynamics generates the regular operations of a shift register, summarized in the table of Fig. 1(b). One of the four possible operations of the BSR is sketched in Fig. 1(b). In comparison with the operation of the ADF flux shuttle 24,25 , Fig. 1(c), it uses no external drive power to advance the stored SFQ from the storage cell. Instead, the incoming bit state is swapped efficiently with the stored one in a reversible process.
We refer to the BSR of Fig. 1(a), where fluxons can arrive on only one input LJJ, as a 1-input BSR, to distinguish it from a BSR with separate write and read channels, cf. Fig. 5. The circuit dynamics of the 1-input BSR is described by the Lagrangian Herein, L l,r are the Lagrangian components of the left and right LJJ, respectively, and L I describes the interface which connects them. The JJs in the discrete LJJs have capacitance and critical current of (C J , I c ), and each unit cell of length a has the inductance L.
The characteristic time, length, speed and energy scales of the LJJ are set by the Josephson plasma frequency , the Swihart velocity c = ω J λ J , and the energy scale E 0 = I c Φ 0 λ J /(2πa) (A static fluxon in the LJJ has energy 8E 0 , cf. Eq. (10)). In our design the inductance in the interface cell is assumed to be negligible, as indicated in Fig. 1(a), and in this situation the phase of the rail JJ of the interface is not independent but fixed by where we introduce shorthand notations for the termination JJ phases in Eq. (3). With this approximation, the interface Lagrangian corresponding to Fig. 1(a) reads where the parameter f E quantifies an external flux f E Φ 0 applied to the storage cell, cf. Fig. 1(a). A finite f E may be useful during the initialization of the BSR, i.e. the initial loading of an SFQ into the storage cell, but it is not necessary in principle. During regular BSR operations, an SFQ is already stored and f E is set to zero. In this work we present results on: regular BSR operations (where f E = 0) and initialization results using f E = 0.

B. Steady states of the circuit (before input)
To analyze the bit-storage characteristics of the BSR we first study the steady states of the BSR circuit (in the absence of a moving fluxon). It is helpful to first compare the BSR to the earlier ballistic gate circuit without a storage cell. Schematically, in the limit of infinite storage cell inductance L s → ∞ the BSR circuit is equivalent to the circuit of the ID and NOT gates 20 . The steady states of Eq. (1) are then given by uniform phase fields in the left and right LJJ, φ (l) n = 2πk L and φ (r) n = 2πk R (k L,R ∈ Z), while the rail phase assumes the value φ B = 2π(k L −k R ). Herein, the integers k L,R label the 'vacuum' states (ground states) of the φ-periodic LJJ potential 36 . Similar to uncoupled LJJs, all configurations (k L , k R ) are degenerate here, and the dynamics are not dependent on their initial values. When a fluxon from the left LJJ is scattered forward without (with) polarity inversion it realizes an ID (NOT) gate; it transfers the system from a state with (k L , k R ) to the state with (k L +2πσ, k R ±2πσ). By the way, the dynamics of the NOT gate, but not the ID gate, will be used below for the BSR.
In the presence of finite L s in the BSRm the degeneracy of different configurations (k L , k R ) is lifted due to the contribution ∝ (φ L − φ R ) 2 /(2L s ) in the potential, cf. Eq. (4). Large values of the rail phase φ B = φ L − φ R (and of the vacuum level difference 2π(k L −k R ) to the left and right of the interface) become energetically inaccessible. At finite |k L −k R | > 0, while the LJJ phases far away from the interface are still confined to their respective vacuum levels 2πk L,R , the LJJ phases near the interface are perturbed. We therefore model the LJJ phases (in the absence of a fluxon) as bound states with evanescent fields of the form The flux state S in the storage cell is determined by the difference in configuration at the left and right side of the interface, Inserting Eq. (5) in the Lagrangian (1), the potential can be expressed, in the limit of small bound-state amplitudes, as Referenced from the interface, each LJJ contribution is reduced to an effective JJ and an effective inductance, where both are in parallel with the corresponding termination JJ (Î c ). In these expressions the inverse decay length µ of the bound state is not yet determined. However, we can estimate µ from the condition that the bound state fulfills the dispersion relation in the LJJ bulk, ω 2 bulk = ω 2 J + 2c 2 /a 2 (1 − cosh(aµ)). Being interested in steady states of the interface, we can set ω = 0 and obtain the estimate µ = a −1 cosh −1 1 + a 2 /(2λ 2 J ) . The potential shown in Fig. 2 is obtained from Eq. (6) by choosing the energy-minimizing configuration, . The resulting diamond-shaped domains are labeled in Fig. 2 by the locally minimizing (k L , k R ). For not too large φ B = φ L − φ R , the potential U S has a local minimum in each of these domains (k L , k R ), and these steady states correspond to a stored flux state States with a single stored flux quantum are found in the domains with |k L − k R | = 1, with the local minima at it follows that the bound-state amplitudes on the left and right sides of the interface are equal and opposite, During normal operation of the BSR, the parameters in the bound-state approximation, Eq. (5), which describes LJJ excitations localized at the interface as a function of the termination-JJ phases φL,R. The potential is 4π-periodic in the sum of the phases φL + φR at constant phase difference φL − φR, due to the combined 2π-periodicity in the two components. However, the potential has an approximate parabolic dependence on φ B = φL − φR due to energy storage in Ls. Each configuration (kL, kR) exists only locally in a diamond-shaped domain, and for φ B 4π, each diamond contains a well which supports a stored flux state S = kL−kR. Steady states in wells with S = ±1 (black points) have energy ES = 2.5E0 ≈ 2π 2 LλJ /(Lsa)S 2 E0. Additional equipotential lines are shown at ES + E fl , for fluxon energy E fl = 10E0, indicating the φL,R-range accessible for an incident fluxon with velocity v = 0.6c. The 4 trajectories (red, blue, orange, light blue points) show the phase evolution of the termination JJs, 0 (t), obtained from the full circuit simulation for incident fluxon and initially stored state S = ±1. Solid (dashed) arrows indicate the resulting transitions to another well of the potential, for σ = 1 (σ = −1). The flux state in the new well is S = ±S if S = ±σ. The system parameters are dimensioned such that the potential US allows these transition types, and also the transition from S = kL − kR = 0 to |S| = 1 for the initialization (SFQloading) of the BSR. Note that US assumes the LJJ fields of the bound-state form, Eq. (5), in the absence of a fluxon. The superimposed scattering trajectories are therefore not described by US alone. The BSR parameters and parameter ranges are given on the left side of Table I. |S| ≤ 1, where the bound-state amplitudes are small and the phase fields in the left and right LJJ are nearly uniform. For a single stored flux quantum S in the BSR, we can thus approximate (φ L , φ R ) in Eq. (5) as (2πk L , 2πk R ). From Eq. (5) it follows that the stored energy relative to the empty BSR (S = 0) is If the BSR is initialized with |S| ≤ 1, an incoming fluxon with velocity v and energy can transfer the BSR into a new stored flux state with energy E S ≤ E S + E fl (v). The equipotential lines in Fig. 2 indicate the corresponding φ L,R -range accessible from |S| = 1. Energetically, it is not possible to load a 2nd SFQ (|S| = 2) into the storage cell, whereas transitions to other states with |S| = 1 or S = 0 are energetically possible.
C. Fluxon scattering dynamics Figure 3 illustrates the BSR operation, where each of the four subfigures shows the circuit simulations for two consecutive input fluxons. In all four cases, the BSR is assumed to initially contain a stored flux quantum S = −1. This means that the circuit is initialized in a bound state of the form of Eq. (5), with (k L , k R ) = (0, 1) and corresponding steady state values of φ L,R . The incoming fluxon(s) are treated in simulation as additional contributions to the initial phase and voltage distribution in the left LJJ, far away from the interface. An input fluxon (antifluxon), which has positive (negative) polarity σ = 1(−1), is parametrized by the ideal phase dis-  Figure 3(a) shows at the earliest times, a first fluxon with polarity σ = +1 traveling in the left LJJ with nearly constant speed v 0 = 0.6c. As it reaches the interface, the fluxon breaks into two parts, i.e. its phaseand voltage-fields become discontinuous. In the process, the energy of the fluxon is coherently transferred to a localized excitation involving the left and right LJJs in form of time-dependent evanescent fields. The localized excitation lasts long enough for its own brief oscillation, and afterwards generates a large field profile in the right LJJ, which eventually moves as a free fluxon in the right LJJ, away from the influence of the interface. During the whole process, the phase φ B of the rail JJ changes monotonously from φ B ≈ −2π to ≈ 2π. This 4π-phase change indicates the simultaneous transfer of the input fluxon's (positive) SFQ-state σ = 1 into the storage cell and of the initially stored (negative) SFQ S = −1 out of the storage cell. Thusly after the scattering, the new orientation of the stored flux quantum is S = 1, and the output fluxon carries the negative SFQ-state, σ = −1, as indicated by the negative sign of the voltage peak. The fluxon scattering dynamics in this case are similar  Right panels show evolution of the rail-JJ phase φ B from initial state φ B ≈ 2πS. In cases where σ = −S, the fluxon scatters forward as an output fluxon with inverted polarity, σ = S, and the stored state after the scattering becomes S = σ. In the other cases, σ = S, the fluxon is simply transmitted with short delay, and the stored state remains unchanged. All cases fulfill (S , σ ) = SWAP(S, σ), thus generate the state map of a 1-bit shift register, cf. Fig. 1(b). The BSR parameters, as listed in Table I, are the same as in Fig. 2 and input fluxons enter with v0 = 0.6c.
to that of the fundamental (1-bit) NOT gate 20 (without a storage cell).
When the second input fluxon with σ = 1 arrives ( Fig. 3(a), ω J t ≈ 12), the input SFQ state now equals the stored SFQ state, S = 1. The resulting scattering dynamics at the interface therefore differs significantly from that of the preceding fluxon. The interface here acts mostly as a low potential barrier by which the fluxon is slowed down temporarily while retaining its fluxon identity, with unchanged polarity. During the fluxon transmission the rail JJ is only weakly excited away from φ B ≈ 2π, indicating that no significant flux transfer occurs. Accordingly, both the fluxon's state σ and the stored flux state S are unchanged in this process. While the result of the fluxon scattering is here the same as in the fundamental ballistic ID gate (the polarity of the outgoing fluxon is identical to that of the incoming one), the scattering dynamics is different: the fluxon here retains its topological identity throughout the process, whereas in the fundamental ID gate it breaks up into two partial fluxons at the interface and generates a large localized oscillation as a result (which has a longer duration compared with the temporary oscillation in the fundamental NOT gate). The difference of the transmission-type dynamics of the BSR compared with the dynamics of an actual ID-gate originates from the added term (φ B ) 2 /(2L s ) in the interface potential, Eq. (4). It limits the φ B -range accessible with the fluxon's initial energy E fl (see Fig. 2 and discussion in Sec. II B). As a result, the rail phase in the BSR cannot increase from an initial value φ B ≈ 2π by ∆φ B ≈ +4π. The transmission-type dynamics creates an advantage for the margins of the BSR (see Sec. II F) relative to the fundamental ID gate, which has somewhat sensitive margins in comparison with the fundamental NOT gate due to the longer resonant oscillation. In summary, the inductor L s enables bit storage, changes the dynamics relative to previous RFL gates, and improves operation margins compared to an earlier gate. Figure 3 demonstrates that the scattering dynamics results for all state pairs (S, σ) in a new state pair, which is related to the old one in the form of a SWAP-operation, (S , σ ) = SWAP(S, σ). The ballistic scattering dynamics in the BSR circuit thus generates the state map of a 1-bit shift register, Fig. 1(b). As described above, two different types of scattering dynamics are involved, and in both types the SWAP happens with almost ideal efficiency (cf. Sec. II F).
The BSR operations can be illustrated as inter-well transitions in the circuit potential U S , induced by the incoming fluxon. This is illustrated in Fig. 2 by the trajectories (φ L , φ R )(t) (data points), where φ L,R (t) are taken from the full circuit simulation. Note that the circuit potential shown in Fig. 2 assumes the LJJ fields have the form of a bound state, Eq. (5), but does not take into account the fluxon. For example, a fluxon with σ = 1 leads to a transition (red) from the initial state in the well with (k L , k R ) = (0, 1) to the well with (k L , k R ) = (1, 0), and this changes the stored flux state S = −1 → 1. In contrast, a fluxon with σ = −1 induces an S-preserving transition (blue), namely to the well with (k L , k R ) = (−1, 0), which is fully equivalent to the initial well. The underlying circuit dynamics for these two processes corresponds to the first fluxon scattering in Figs. 3(a) and (c), respectively. Equivalent dynamics are observed for an initial stored flux state S = 1, e.g. initially (k L , k R ) = (1, 0), if the polarity of the incoming fluxon is inverted at the same time. Thus, an incoming fluxon with σ = −1 (σ = 1) induces a transition that inverts (preserves) S, as shown by the orange (light blue) trajectories.
The dynamics shown in Fig. 3 illustrate the regular BSR operations, where initially a flux quantum is already stored in the storage cell. Without this initialization, the BSR will not perform all the intended reversible operations. To initialize, an SFQ can be loaded into the empty storage cell by sending in a fluxon which is stopped at

FIG. 4.
A 2-bit Serial-In-Serial-Out (SISO) shift register (a) and its dynamics (b-e) for a single input fluxon, σ = +1, and four different initial configurations of the two stored bits: (S1, S2) = (−1, −1), (−1, 1), (1, −1), and (1, 1). As in Fig. 3, the left panels show the JJ voltages Vn in the LJJs, where a fluxon (σ = 1) is seen as a blue track and an antifluxon (σ = −1) is seen as an orange track. The two BSR are located at xn = 0 and at xn = (N + 2)a = 40a ∼ 15λJ , respectively, though smaller distances are also possible. The right panels show the evolution of the rail-JJ phases φ Bi of the two BSR (i = 1, 2). The numbers printed in each of the left panels are the relative speed v1/v0 (v2/v1) after passing through the first (second) BSR. The BSR parameters are the same as in Fig. 3.
the interface such that its flux is transferred to the storage cell. We find that it is possible to load an SFQ using no external flux (f E = 0). However, the initialization fluxon could be back reflected if too slow. In practice, an external flux (f E = 0) would likely be applied to the storage cell during loading, to prevent such reflection.

D. Consecutively arranged shift registers
A multi-bit shift register can be constructed from consecutively arranged BSRs, constituting a Serial-In-Serial-Out (SISO) register. As an example, Fig. 4 shows a 2-bit serial shift register and its dynamics. The two bits are stored in one of four different configurations (S 1 , S 2 ) = (−1, −1), (−1, 1), (1, −1), and (1, 1). Subfigures 4(b-e) show the gate dynamics for each of these initial configurations and a single input fluxon, here with σ = +1. The two BSR are located at x = 0 and x ≈ 15λ J (separated by N + 2 = 40 LJJ cells). As in Fig. 3, the stored flux quanta can be inferred from the values of the rail-JJ phases φ B1 and φ B2 in the right panels of each subfigure, using that φ Bi ≈ 2πS i (i = 1, 2). The operation of the entire 2-bit shift register is powered by the energy of the input fluxon, which looses only a fraction of its kinetic energy in each of the scatterings. The numbers printed in the left panels are the output-to-input velocity ratios after each scattering, v 1 /v 0 and v 2 /v 1 , where again we use initial velocity v 0 = 0.6c. The lowest velocity ratio (0.91) corresponds to 95% energy conservation according to Eq. (10).
For each scattering type (NOT and transmission), both stages of the 2-bit shift register give approximately the same velocity ratios (≈ 0.91 for NOT, ≈ 0.95 for transmission), corresponding to those of a 1-bit BSR (see Sec. II F). The observed small variability in forwardscattering efficiency at the 1st and 2nd BSR (e.g. between 0.95 and 0.96 for the two consecutive transmissions in panel (e)) can be attributed to the presence of fluctuations in the connecting LJJ and at the 2nd BSR prior to the fluxon arrival there. These fluctuations are emitted from the first BSR during the first scattering event.

E. 2-input shift register
The 1-bit BSR, shown in Fig 1(a), has one input LJJ and one output LJJ. Together they form a single channel called a bit line for the forward-scattering fluxon. This 1-input 1-bit BSR may be generalized to a 2-input 1-bit BSR, where a storage cell is shared between two such scattering channels, as shown in Fig. 5. We have verified in simulations that the 2-input structure also acts as an energy-efficient 1-bit BSR, using the same interface parameters as for the 1-input 1-bit BSR, cf. Table I. For the operation of this BSR, it is irrelevant which of the two input LJJs a fluxon is sent in on -the dynamics for both input cases is equivalent and it is qualitatively equivalent to the dynamics of the 1-input BSR. In the 2-input device the role of the rail-JJ phase φ B of the 1-input BSR The inductance of the storage cell is Ls and the interface cells of both scattering channels are symmetric. Efficient BSR operation takes place with parameter values given in Fig. 3, and operation margins given in the right side of Table I. is taken over by the phase difference of the two rail JJs, φ B → φ B − φ C . Motivated by the small difference in parameter margins between the 1-input and the 2-input version of the BSR, cf. Table I, we expect that a version with many inputs would also operate. This implies that a stored bit of information could be routed to one of many outputs.
Despite the shared storage cell there is no strong dynamic coupling between the upper and lower part of the gate. By that we mean that even during the NOT-type scattering an input fluxon on the upper (lower) LJJ induces a large phase change of 4π only in the adjacent φ B (φ C ), and a relatively small temporary excitation in φ C (φ B ), resulting in an output fluxon only on the upper (lower) output LJJ. A similar observation holds for the transmission-type scattering, however in this case no significant phase change takes place even in the adjacent rail JJ. With this property, the 2-input BSR may be used as an SFQ memory with separate write and read lines.

F. Margins
An optimal set of circuit parameters for an energyefficient BSR are given by the first and second columns in Table I. These parameters optimize the elastic nature of both scattering types (NOT and transmission) of the BSR operation, such that the dominant fraction of the input fluxon's energy is conserved in the forwardscattered fluxon. The resulting output-to-input velocity ratio v f /v 0 of the optimized dynamics amounts to 0.91 and 0.95, respectively. For an input fluxon with v 0 = 0.6c the average energy efficiency of the BSR therefore is 96% according to Eq. (10). Figure 6 shows the output-toinput velocity ratio under variations of different parameters. Setting the minimum ratio v f /v 0 to 0.6 (corresponding to an energy efficiency E fl (v f )/E fl (v 0 ) ≥ 0.86 for initial v 0 = 0.6c), we find the operation margins for Ic/Ic 1.6 -90% +16% 106% -78% +20% 98% Ls/L 20 -37% +130% 167% -35% +124% 159% TABLE I. Interface parameters and margins for 1-input BSR, Fig. 1(a), and 2-input BSR, Fig 5. Margins are defined by a required output-to-input velocity ratio v f /v0 ≥ 0.6, cf. Fig. 6, corresponding to an energy efficiency E fl (v f )/E fl (v0) ≥ 0.86 for initial v0 = 0.6c. This condition is met by all regular BSR operations, i.e. for any combinations of S = ±1 and σ = ±1.
In case of the 2-input BSR, it is also independent of the choice of input LJJ. In both BSR types the parameters allow for a velocity retention up to v f /v0 = 0.91, cf. Fig. 6.  Table I. the BSR, as shown in the next three columns in Table I. The current limiting factor of the BSR design, as shown in Fig. 6(f), is the somewhat restricted range of input velocities for the transmission-type BSR dynamics. In this case, the interface's potential barriers which are proportional to I B c andÎ c impose a sharp lower operation limit of v 0 ≥ 0.53c, though other parameters can be used to reduce this lower velocity limit. Of the parameter margins, I B c is the smallest with a range of 47%. The margins of the 2-input BSR, shown in the last three columns of Table I, are almost the same as those of the 1-input BSR. This is consistent with our observation earlier, that the dynamics on each (upper or lower) bit line is only very weakly affected by the presence of the other bit line. As long as there is no excitation on the extra bit line, it mainly acts as an inductance added to the storage loop. Therefore, we expect that a BSR gate with more bit lines (an N-input BSR) will operate similarly well.

G. Discussion
Superconducting memory has been developed for the irreversible types: RSFQ 37-39 , RQL 40 , and AQFP 41 , where an all-superconducting memory achieved a density of up to 1 Mb/cm 2 , Ref. 42, and the incorporation of magnetic elements provides a route to higher density without further advancements in lithography 43 . The shift register, being more relevant here, is a fast memory placed onchip with the processing components of the logic, related to "registers" and cache. It has been demonstrated in RSFQ 44 , RQL 5 , and AQFP 45 . It has also been adapted for memory arrays in processors 4,46 . In contrast to these schemes, the BSR uses an SFQ without external bias (or π-junctions). Also unlike non-destructive readout, the readout of the BSR always moves the stored bit. As we have shown, the read and write operation is accomplished by ballistic data input. Based on our results for the SISO and parallel 2-or N-input shift register, we expect that it should be extensible into many-bit memory arrays. The 2-bit SISO shift register, made from two 1-bit BSR, shows that ballistic gates can be performed in sequence without external power. This usage should apply equally well to the 2-bit SR. These sequenced structures have a logical depth of two without external power, which provides a useful feature generally in the context of sequenced logic functions (see e.g., Ref. 47).
Logic gates generally have different execution times (delays) 48 , and in SFQ logic, delays and jitter lead to requirements for clock and bit synchronization 26-28 and sometimes bit arbitration 49 . However, some progress has been made recently in this area with the introduction of a second time-constant within an AND and OR gate to conveniently define a timing window for receiving the SFQ (bit=1 state) 6 . Additionally, our asynchronous gates provide a positive development for SFQ logic because the timing requirement basically reduces to a requirement of bit order.
When setting the gate energy efficiency to ≥ 86%, we obtain the wide parameter margins shown in Table I. It follows that the energy cost per operation is E op < 0.14E B , where E B is the energy of the input bit (which is independent of its bit state). For the assumed input velocity of the fluxon v 0 /c = 0.6 this bit energy is E B = 10E 0 , compared with the rest energy 8E 0 of a stationary bit (cf. Eq. (10)). Herein, the energy scale E 0 = I c Φ 0 λ J /(2πa) depends on the LJJ fabrication. The BSR can be fabricated from digital foundry materials, such as Nb superconductor with an AlOx barrier, similar to previous RFL gates 35 . For example, in an LJJ built with the discreteness used in our simulations, a/λ J = 2πI c L/Φ 0 = 1/ √ 7, and with I c = 3 · 10 −6 A, an energy cost of < 3.7 zJ/op would result. When experimentally optimized and realized, this could compare favorably with state-of-the-art logic efficiency results (cf. Ref. 50). With other materials, one could in principle lower E B closer to k B T to achieve an even lower energy cost.
Although it is beyond the scope of this work to specify a full architecture for RFL, it is obvious that the BSRs could be tested by a train of fluxons traveling with some interval between them. For example in the simulation data of Fig. 3, the input fluxons arrive with a time interval of T = 8/ν J for clarity (smaller intervals are possible). The energy cost estimated above from the circuit simulation includes loss due to plasma waves. At very high Josephson frequencies comparable to the superconducting gap, additional loss due to quasiparticles is expected and would therefore set an upper limit to the Joseph-son frequency ν J and the resulting operation speed. Assuming circuits are made with a Joshephson frequency ν J = 44 GHz and the above-mentioned time interval is used between bits, we calculate a real time interval of 182 ps/op. From the rate (5.5 GHz) and the above energy calculation, the maximum power loss per bit (during operations) is estimated as 20 pW. Our gates allow a combined benefit of asynchronous timing and energy efficiency. With these modest assumptions, the maximum energy delay product (EDP) for the shift register is less than 6.6 · 10 −31 Js = 10 3 h. Clocking will cost energy as well, and will be addressed in future work. However, we note that an EDP on the order of 1 · 10 −22 Js may be achieved in a one-stage clocked RSFQ architecture 28 . In the future we can target much lower EDP due to the lower energy costs in reversible logic (see, e.g., Ref. 21 for a clock-triggered gate).

III. COLLECTIVE COORDINATE ANALYSIS
For solitons and other collective excitations of a manybody system, the collective coordinate (CC) method is a powerful way to reduce the many degrees of freedom to a few essential coordinates 36 . We have previously developed such a CC model for the fundamental (1-bit) RFL gates 20 . Here we extend the model to the BSR, in particular the 1-input BSR of Fig. 1. To this end we parametrize the LJJ fields left and right of the interface (at x = 0) with the ansatz Each (left and right) field consists of a linear superposition of a fluxon and its mirror antifluxon, where φ (σ,X) is the phase field of a fluxon of polarity σ which we model as a kink equivalent to the soliton solution of the LJJ field 36 , φ (σ,X) (x, t) = 4 arctan e −σ(x−X)/W . Herein, the time-dependent fluxon positions X L,R (t) serve as the dynamical coordinates of the model, while the fluxon width W is taken to be constant in a so-called adiabatic approximation 51 . As in Sec. II B the integers k L,R describe the vacuum levels of the left and right phase fields before the arrival of the fluxon. The resulting rail-JJ phase φ B = φ L − φ R = 2π(k L − k R ) corresponds to an initial orientation S = (k L − k R ) of the stored flux quantum. In comparison, the CC model developed for 1-bit RFL gates 20 is based on Eq. (11) with the special case k L − k R = 0.
The ansatz (11) neglects that for S = 0 the LJJ fields may deviate in the vicinity of the interface from the vacuum levels, as modelled by the bound states, Eq. (5). However, considering the relatively small bound-state amplitudes of the BSR with |S| = 1, this approximation seems justified.

A. CC Model Parametrization and Potential
Examples for the parametrization of Eq. (11) are shown in the insets of Fig. 7 for different points in coordinate space (X L , X R ). Subfigures (a-c) represent the different configurations (k L , k R ) = (0, 0), (1, 0), and (0, 1), respectively, for fluxon polarity σ = 1. A fluxon (σ = 1) initially situated in the left LJJ far away from the interface at X/λ J −1, is approximated by Eq. (11) with the coordinate X L = X, while X R = 0 describes the absence of excitations in the right LJJ (see left-most inset in all panels (a-c)). For this initial state, Eq. (11) forms a step at the interface (x = 0) between 2πk L to the left and 2πk R to the right, corresponding to the initially stored flux state S = (k L − k R ). With k L,R and σ set by the initial state, Eq. (11) fulfills the boundary conditions, φ(x → −∞) = 2πk L + 2πσ and φ(x → ∞) = 2πk R , for any finite X L,R . Under these boundary conditions, four different asymptotic single-fluxon states are permitted and these can be parametrized through suitable choice of X L,R : a fluxon (antifluxon) in the left LJJ is parametrized by X L < 0 (X L > 0) together with X R = 0 and a fluxon (antifluxon) in the right LJJ is parametrized by X L = 0 together with X R < 0 (X R > 0). In the center of the coordinate space, (X L , X R ) = (0, 0), the phase distribution forms a step between 2π(k L + σ) to the left and 2πk R to the right of the interface, where φ B = 2π(k L − k R + σ). At points near (X L , X R ) ≈ (0, 0), the step is modified by the possible excitations near the interface, see e.g. the inset in bottom right corner of Fig. 7(c). In the corners of the configuration space where (|X L | 1, |X R | 1), Eq. (11) describes unavailable (high-energy) two-fluxon states (not shown).
Using Eq. (11) we can derive the collective coordinate model for the BSR. This derivation is discussed in detail in Appendix A, while here we simply summarize the results. After inserting Eq. (11) into the system Lagrangian, Eq. (1) is simplified to where U (X L , X R ) is the dimensionless CC potential, and the mass matrix M is composed of the coordinatedependent, dimensionless elements M ii = m i (X i ) and M i,j =i = m LR (X L , X R ) (i, j = L, R). The CC potential U , masses m i and mass coupling m LR are given in Eqs. (A7), (A5) and (A6), respectively. Compared with the CC model of the 1-bit RFL gates 20 , an additional term contributes to the CC potential U , cf. Eq. (A7), which stems from the shunt current through the inductor L s . The diagonal elements m i of the mass matrix M vary with X i near the interface, but asymptotically (|X i | 0 39 λ J ) approach a constant value, m i = 8λ J /W . The mass coupling m LR is exponentially suppressed far away from the interface, but is finite near it. It is proportional to the rail-JJ capacitance C B J , and this explains the important role of C B J for the forward-scattering of a fluxon from one LJJ to another in many gates. In the fundamental (NOT and ID) RFL gates, mass coupling is the dominant coupling mechanism between the LJJs, whereas coupling generated by the potential is negligible since the potential gradient always acts perpendicular to the coordinate axes, ∂U/∂X i | Xi=0 = 0. Relative to the fundmental RFL gates, the BSR has an added contribution u s in the CC potential U which can generate a much stronger coupling between X L and X R , depending on the configuration (k L , k R ).
The CC potential U is shown in Fig. 7 for the BSR parameters of table I, σ = 1, and three different configurations (k L , k R ). We emphasize that U depends parametrically on parameters of the initial state, namely on the initially stored SFQ, S = k L − k R , and on the polarity σ of the incoming fluxon. Specifically, the dependence enters in form of the product σ · S, as can be seen from Eq. (13) for the case of zero external flux through the storage cell, f E = 0. All other contributions to the CC potential, U 0 , u 1 , and u 2 in Eq. (A7), are independent of both σ and S. Note that the product σ · S preserves the circuit's invariance under phase-inversion (σ → −σ and S → −S), which would only be broken in presence of finite f E .
Most contributions to the CC potential, U 0 , u 1 , and u 2 in Eq. (A7), have mirror symmetry about the line X R = −X L , whereas u s has this symmetry only for σ(k L − k R ) = −1, as can be seen from Eq. (13) for f E = 0. In Fig. 7 the mirror symmetry is thus seen only in panel (c), where σ(k L − k R ) = −1, while in the other cases it is broken. The asymmetry is particularly strong for σ(k L − k R ) = +1, panel (b).
A fluxon initially at position X −λ J , moving with velocity v 0 , is parametrized by (X L , X R ) = (X, 0), (Ẋ L ,Ẋ R ) = (v 0 , 0), and the related fluxon width W/λ J = 1 − v 2 0 /c 2 . For these initial conditions, the initial energy of the system is found from Eq. (12) to be E init = E S + E fl (v 0 ). Herein, E fl (v 0 ) is the initial fluxon energy, Eq. (10), and E S is the energy of the initially stored flux quantum S, as given in Eq. (9). The coordinate space accessible during free evolution with energy E init is indicated by the corresponding equipotential lines (gray) in Figs. 7(a-c). In Fig. 7(c) this space consists of a central well which connects four asymptotic 'scattering valleys'. All of these correspond to a single fluxon, but differ by its polarity or its position in either the left or right LJJ, cf. description above. In Figs. 7(a,b), only two of these valleys are connected as a result of the potential's asymmetry, namely the fluxon's input valley (X L < 0, X R ≈ 0), with the valley (X L ≈ 0, X R < 0) that corresponds to a forward-scattered fluxon.
The Lagrangian, Eq. (12), generates the coupled equa-tions of motion, which describe the free dynamics of the coordinates X L,R for fixed initial values of S and σ. Recall that in our CC model, Eq. (11), S and σ are mere parameters determined by the initial state. However, as will become clearer in the discussion below, the corresponding values S and σ after the scattering can also be deduced from the asymptotic states of the evolution.

B. CC Model Results
From Eq. (14) we obtain the CC trajectories (X L , X R )(t) shown in Figs. 7(a-c) (red lines). We also compare the CC trajectories with 'simulated' trajectories which are obtained by fitting the phases φ l,r n (t) of the full circuit simulations to Eq. (11) (blue markers). As Fig. 7 demonstrates, there is generally very good qualitative and quantitative agreement with the CC model trajectory.
Next we describe how an empty BSR circuit is loaded with an SFQ such that it is initialized for regular BSR operation. In Fig. 7(a) the trajectory of the incoming fluxon enters the central potential well where it bounces multiple times. Since no damping has been included in the CC dynamics, Eq. (14), the trajectory may eventually exit the well, corresponding to a fluxon emitted from the interface into the left or right LJJ (insets). In the circuit simulations, however, even though no resistances are included, the generation of plasma waves at the interface effectively constitutes a weak damping mechanism which prevents later escape from the interface. For the coordinates trapped near the center point (X L , X R ) ≈ (0, 0), the phase distribution is close to a step profile (inset pointing to center of coordinate space), whereas the initial fluxon profile has vanished. From a comparison with the initial state (inset pointing to left side of coordinate space), where no flux was stored in the BSR (S = 0), it is clear that a flux quantum has now been added to the storage cell, i.e., S = 1 = S + σ. While Fig. 7(a) shows the dynamics for a high-energy fluxon (Ẋ L (0) = v 0 = 0.6c) in absence of an external flux f E through the storage cell, the loading process can be improved by using a low-energy fluxon, to decrease the amount of energy that must be lost to capture the fluxon, and f E = 0, to lower the interface potential that causes back reflection. Figure 7(b) shows results for the initial state S = 1. Here the central well of U is separated by a potential barrier from the input valley. The trajectory is shown to follow along the curved potential into the scattering valley, which corresponds to a fluxon in the right LJJ, while S remains unaffected (inset). This process thus corresponds to the transmission of a fluxon without topological change -the initial phase difference of 2π between the left and right LJJ is therefore roughly maintained during the scattering. In comparison, the dynamics of an ID gate is more complicated (as well as longer in duration), strongly relying on mass-coupling forces (cf. Fig. 4(a) in Ref. 20). Figure 7(c) shows results for the BSR initially in the state S = −1. Here the CC potential resembles that of a fundamental 1-bit gates (cf. Fig. 4(a) in Ref. 20). The resulting CC dynamics is similar to the NOT fundamental gate dynamics (cf. Fig. 7(c1) in Ref. 20), and can be explained by the combined effect of the strong mass-coupling (large C B J ) together with the forces from the potential (I B c , L s ) and the mass-gradients (C B J ,Ĉ J ). The resulting state after the scattering corresponds to a forward-scattered antifluxon, while the stored flux has been inverted, S = σ = −S (inset).
As these examples show, the CC model -though heavily simplifying the many-JJ circuit to a reduced system with two degrees of freedom -describes the fluxon scattering in the BSR accurately. Furthermore, it is a good tool to interpret and predict fluxon dynamics at circuit interfaces. With the help of the CC model, we were able to understand how the product σ·S, which represents the relative polarity of moving and stored bit states, changes the potential landscape. This in turn changes the scattering dynamics, as we described for the three relevant cases (initialization and the two distinct BSR gate operations).

IV. CONCLUSION
Reversible logic may progress digital computing generally because it allows great improvements in computing efficiency at the gate level. In contrast, end-of-theroadmap CMOS will have orders of magnitude higher energy cost per bit switching. The type of reversible logic which we study here (RFL) is ballistic. By introducing asynchronous ballistic gates in this work, we expect greater practicality in our reversible logic since the timing requirements are reduced.
The ADF (Anderson, Dynes, and Fulton) flux shuttle provided a pioneering design for a shift register prior to the start of SFQ logic. That logic is thermodynamically irreversible with the bit's energy dissipated during every logic operation. In contrast to the ADF shuttle, which has bits encoded by SFQ presence, our RFL ballistic gates conditionally invert fluxon polarity, where the fluxon polarity encodes the bit state. In this work we introduce BSRs (Ballistic Shift Registers) which add the feature of memory to previous ballistic multi-port gates. The BSRs rely only on ballistic scattering dynamics between the input fluxon and stored SFQ. Here the gate dynamics fall into two cases which consist of the resonant NOT case, generally used in RFL, and a simpler transmission case.
We have performed circuit simulations of a 1-input BSR, as well as a shift register composed of two 1-input BSR gates in sequence. In another design we introduced a 2-input BSR which can be used as a register with separate write and read ports or alternatively as a device to shift the bit state between different bit lines. Furthermore, we discuss how this may be helpful for a registerbased memory.
Since the ballistic scattering depends on the stored bit state (unlike previous RFL gates), the 1-input and 2input BSR constitute the first set of asynchronous reversible logic gates appropriate for feed forward computing. The former (1-input) gate is shown to allow the execution of two in sequence without external power. The latter gate allows more bit lines to be added. We discussed how this is related to logical depth and timing requirements.
Most importantly technically, perhaps, is that the BSR has wide process margins, where all parameter margins are above 46% when the energy efficiency is set to 86%, for example. This is far above the variation in today's standard fabrication processes such that BSRs can be tested.
In addition to full circuit simulations, we have modelled the BSR dynamics by a collective coordinate model which reduces the many-JJ degrees of freedom to only two coordinates. With the help of this model, the statedependent scattering dynamics can be understood from effective potentials in fluxon coordinate space -the BSR scattering potentials are dependent on the initial fluxon and SFQ states.
All SFQ logic types switch in a time equal or greater than the natural oscillation period of the Josephson junctions. Our logic is a fast reversible logic type in that it is designed to switch in only a few Josephson periods, as opposed to the speed-constraint of adiabatically powered reversible logic. Consecutive BSR operations are shown to be possible in less than 8 Josephson periods. We do not currently see the need for an adiabatic clock in contrast to other reversible logic families and this helps enable logic at high speed. Thus, we are optimistic that our ballistic logic may enable high-throughput high-efficiency computation with unpowered gate sequences.