{'fraction_non_alphanumeric': 0.02904162633107454, 'fraction_numerical': 0.0, 'mean_word_length': 5.08235294117647, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Enhancing the Utilization of Dot-Product Engines in Deep Learning Accelerators

In the last couple of years, the goal of deploying Deep Neural Networks (DNNs) in the embedded domain has led to the development of several dedicated DNN Hardware Accelerators (HWAs), many of which rely on a Dot-Product Engine (DPE)-based architecture. A DPE is a hardware block that receives two input vectors of the same size and produces one scalar value. Nevertheless, when the actual input vector does not match the DPEs native input-size, the DPE becomes underutilized. This is particularly observed for Convolutional Neural Networks (CNNs). In this article, we introduce kernel linearization, a technique to mitigate the underutilization of DPE-based HWA for DNNs. To demonstrate the benefits of this method, we implemented AEXelerator, a DPE-based HWA prototyped on FPGA and validated using automotive relevant DNNs. Our evaluation shows that our architecture achieves a high DPE utilization even in the presence of large vector-size mismatches.