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A new functional fault model for FPGA application-oriented testing

The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates that the faults affecting the bit cells of the look-up tables (LUTs) are not redundant, although they store constant values. We demonstrate that these faults cannot be neglected and that the fault model corresponding to modifying the content of each LUT memory cell must be considered in order to cover the full range of possible faults. In order to evaluate the fault coverage of the proposed fault model, a set of circuits mapped on a Xilinx Virtex 300 FPGA have been considered. Test sequences generated by a gate-level commercial ATPG and an academic RT-level one have been fault simulated on these benchmark circuits. The obtained figures show that a high percentage of faults affecting the LUT bit cells are undetected, thus suggesting that suitable ATPG algorithms adopting the new fault model are required.