{'fraction_non_alphanumeric': 0.020585048754062838, 'fraction_numerical': 0.0065005417118093175, 'mean_word_length': 4.5, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Directions for silicon technology as we approach the end of CMOS scaling

CMOS at the 45 nm node has been in production for a couple of years now, and 32 nm CMOS is making its way into leading-edge products. If everything goes according to plan, CMOS at the 11 nm node should be in production in less than ten years from now. However, every technology has its limits and CMOS is no exception. While there will be billions of CMOS devices on a chip, and “mobility engineering” will continue to enable ever faster CMOS devices, band-to-band tunneling will push up the standby currents and cap the speed of any transistor requiring low standby power dissipation. At the same time, the total power dissipation, at the chip level as well as at the system level, is severely limiting the realizable speed from these CMOS devices. More innovative approaches will be required to meet the expected improvement in system performance.