SOTB process is proprietary transistor technology from Renesas based on SOI (Silicon on Insulator) wafers.

SOTB process technology can realize extreme reduction of both active and standby current, which are normally under a tradeoff relationship. SOTB has the low leakage benefits of larger geometry node size, with the high-performance and low active current benefits of smaller silicon geometries and shown here. This makes SOTB-based products well suited for applications requiring long battery life, or no batteries at all.

SOTB Process Target

SOTB Transistor Bulk CMOS Transistor (for comparison)

A thin insulating oxide film (BOX, buried oxide) is deposited on top of the base silicon substrate. Next, a very thin silicon layer with no impurities is deposited on top of the BOX insulator layer to form dopantless channel transistor under the gate, that reduces threshold voltage variance, and thus enables very low operating voltage. The net effect of the BOX insulating layer and the dopantless channel is high performance, low-voltage operation with very low leakage current, and very low operational current. To further optimize performance while reducing leakage during standby, a bias voltage may be applied to the base silicon substrate underneath the BOX insulator layer.

Hybrid SOTB and BULK Structure

SOC designers can mix the use of SOTB and standard CMOS bulk transistors as needed to optimize performance, efficiency, and adapt to existing IP designs as needed. Examples of using bulk transistors: I/O ports, charge pumps, and specific analog functions.

Hybrid SOTB and BULK Structure