VHDL Tutorial

Peter J. Ashenden
1 comment

The purpose of this tutorial is to describe the modeling language VHDL. VHDL includes facilities for describing logical structure and function of digital systems at a number of levels of abstraction, from system level down to the gate level. It is intended, among other things, as a modeling language for specification and simulation. We can also use it for hardware synthesis if we restrict ourselves to a subset that can be automatically translated into hardware.


VHDL can be also used combined with C code using the VHPI. I have made simple demo fro creating random numbers.
Here is a short description of the work:
"...Recently I have improved the random generation using c code and VHPI. First some links , which show simple examples of c code interface for GHDL. VHDL
--small changes during average calculation (0..3)
gen_rand := std_logic_vector(
to_unsigned(g_rand_int_c(sim_seed, 4), 4)
c code
int g_rand_int_c(int seed, int Pmax) {
int rnum;

if(srand_f) {
srand( (unsigned)seed);
srand_f = 0;
rnum = rand() % Pmax;
return rnum;
... "
4 years ago
Sorry, you need javascript enabled to post any comments.
Sorry, you need javascript enabled to post any comments.