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Honored Contributor I

DE0 Cyclone V GPIO 1-Z switching, RN series

Hello, I am currently working with DE0 cyclone V now. 

I am trying to make a circuit that constantly switches the GPIO pins between 1-Z ( high impedance state) at a specified frequency (ex: 900 kHz). 

But when I measure the voltage signals between GPIO pins and ground by an oscilloscope, it shows that even when GPIO pins are Z state, there are still some voltage. 

Looking at the schematics, I can see that the GPIO pins are not directly driven by the FPGA. There are a RN series between GPIO pins and FPGA pins, as illustrated in the following photo: 



I tried to look it up but I couldn't find what is that RN series, and what are they used for ? 

And I also see that GPIO pins are driven by a source voltage through a pair of schottky diode ( as as illustrated in the following photo:  


I don't get why they need to drive the GPIO pins by another source of voltage. Then when the signal comes from the FPGA, how can it pull down the value of GPIO pins to 0 ? 


Does anyone have the schematics of the above RN series and the schottky diode ( array ? 

Thank you so much!
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Honored Contributor I

It sounds like you're expecting to see 0V when the I/O pin is tri-state. This is a poor assumption. 


The RN (resistor network) is likely to be around 20-25 ohms and combined with the schottky diode these protect the FPGA I/O - to an extent. Typically, in normal operation, you can ignore these. However, when all you're connecting to the I/O pin is a scope probe, the protection circuit comes into play - along with the FPGA itself. All the small currents associated with each of these - the probe, diodes, FPGA - will contribute to the voltage you're seeing on the oscilloscope. 


Probe the pin with a 10kOhm-50kOhm resistor connected between your scope probe and ground. Do the same with the resistor connected between your probe and 3.3V (assuming that's the voltage of the I/O bank in question). See what behaviour you get.