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An effective implementation scheme for TSV leakage testing

Leakage test is necessary for the through silicon vias (TSVs) in the 3-D integrated circuits (ICs). There are still some challenges on narrow test range for the most existing leakage test methods. In this paper, an effective scheme by utilizing the Enhanced Launch and Capture Clock Generation (Enhanced LCCG) structure is implemented to enhance the capability of TSV leakage testing. In this scheme, expanded leakage test range is obtained by using the series structure of Enhanced LCCG. The leakage fault test results are more precise than that of the traditional leakage test method. Experimental results are showed to prove the feasibility of the scheme.