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A 1.33 Gsps 5-bit 2 stage pipelined flash analog to digital converter for UWB targeting 8 stage time interleaving architecture

Current trends in wireless communications emphasize the development of UWB (Ultra-Wide Band with bandwidths greater than 500 MHz or 20% of center frequency) radios. As the size of the digital part scales down, more and more components are being pushed into the digital domain. As a consequence of this, in receiver architectures, the ADCs are being pushed more towards the antenna in the front end. This places a lot of constraints on ADCs such as high speed, high resolution, high integrability onto ICs and low power. Time interleaved architectures are used to provide high speed. ADCs that work at speeds up to 40 Gsps have been reported in literature but on non-CMOS technology or based on photonics, but they consume high power and operate at higher voltages and are less integrable. The goal of the present work is to implement a high speed ADC with low voltage supply and low power consumption. The paper uses flash ADC architecture aimed at time interleaving in standard 180 nm CMOS process. The current work shows the implementation of a 5 bit, 1.33 Gsps 2 stage pipelined flash with an input frequency bandwidth of 200 MHz and designed for time interleaved architecture having a clock duty cycle of 12.5% and working on a 1.8 V power supply. This allows interleaving up to 8 similar stages, thus providing either a 8 Gsps ADC with 200 MHz input frequency range or a 1 Gsps ADC with 1.6 GHz input frequency range. The ADC discussed in this paper will be a single ADC in the 8 stage ADC system.