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Stress mitigation of 3D-stacking/packaging induced stresses

Where the introduction of 3D stacked ICs offers opportunities for new and faster applications, the use of ultra-thin stacked Si dies leads to new reliability challenges. One such challenge is to cope with the thermo-mechanical stresses induced by mismatches in the Coefficient of Thermal Expansion between the different materials used for stacking and packaging such as Si, copper, overmoulds, laminates and underfills, amongst others. These stresses are a key-concern for today's 2D-technologies and are even more severe for 2.5/3D-stacking and -packaging technologies with high interconnect densities.