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Design and Analysis of Low Power, High Speed, Leakage Control Comparator using 180nm Technology For A/D Converters

This paper presents design and analysis of a low power, high-speed comaprator for high-end devices like analog to digital converters. The proposed design focuses on limiting the leakage power which is the major contributor to the overall power dissipation of the comparator. The proposed design limits the leakage power of the overall circuit by interpolating two pairs of leakage control transistor sets between pull-up and pull-down networks in a dynamic single tail comparator. Simulations of the proposed comparator are performed using Cadence Virtuoso Software using 180nm technology. The simulation results show that the delay of the proposed design reduced by a factor of 0.87 and the overall power consumption is 1.68x lower when compared with the conventional dynamic single tail comparator at an operating frequency of 250 MHz.