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The effect of emitter current crowding on CMOS latchup characteristics

Both static latchup and intrinsic p-n-p bipolar characteristics are compared and analyzed for various p-n-p-n test structures using a modern p-epi on p+CMOS technology. By varying the epi-layer thickness and the lateral spacing between the p+injector and the n-well boundary, it is shown that high-level injection and current crowding dominate the carrier transport inside the well under latchup conditions, especially when a shallow epi layer is used. As a result, a guideline for latchup-related design rules, applicable for large devices, which combines good latchup protection and a negligible penalty in area of performance, is proposed and discussed.