{'fraction_non_alphanumeric': 0.022354694485842028, 'fraction_numerical': 0.0, 'mean_word_length': 5.0, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
An automatic and practical flow for clock tree construction in physical design

High performance chip design is always a hot topic in integrated circuit (IC) field. Clock design plays a critical role in improving chip performance. In this paper, we propose an automatic and practical flow for clock tree design, which is a popular clock structure. Based on deferred-merge embedding (DME) algorithm, we integrate buffer insertion and obstacle processing into the layout design. The clock skew is guaranteed to be small in the presence of correlated process variations. Our work also combines the algorithm results and SPICE-driven simulation results into a practical flow.