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Design, implementation and analysis of 4-bit look ahead carry adder using adiabatic and stacking techniques

For many years, designing of high speed low power circuits with CMOS technology was a difficult challenge for research community. There are various levels at which design problem related to low power and increased demand can be addressed; these levels are — software level, architecture level, algorithm level, circuit level and process technology level. In this paper we have designed a 4-bit Look Ahead Carry Adder using CMOS technology. The objective of this paper is to put different approaches that reduce the consumption of power of Look Ahead Carry Adder. Conventional Look Ahead Carry Adder is compared with Adiabatic and Stacking Look Ahead Carry Adder.