{'fraction_non_alphanumeric': 0.026923076923076925, 'fraction_numerical': 0.005128205128205128, 'mean_word_length': 5.198412698412699, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Power-Efficient Floating-Point Co-processor Design

According to dramatically growing interesting in power-efficient embedded processor, designers must establish the proper power strategy when they design new embedded processor cores. This paper develops a SPARC compatible floating-point co-processor, which is part of a SPARC compatible embedded processor and implements the SPARC V8 floating-point instruction set except for square root and all quad precision instructions. To lower the power dissipation of floating-point co-processor, we modify the decoder stage of the integer unit pipeline to generate the clock gating signals so that the unused floating-point co-processor execution pipeline can be clock-gated. The design is implemented in a SMIC 0.18-mum CMOS process.