{'fraction_non_alphanumeric': 0.02075812274368231, 'fraction_numerical': 0.0, 'mean_word_length': 5.485380116959064, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Improving Digital Design PPA (Performance, Power, Area) using iSpatial Physical Restructuring

At advanced process nodes, the highly iterative nature of the digital IC design process has exacerbated the problem of achieving design closure. Early in the design flow, synthesis has more optimization flexibility such as power techniques and architecture selection to tradeoff among timing, power, and area. However, the accuracy of placement and routing is poor due to the lack of actual physical information about the design. While the implementation tool has already access to the actual design attributes in the physical design stage, optimization techniques are only limited to placement, routing, and cell resizing. To bridge the gap between synthesis and physical design in the digital IC design flow, this paper presents a unified placement, routing, and optimization engines through iSpatial flow. This merging of capabilities between two engines allows the synthesis tool to utilize the technologies from the implementation tool in order to provide a design with improved performance, power, and area.