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On the design of tunable high-holding-voltage LVTSCR-based cells for on-chip ESD protection

Optimization of the lateral dimensions of an LVTSCR-based ESD cell allows flexible tuning of the I-V characteristics and maximization of the cells' performance under snapback conditions during the high current regime of an HSD event. Once the trigger point is reached and the voltage snaps back, the holding voltage is dependent on lateral arrangement of the wells' implantations and changes in the cell's interconnections. Appropriate choices of these dimensions and interconnections permit design of tunable high holding voltages over a wide range. This paper presents the design optimization method and I-V characteristics of cells fabricated for different operational conditions and ultimate on-chip BSD protection schemes extendable to a variety of technologies.