{'fraction_non_alphanumeric': 0.028684470820969338, 'fraction_numerical': 0.002967359050445104, 'mean_word_length': 5.325, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration

SRAM-based field programmable gate arrays (FPGAs) are vulnerable to soft-error. To improve circuit dependability, various dependable design techniques have been studied. By the same token, evaluation techniques are required to ensure dependability. The most popular evaluation technique is reconfiguration-based fault-injection (FI) analysis. However, most FI analyses are inadequate for the evaluation of a dependable circuit because they don't consider fault accumulation. The critical issue is the reconfiguration time for injecting many faults. This paper presents an FI analysis system using frame-based partial reconfiguration and a bootstrap method to accelerate evaluation. As a result, our system can accelerate FI time by about a factor of 5 ~ 10 relative to the full-reconfiguration FI system. Further, the number of reconfiguration times is reduced to one out of several dozen by applying the bootstrap method.