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Effective communication methods for many core architectures with on chip networks in the absence of cache coherence

Since the beginning of the multicore era, parallel processing has become prevalent across the board. Accordingly, the development of processors with multiple computing cores per chip was caused by the fact that fundamental limits in single core performance had been reached. If the trend of integrating more and more cores to a single die continues, general purpose processors with hundreds of cores may be expected in the near future. Further in the future, many-core technology will potentially lead to processors with thousands of cores. The result of this development would be massive parallel-processor architectures that will inevitably create new challenges for the scalability of common software synchronization and communication methods. It is commonly believed that a reevaluation of established concepts is needed to address such research challenges. One important aspect is the reevaluation of hardware support for effective communication methods. Given a particular power budget per chip, this aspect will be of significant importance. A related question is the demand of changes for established architectures and for redesign of components to support thousands of cores. Similar challenges exist for the support of new memory technologies, which are emerging trends in the field of parallel computing. For instance, instruction-set extensions have been recently introduced for the established Intel Architecture to support non-volatile memory (NVM) and hardware transactional memory (TSX). Full control of on-chip data movement is a related aspect that will result in the waiving of transparent access – for example, of additional instructions for finer-grained cache control. Because the importance of efficient communication for processors with many cores cannot be underestimated, the focus of this dissertation is on the analysis of efficient communication methods to exploit locality, and on low latency of architectures that follow the network-on-chip paradigm and provide software-controlled high-performance memory in terms of low latency and high throughput. In 2010, Intel Corporation founded the Many-core Applications Research Community (MARC) to support many-core software research. As a member of this community, the RWTH Aachen University started the projects MetalSVM and iRCCE to explore new communication concepts and systemsoftware support for future many-core systems. These projects – the results of which are presented in this dissertation – include the development of software concepts for on-chip communication and synchronization in the absence of hardware-cache coherence. Intel’s Singlechip Cloud Computer (SCC) is a cluster-on-a-chip architecture that represents the first x86 based many-core processor. It implements a new communication concept by waiving full chip cache-coherence and providing hardware support for on-chip message passing with alternative support for on-chip consistency control and explicit communication. The experimental hardware consists of 48 cores which are connected through a mesh interconnect on a single processor die. This configuration, in combination with a flexible and fine-grained memory control, has enabled experiments and the development and verification of low-level communication concepts today, and it thereby guides the development of future systems. In order to further explore the scalability of low-level software for this kind of architecture, this dissertation includes consideration of the design of a transparent virtual extension. A major achievement of this project is a full working prototype of a cluster of clusters on a chip, which can emulate a many-core processor with more than two hundred cores. This prototype has enabled a deeper analysis of new many-core communication concepts, and has uncovered potential for optimization. Major performance improvements could be achieved by the combination and further development of well-known mechanism and software techniques. Moreover, a communication model is essential if we are to analytically explore the limits of many-core processors that follow the network-on-chip paradigm and implement a low-memory abstraction by providing softwarecontrolled on-chip memory. Fundamental requirements for the efficient communication methods that are developed, parametrized and evaluated in this work include configurable caches for direct on-chip memory access or at least finer-grained cache control for data movement. Moreover, a low-level contention model is developed to evaluate different synchronization concepts and to derive optimizations for many-cores with remote direct memory access. Because on this level a contention model is hardware specific, the decision was made to focus on a packed switched on-chip mesh interconnect. This interconnect is implemented by the experimental SCC architecture and also in the next many-core architecture of the Xeon Phi family: codename Knights Landing (KNL). The Intel SCC research system has been used to support analysis of methods and to verify the accuracy of our concepts when used to model communication. The research system has directly addressable memory, with a highperformance in terms of low-latency and high throughput in relation to the computational performance of the cores. The experimental hardware shares basic characteristics with attributes of future many-core architectures that result, for example, in a combination of stacked memory and a tight integration of the fabric interconnect. Such similarities create opportunities for the applicability of the effective communication methods to future architectures.