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Improved Cost of Test by Optimized Tester Utilization

The semiconductor test industry agrees that cost of test (CoT) is one of the biggest challenges today and it will be crucial in future. Test cell efficiency needs to be increased. Enhanced tester capabilities allow shorter test times and higher parallelism. Handlers try to keep pace with higher parallelism but missmatch with speed. The urgent challenge is to optimize the tester utilization in order to benefit from higher parallelism as well as from shorter test times. The solution needs to improve the overall handler preformance. Increasing the number of contact sites will not be sufficient. In addition speed related parameters like soak capacity, index time and loading and sorting speed need to be considered.