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A power-efficient high gain differential LNA in 0.18µm CMOS technology for 400–900 MHz frequency range

In this paper a differential low noise amplifier working in 400–900MHz frequency range is designed in 0.18µm CMOS technology with the help of Cadence software. By using common gate topology at the input of the proposed circuit and also employing one pair of series and parallel RLC to the load, the bandwidth is increased and the gain and S11 become flat in the desired frequency range. For the gain improvement a cross-coupled resistance is designed and set in parallel with the load. Furthermore by utilizing current-reused technique the gain is increased without dissipating extra power. The gain of the proposed LNA is 23dB, while its NF is lower than 2.5dB. The S11 parameter is lower than 10dB and IIP3 equals to 11.3dBm and power dissipation is 4.77mW.