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Performance investigation of a 1-bit periodic sigma delta phase-signal generator for mixed-signal embedded test

In this paper we present an implementation and performance investigation of a phase signal generator for use in mixed-signal embedded test. The generator consists of a circular 1×N-bit memory and a time-mode filter. The memory is loaded with a phase-modulated sigma-delta encoded bit stream generated in software. Due to its digital nature, the generator except for the time-mode filter is fully synthesizable using standard logic. A discrete prototype was constructed using off-the-shelf components at 50 MHz. It shown that the phase of the reference clock frequency can be shifted by approximately 45 degrees with a phase step of about 1 degree. The main limitation of this approach lies with the phase noise associated with the PLL making up time-mode filter.