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Full chip impact study of power delivery network designs in monolithic 3D ICs

In this paper, we present a comprehensive study on the impact of power delivery network (PDN) on full-chip wirelength, routability, power, and thermal effects in monolithic 3D ICs. Our studies first show that the full PDN worsens routing congestion more severely in monolithic 3D ICs than in 2D designs due to the significant reduction in resources for 3D connections. The increase in signal wirelength translates into additional net switching power dissipation, which significantly contributes to total power. This in turn aggravates thermal issues in 3D ICs. In addition, we observe that PDN tradeoffs among wirelength, power, and thermal are more pronounced in monolithic 3D ICs than TSV-based 3D and 2D designs. This is because of the higher integration density and the severe competition between signal and power connections. Lastly, we develop various PDN design optimization techniques for monolithic 3D ICs and obtain up to 8% signal wirelength and 5% maximum temperature reduction under the given IR drop budget.