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Power grid analysis based on a macro circuit model

Analysis and design of on-chip power grids are complex problems. A typical grid consists of hundreds of millions of transistors that act as current consumers. Typical algorithms for power grid analysis or power grid automatic design, model the current consumers, namely the CMOS logic gates, as ideal current sources. In this study we offer a new methodology for modeling the power-consuming gates on the grid. Our approach is based on the analysis of the total dissipated power by these consumers. We propose a new model for the current consumers, based on effective impedance. In this model, only passive elements are employed. It relies on a calculation of the effective capacitance and effective resistance of the logic gates. Since during each clock period the dissipated power and the stored energy are exactly represented, total energy and power are exactly modeled. Methods from statistical/computational physics can be adopted to represent clusters of consumers on each sub-grid as "macro-circuits". The interaction between the power grid and the current consumers is taken into account in this model and an example for it is presented.