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Strain Analysis of FinFET Device Utilizing Moiré Fringes in Scanning Transmission Electron Microscopy

In semiconductor industry, the progressing miniaturization makes the device structure to be three dimensional (3D). A typical 3D structure for a field effect transistor (FET), which is used for highly integrated devices, is a finFET, which has a tri-gate structure [1]. On the other hand, for the less power consumption and higher switching speed, the device technology utilizes strained silicon to enhance the mobility of carriers. In the case of a typical pMOS device, the strain arises between the stressors typically consisting of Si/Ge. It is important to measure of the strain of the channel in finFET. However, it was difficult to measure, since the channel is sandwiched with gates (see Fig. 1). And the sample thickness cannot be as thin as < 100 nm to avoid strain release [2]. On the other hand, we have succeeded to measure a strain by moiré fringes, which appears as a result of undersampling lattice fringes in the raster of scanning transmission electron microscopy (STEM), we namely call the method “STEM moiré” [3, 4, 5]. We applied the method to measure the strain of Si channel in a finFET. In this paper, we report how we measure the strain by the STEM moiré method.