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Fast thermal-aware floorplanning using white-space optimization

The power density of modern ICs continues to increase with each new process technology. Larger power density blocks result in higher temperatures which in turn decrease the reliability of chips and produce more leakage power. In this paper we present a method to help reduce the temperature of chips at the floorplan design level by adjusting block utilizations based on the available whitespace in a floorplan. We also briefly outline a method for fast and accurate thermal floorplanning. Our experimental results show that peak IC temperatures can be significantly reduced at the floorplan design stage by using the aforementioned methods without sacrificing significant increases in floorplanning run-time, or wirelength.