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Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems

Reconfigurable architectures such as FPGAs are a key technology for implementing self-adaptive and flexible systems, since the possibility for dynamic and partial hardware reconfiguration offers a higher degree of freedom in the resource allocation. However, for many applications, modern reconfigurable architectures cause too high power consumption. For this reason, FPGAs are typically used in highly computational applications where the possibility for performing parallel calculations can be exploited to achieve decreased power consumption as compared to a microcontroller based solution. In order to enable the usage of FPGAs even in lowpower applications, techniques for adapting the power consumption according to the work load must be investigated. One novel approach would be to exploit the possibility for dynamic reconfiguration of the FPGA for this purpose. This paper presents the realization of dynamic clock scaling in a Xilinx Spartan 3 based system by performing dynamic and partial reconfiguration of the fixed Digital Clock Manager (DCM) core configuration.