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Quantum Circuit Compiler for a Shuttling-Based Trapped-Ion Quantum Computer

Increasing capabilities of quantum computing hardware and the challenge to realize deep quantum circuits call for fully automated and efficient tools to compile quantum circuits. To express arbitrary circuits in a sequence of native gates pertaining to the specific quantum computer architecture is necessary to make algorithms portable across the landscape of quantum hardware providers. In this work, we present a compiler capable of transforming and optimizing a quantum circuit, targeting a shuttling-based trapped-ion quantum processor. It consists of custom algorithms set on top of the Cambridge Quantum Computer's quantum circuit framework Pytket. The performance is evaluated for a wide range of quantum circuits, showing that the gate counts can be reduced by a factor of up to 3.6 compared to standard Pytket and up to 2.2 compared to standard Qiskit compilation, while we achieve similar gate counts as compared to a Pytket extension targeting the AQT linear-static trapped ion addressing-based architecture.


Introduction
The current rapid maturation of quantum information processing platforms [1] renders meaningful scientific and commercial applications of quantum computers to be within reach. While it seems unlikely that fault-tolerant devices [2,3] will scale to sufficiently large logical qubit numbers in the near future, noisy intermediate-scale (NISQ) quantum devices are predicted to usher in the era of applied quantum computing [4]. The capabilities and performance of such platforms will be crucially determined by their quantum compiler stack: First, fully automated, hard-ware agnostic frontends enable access for non-expert users from various scientific disciplines and industry. Second, optimizations carried out at the compilation stage allow for circumventing limitations due to noise and limited qubit register sizes, thereby enabling increased functionality of a given NISQ platform.
With the scaling up of quantum hardware to larger qubit register sizes and deeper gate sequences, the platforms become increasingly complex and require tool support and automation. Thus, it is no longer feasible to manually design quantum circuits and use fixed decomposition schemes to convert the algorithm input into a complete set of qubit operations which can be executed by the specific quantum hardware, referred to as its native gate set. Dedicated quantum compilers are required for the optimized conversion of large circuits to low-level hardware instructions.
In this work, we present such a circuit compiler developed for a shuttling-based trapped-ion quantum computer platform [5,6,7]. This platform employs qubits encoded in long-lived states of atomic ions, stored in segmented microchip ion traps as depicted in Fig. 1. In order to increase potential scalability, subsets of the register are stored at different trap sites, and the register is dynamically reconfigured between subsequent gate operations by shuttling operations, which are carried out by controllably changing voltages applied to the trap electrodes. Gates are performed at specific trap sites and are driven by laser or microwave radiation. While this approach enables effective all-to-all connectivity within the register and avoids cross-talk errors [8], the shuttling operations incur substantial timing overhead, leading to rather slow operation timescales. This can lead to increased error rates, as dephasing is aggravated by the reduced operation speed. Furthermore, the shuttling operations can lead to reduced gate fidelities via shuttlinginduced heating of the qubit ions. Therefore, besides compiling a given circuit to a native gate set, the main task of the gate compiler stage of a shuttling-based platform is to condition the circuit such that the required amount of shuttling operations can be minimized. This is accomplished by minimizing the overall gate count and by arranging the execution order of the gates in a favourable way. The task of gener-

Background
Due to the increasing size and complexity of quantum circuits, circuit compilation is an active research field. Since the circuit compilation is essential to make algorithms portable and execute quantum circuits on different platforms, powerful frameworks for quantum computing [13,14,15] were developed. While the features of these are notably different, all frameworks offer built-in optimization. While the simplest form of circuit compilation replaces gates by predefined sequences of other gates (often referred to as a decomposition), more advanced techniques serve to minimize the number of gates. A common strategy is the reduction of overall gate count with special focus on expensive two-qubit gates [16,17,18]. There are various ways to achieve such a gate count reduction. One possibility is the utilization of a different circuit representation called ZXcalculus [19], which allows for simplifications on the functional level. A different approach uses templates, where common circuit patterns are searched and replaced by a shorter or otherwise preferable, but functionally identical gate sequences [18]. When compiling quantum circuits, also the qubit mapping is often considered. Ideally, each qubit can interact with every other qubit, such that two-qubit gates can be executed between each pair of qubits. However, for existing platforms, interactions are restricted to nearest-neighbor topology or full connectivity within subsets of limited size. Mapping the qubits from the algorithmic circuit to physical qubits subjected to these hardware restrictions is called the routing problem [13]. To render arbitrary two-qubit gates executable on the quantum hardware, SWAP gates have to be inserted into the circuit using heuristics [20,21,22,23]. In case of ion trap quantum computers, ion positions can be physically swapped to establish dynamical all-to-all connectivity. Consequently, no computational SWAP gates have to be inserted at this stage. The Cambridge Quantum Computing's Pytket framework [13] offers a wide variety of circuit transformation algorithms and is therefore used as the operational basis for the custom circuit compiler described in this work. Functionality like the removal of redundancies as well as the rebasing of arbitrary gates into the native gate set is realized mainly using built-in functions of Pytket. Since Pytket is designed for superconducting architectures, some specific functionalities for trapped-ion quantum computers were additionally developed and implemented. This includes the concatenation of multiple local rotations into global rotations, restricting gate parameters to a fixed set of values and improving the gate order.

Graph description of the quantum circuit
In this section a quantum circuit is described as directed acyclic graph (DAG), which is the data structure Pytket and our custom subroutines work on. The  Fig. 2: Example of a quantum circuit's graph with four qubits and seven gates. The four qubits are depicted on both sides and every qubit qi is assigned to its input node vi. In the middle are the gates which are executed on the qubits. Each gate has as many subnodes as qubits the gate is acting on. On the right side are the output nodes for each qubit. The directed edges show in which order the gates are executed on each qubit represented by the different edge colors. No gate is executed on qubit q3.
first subsection defines the DAG and in the second subsection the DAG is constructed. Such a graph is depicted in Fig. 2. At the end of this section, we describe the native gate set of our platform.

Graph definition
We consider a quantum circuit consisting of a set Q = {q 0 , . . . , q n−1 } of n qubits. The circuit is represented as directed acyclic graph C = (V ∪ G ∪ W, E) with sets of vertices V, G and W which are pairwise disjoint and defined as follows: • V is the set of input vertices. For every qubit q i ∈ Q exists exactly one vertex v i ∈ V, so |V| = n applies. Every vertex v i has exactly one outgoing edge.
• G is the set of the circuit's quantum gates. If a quantum gate operates on m ≥ 1 different qubits q i0 , . . . , q im−1 ∈ Q, the vertex will have exactly m incoming and m outgoing edges. Additionally, every gate G ∈ G depends on a ≥ 0 parameters, which are angle parameters with values of 0 ≤ φ 0 , . . . , φ a−1 < 2π. In the following, a gate G acting on the qubits q i0 , . . . , q im−1 and depending on the parameters φ 0 , . . . , φ a−1 is denoted as where j is a unique identifier for the gate.
• W is the set of output vertices. For every qubit q i ∈ Q exists exactly one vertex w i ∈ W, so |W| = n applies. Every vertex w i has exactly one incoming edge.

Graph construction
Each quantum circuit C starts with the input vertices v 0 , . . . , v n−1 ∈ V. Every qubit q i ∈ Q is assigned to its vertex v i . The outgoing edge (v i , G) ∈ E leads to the vertex G ∈ G that represents the quantum gate which is executed first on q i . If the circuit does not contain any quantum gate executed on q i , the outgoing edge will lead directly to the output vertex w i ∈ W so that (v i , w i ) ∈ E applies. All nodes in G represent the inner nodes of the circuit C. If a gate G j ∈ G is executed directly before a gate G k ∈ G on the same qubit q i , G j and G k will be connected by one directed edge G j , G k ∈ E. The end of the circuit C is built by the output vertices w 0 , . . . , w n−1 ∈ W. Every qubit q i ∈ Q is assigned to its vertex w i . The incoming edge (G, w i ) ∈ E comes from the vertex G ∈ G that represents the quantum gate which is executed last on q i . If the circuit does not contain any quantum gate executed on q i , the incoming edge will come directly from the input vertex v i ∈ V.
In contrast to the input and output vertices, which have all exactly one outgoing or one incoming edge, the inner nodes have m ≥ 1 incoming and outgoing edges. To manage these edges, every inner vertex G j ∈ G consists of m subnodes s j,0 , . . . , s j,m−1 .
Each of these subnodes has exactly one incoming and one outgoing edge. The set of the subnodes of G j is denoted as S G j in the following. Assume G j , G k , G l with G j ∈ V ∪ G, G k ∈ G and G l ∈ G ∪ W are executed sequentially on a qubit q i ∈ Q, so that the edges e in = G j , G k ), e out = (G k , G l ∈ E exist. Instead of directly connecting the incoming edge e in to G k , it is connected to a subnode s k,α ∈ S G k . The outgoing edge e out starts on the same subnode s k,α . Each subnode has only one incoming and outgoing edge. If G k is a controlled gate, the m − 1 control qubits are connected to the subnodes s k,0 , . . . , s k,m−2 and the target qubit to the subnode s k,m−1 . Because only q i is connected to the subnode s k,α , the subnode can be denoted as s k,α i . After constructing the complete graph, there are n disjoint, clearly defined paths in C beginning on one input vertex v i ∈ V and ending at a output vertex w i ∈ W. Every path from v i to w i describes the order in which the gates are applied to qubit q i ∈ Q. An example of a graph representation of a quantum circuit is shown in Fig. 2.

Native gate set
The state of an n qubit register is commonly represented by a normalized complex-valued vector with 2 n entries, corresponding to the probability amplitudes of the logical basis states. The gates then act as unitary transformations on the state, which are represented by unitary matrices of dimension 2 n × 2 n . The serial execution of gates on different qubits is represented by products of unitary operators or the corresponding matrices, where the products are read from right to left. Note that we employ a less strict notation throughout the manuscript, where operator products are written as simple products albeit the operators might act on different subsets of the qubit register and tensor products are not always written explicitly. Since global phases of the quantum states do not affect measurement outcomes, equality of unitaries and states denotes equality up to a global phase. To execute the circuit C on a given hardware platform, it must be transformed to an equivalent circuit consisting only of gates from a native gate set. Our platform [8] implements the native gate set where each gate is parameterized using up to two rotation angles θ and φ with 0 ≤ θ, φ < 2π. In the following they will be also referred to as the pulse area and the phase, respectively, due to their meaning for the actual operation. The gates from M are defined as follows in terms of the Pauli operators X, Y and Z: The gates R and Rz are single qubit gates, whereas ZZ is a two-qubit gate. This set is complete, such that any quantum algorithm can be decomposed into a sequence of these operations [24,25]. Note that some trapped-ion platforms do not allow for native ZZ gates, but rather employ XX gates generated by bichromatic radiation fields [26]. Our compilation scheme is still vaild for such architectures, as ZZ gates can be generated from XX gate using local wrapper rotations. Furthermore, the identity I, the Pauli gates X, Y, Z and rotations around X and Y , Rx and Ry, are special forms of the R and Rz gates and therefore also part of the native gate set. Their relation to the gates in M is A peculiar feature of the shuttling-based platform concerns SWAP gates, defined as While these gates, required to establish full effective connectivity, could be realized using the logical gates contained in M, they are removed from circuits upon compilation and reintroduced in a following compilation stage, which is discussed in Sec. 4.1. Instead of laser-driven SWAP gates, physical ion swapping is used to reconfigure the qubit registers. This process is advantageous as it does not require manipulate of the internal qubits states and therefore can be executed at unit fidelity [27,28,29]. On our platform, all gate operations from (3) are realized via laser pulses, and the rotation angle parameters θ correspond to pulse areas, i. e. integrals of intensity over time. In order to perform gate operations at high fidelities, these pulse areas must be carefully calibrated. We therefore restrict the set of available gates to rotation angles equal to the pre-calibrated pulse areas θ = π and θ = π 2 for R gates and π 2 for ZZ gates. Note that there is no restriction on the rotation angle θ for the Rz gates. Concatenated application of R gates allows for all pulse area multiples of π 2 . The phases φ of the gates can be chosen arbitrarily at a resolution only limited by hardware capabilities. These considerations lead to a restriction of the gate set to: In the following sections, the individual transformations leading to a circuit entirely comprised of elements of N will be described.

Transformations
The overall goal of a quantum compiler is to modify and rearrange gates in a given quantum circuit in order to obtain an equivalent circuit with reduced total gate count and more favorable operations in terms of the execution resources fidelity and runtime. The following section describes the transformations applied to the input circuit C for converting into a circuit comprised only of gates from the allowed gate set N , composed in a way minimizing the execution overhead on a shuttling-based platform. For some of the following transformations, the built-in functions of the quantum programming framework Pytket [13] are used. An overview over all compilation steps and the corresponding set of gates is shown in Fig. 3. In the same order, each compilation step will be described in a subsection. In general, transformations impacting the circuit structure on a large scale are applied earlier while local adjustments are applied at later stages to preserve optimized structures of previous steps. Throughout this section, we assume the input circuit C to consist only of quantum gates defined within Pytket [30]. This means that all highlevel sub-circuits, e. g., a Quantum Fourier transform, are substituted by Pytket-defined quantum gates before applying the following transformations. A circuit which contains gates not being part of the restricted native gate set N and deals as an example throughout this section is depicted in Fig. 4. In addition to Pytket's built-in algorithms, the characteristics of the segmented ion trap architecture are

Elimination of SWAP gates
Our shuttling-based ion trap quantum computer natively supports physically swapping ions [27,28,29], required for establishing effective full connectivity between the ion qubits. In contrast to other gates, SWAP gates are carried out by physically swapping ions. Thus, the function of SWAP gates is replaced by renaming the qubits for all succeeding operations. It is the task of the Shuttling Compiler further downstream in the software stack to generate the corresponding reconfiguration operations. The process of SWAP gate elimination on the circuit from Fig. 4 is shown in Fig. 5. In order to eliminate the SWAP gates the elimination algorithm iterates over the gates G ∈ C in their executing order. When G is a SWAP k i,j gate acting on the qubits q i and q j , G has two subnodes s k,0 i and s k,1 j , respectively. The algorithm exchanges the outgoing edges of these two subnodes. This means that on q i all gates are applied which are on the path from the input node v i to SWAP k i,j . Because the outgoing edges of s k,0 i and s k,1 j were exchanged, after SWAP k i,j q i follows the path original followed by q j . The same holds for q j which follows after SWAP k i,j the path original followed by q i . Consequently, all gates after SWAP k i,j which were original executed on q j are now executed on q i and vice versa. In this way the swap is passed through all gates succeeding SWAP k i,j , and SWAP k i,j can be eliminated from the circuit.

Repeated removal and commutation of gates
To reduce the total gate count, after some transformations it is tested whether the circuit contains redundant gates or gate sequences. For this purpose, Pytket's RemoveRedundancies pass is used. Additionally, Pytket's CommuteThroughMultis pass is executed to commute gates. When applying commutations, single qubit gates are commuted through (a) The SWAP gate elimination is applied on the first SWAP gate (the red box). Compared to Fig. 4 the outgoing edges are exchanged. This means that after the SWAP gate, q 1 is following the green path and q 2 the blue one. Consequently, the qubits on which the CNOT 2,0 , CRy 3,1 (π),SWAP 2,0 and ZZ 1,2 (π) gates from Fig. 4 are acting on must be adapted to the new qubit following the path. Because all gates which are on the path of q 1 and q 2 after the SWAP gate are adapted to the new qubit following the path, the SWAP gate can be eliminated from the circuit.
(b) The SWAP gate elimination is also applied on the second SWAP gate (the right red box). Consequently, the outgoing edges are exchanged compared to panel (a). This means that after the SWAP gate, q 0 follows the green path and q 1 the red one. Because the CRy 3,0 π 2 gate from panel (a) is adapted to q 1 following the red path and the ZZ 2,1 (π) gate to q 0 following the green path, the SWAP gate can be eliminated from the circuit.  two-qubit gates wherever possible. This may again give rise to redundant gates, which can then be removed. Procedures of commutation and removing are repeated until the total gate count does not further decrease. This transformation step is first executed after eliminating the SWAP gates and will be applied after some of the later transformation stages as well. It conserves the property of a gate sequence being in gate set M or being in gate set N up until multiples of π 2 .

Macro Matching
Although Pytket contains a transformation for arbitrary gates into the native gate set M, which will be utilized in Sec. 4.4, a custom decomposition might yield better results. Therefore, in this step, for several gates or gate sequences, a predefined decomposition into the native gate set -termed macro matching -is applied to the quantum circuit. This is especially useful for large structured circuits, where known structures can be replaced by beneficial alternatives. The macro matching transformation is carried out only for gates acting on m ≥ 2 qubits, as efficient transformations of local rotations m = 1 exist, (see Sec. 4.4). Let L be a set of gates for which an efficient decomposition is known. All gates from C contained in L are substituted by a sequence of gates from M. The gate sequence of the macro is defined in a way that it can be described by the same unitary matrix as the gate G, up to a global phase. An example for such a macro is Due to the angle restrictions of the gates in N , this macro is only applied if θ = π with ∈ Z holds. Otherwise, the original CRy gate remains in the circuit and will be substituted via the transformations in Sec. 4.4. To simplify the circuit the repeated removal and commutation of gates from Sec. 4.2 is executed again. It is depicted in Fig. 6 how the macro matching is applied to the circuit from Fig. 5c.

Transformation to the native gate set
The predefined gate decomposition into the native gate set via macro matching is followed by the conversion of all remaining gates into the native gate set. For this transformation, two different approaches can be employed. In the first approach, Pytket's Clif-fordSimp pass is applied to the quantum circuit C, which contains simplifications similar to Duncan and Fagan [31]. After applying the CliffordSimp pass on a circuit, the resulting circuit consists only of Pytket's universal single qubit TK1 gates and two-qubit CNOT gates, which are defined as follows: Because the CliffordSimp pass also converts ZZ gates with θ ∈ { π 2 , π, 3π 2 } already contained in C to a sequence of several TK1 and CNOT gates, it is not directly applied to the entire circuit C, but is executed on subcircuits of C such that ZZ gates with θ ∈ { π 2 , π, 3π 2 } are preserved. This is advantageous because ZZ π 2 gates are already part of the restricted native gate set N and thus this gate sequence would not become shorter. Similarly, ZZ (π) as well as ZZ 3π 2 gates can also be transformed with a smaller gate count, see Sec. 4.10. The result when applying the Clifford-Simp pass on the example from Fig. 6 can be seen in Fig. 7a. As it will be seen in Sec. 5, the CliffordSimp pass has a non-linear runtime in the number of gates. To make even large circuits transformable in a reasonable time, we developed an alternative approach to convert an arbitrary gate sequence to the given native gate set uses Pytket's SquashTK1 pass which simplifies single qubit gate sequences. Because this pass does not change the two-qubit gates and the built-in rebasing routine employed in the following paragraph does not allow to restrict the rotation angles to the ones contained in the restricted native gate set, all ZZ gates in C with θ / ∈ { π 2 , π, 3π 2 } must be substituted manually. For that purpose the following decomposition is used: After the substitution, the repeated removal and commutation of gates from Sec. 4.2 is executed again to simplify the circuit. Following, Pytket's SquashTK1 pass is applied, which converts every sequence of single qubit gates to exactly one TK1 gate. Applying these substitutions on the example from Fig. 6 results in the circuit shown in Fig. 7b. For either approach used, the gates in C are subsequently transformed to the gates in the set {Rx, Rz, ZZ}. This process is called rebasing. The transformation is executed using Pytket's Rebase-Custom pass. We found smaller gate counts when excluding the Ry gate, thus we excluded Ry from the set. Because the circuit C can contain two-qubit gates which are not ZZ gates when using the second approach described above, the rebasing first substitutes all two-qubit gates not being ZZ gates to sequences of TK1 and CNOT gates and subsequently rebases the TK1 gates by the definition from (8a) and the CNOT gates to The decomposition guarantees that only ZZ gates with an angle of θ = π 2 are introduced into G so that after applying this transformation, all ZZ gates have an (a) Example from Fig. 6 after applying Pytket's CliffordSimp pass as described in Sec. 4.4. All sequences of single qubit gates were substituted by exactly one TK1 gate. Moreover, the CRy 3,1 (π) gate in Fig. 6 was transformed to the two orange CNOT 3,1 gates and additional TK1 gates. Because the CliffordSimp pass is executed so that ZZ gates with θ ∈ { π 2 , π, 3π 2 } are not converted, ZZ 3,2 π 2 and ZZ 2,0 (π) remains in the circuit.   angle θ ∈ { π 2 , π, 3π 2 }. After applying the RebaseCustom pass on the circuits from Fig. 7a and Fig. 7b the circuit in Fig. 7c results.

Building Rx-Rz sequences
At this point, the quantum circuit contains only R and Rz gates with arbitrary angle parameters as single qubit gates and ZZ gates with an angle parameter of π 2 as two-qubit gates. This makes the gate set of the quantum circuit gates compatible with the native gate set M. Since any arbitrary sequence of single qubit gates can be compactly represented by exactly one TK1 gate, the first step is to reduce every sequence of concatenated single qubit gates into a TK1 gate. Such sequences start and end at either two-qubit gates or at input or output vertices v i , w i . The implementation of the algorithm is Pytket's SquashTK1 pass. It is depicted in Fig. 8a how this algorithm is applied to the circuit from Fig. 7c. Then, Pytket's RebaseCustom pass is used to transform the TK1 gates into gates of set M using (8a). It is instructive to write down the circuit unitary reduced to all gates acting along the path of qubit q i , which assume the following form: In this expression, ω i is the number of ZZ gates executed on q i and j (λ) stands for the qubit q j(λ) on which the ZZ gate λ also acts. The circuit from Fig. 8a in which each path has the above form after applying the transformation is shown in Fig. 8b. Each ZZ gate ZZ k i,j ∈ C is now sandwiched by two Rz gates, which commute with the ZZ k i,j gate, on both qubits q i and q j . Therefore, we can commute the succeeding Rz gates through the ZZ gates and merge with the preceding Rz gates: (12) Repeating this procedure combined with the elimination of redundant gates until no further reduction of the number of gates is possible as described in Sec. 4.2 results in a circuit C in which the disjoint paths of each qubit q i ∈ Q have the following form: Consequently, on each qubit q i at most one Rx and one Rz gate are executed between two ZZ gates. Let be the number of ZZ gates in G. Hence, G consists exactly of ω two-qubit gates and at most 4ω + 3n single qubit gates. It is shown in Fig. 8c how this transformation is applied to the circuit from Fig. 8b. Rx and Rz with arbitrary angles are the only remaining single qubit gates in the circuit and both are also part of M. Since also all remaining two-qubit gates are part of that set, all gates G i of the circuit now fulfill G i ∈ M.

Transforming single qubit gates to our trapped-ion native gate set
Since all gates in the circuit are now part of M, the next step is to make the angles compliant with the restricted native gate set N , which has restrictions to the allowed rotation angles. Therefore, all Rx gates must have θ ∈ π 2 , π . Two trivial conversions can be executed for θ = 0 and θ = 3π 2 . In the first case the gate is equal to the I gate and can thus be eliminated. In the second case the gate can be substituted by Rx π 2 Rx (π). Rotations Rx with any other values of θ are required to be converted into a sequence of Rx gates with allowed rotation angles and Rz gates with freely variable rotation angles. We employ the decomposition After this substitution, the restrictions of the restricted native gate set N are fulfilled for the single qubit gates. It is shown in Fig. 9a how the circuit from Fig. 8c is transformed. Because this transformation is directly applied after the creation of Rx-Rz sequences in Sec. 4.5, the unitaries pertaining to the disjoint paths of each qubit q i assume the following form: By again commuting Rz gates through ZZ and combining consecutive Rz gates according to (12) using the procedures from Sec. 4.2, the expression can be simplified to Consequently, on each qubit q i at most two Rx and two Rz gates are executed between two ZZ gates. Let ω be the number of ZZ gates in G as defined in (14). Hence, G consists exactly of ω two-qubit gates and at most 8ω + 5n single qubit gates. It is depicted in Fig. 9b how this transformation is applied to the circuit from Fig. 9a. Since all R(x) gates now fulfill θ ∈ π 2 , π , all single qubit gates are now part of the restricted native gate set N .
(a) Example from Fig. 7c after applying Pytket's SquashTK1 pass. Each single qubit gate sequence was transformed to exactly one orange TK1 gate.
(b) Circuit after applying Pytket's RebaseCustom pass on the circuit from the panel (a). Each TK1 gate was transformed to the TK1 decomposition consisting of three gates. Because the angles of same gates from the decomposition are 0 and thus these gates are equal to the identity gate, some decomposition have less than three gates.
(c) Circuit from panel (b) after the Rz gates were commuted through the ZZ gates and the resulting redundancies were removed. Consequently, there are at most two single qubit gates between two ZZ gates on each qubit q i and between the last gate executed on q i and the output node of q i . Only between the input node of q i and the first gate executed on q i three single qubit gates are possible.  (b) Circuit from panel (a) after the Rz gates were commuted through the ZZ gates and the resulting redundancies were removed. Because the transformation is applied directly after the building of the Rx-Rz sequences there are at most four single qubit gates between two ZZ gates on each qubit q i and between the last gate executed on q i and the output node of q i . Only between the input node of q i and the first gate executed on q i five single qubit gates are possible.   Fig. 9b after applying the phase tracking algorithm on the circuit. For each Rx gate, the graph contains an R gate depending on the angle of the original gate and the value of the tracking phase bi when executing the algorithm on qubit qi. The R gates can be simplified to Rx or Ry gates if bi = 0 or bi = π 2 , respectively. The graph does not contain Rz gates any more except between the last R gate executed on each qubit qi and the output node of qi. Consequently, there are at most two R gates between two ZZ gates on each qubit qi and between the input node of qi and the first gate executed on qi.
Only between the last gate executed on qi and the output node of qi two R gates and one Rz gate are possible. Because the value of tracking phase b0 is 0 after applying the algorithm on qubit q1 and q3, there is no Rz gate placed before the output nodes of q1 and q3.

Phase tracking
We now utilize that a gate Rz followed by a gate R is equivalent to a single R gate with a phase shifted by the rotation angle of the Rz gate: Combined with the fact that Rz gates commute through ZZ gates this allows for virtual execution of all Rz gates using the well-known approach called phase tracking [32,7]. This technique avoids any physical execution of Rz gates and is therefore beneficial in terms of overall runtime and fidelity. All R gates contained in C have to be modified in terms of their phase arguments according to the procedure outlined in the following.
The algorithm initializes a tracking phase b i = 0 for every qubit q i ∈ Q and follows its path from input vertex v i ∈ V to output vertex w i ∈ W. The following rules are applied to each gate g ∈ C encountered: An additional gate Rz i (b i ) is inserted into C directly before w i , correcting for the final accumulated phase.
Since the Rz gate does only change the phase of the qubit, the measurement result in the computational basis as performed on the hardware would not be affected. However, adding the Rz gate still has advantages when working with the unitary matrix and when using the circuit as a building block for even larger circuits. An example can be seen in Fig. 10.
Because the phase tracking algorithm is directly executed after the transformation of Sec. 4.6, the disjoint paths of each qubit q i ∈ Q assume the following form: Note that the subsequent R gates can generally not be merged as they have different phase parameters. Thus, on each qubit at most two R gates are executed between ZZ gates. Hence, G consists exactly of ω two-qubit gates and at most 4ω + 3n single qubit gates. Consequently, phase tracking can almost halve the number of single qubit gates.
Since only phases, but not pulse areas, are changed, still all single qubit gates are part of N .

Block aggregation
In this section, we describe further optimization steps which are specific to our shuttling-base architecture.
Here, the ions are stored in a linear segmented trap, where qubit subsets are stored at different trap segments. The qubit sets can be rearranged between gate operation via shuttling operations [8,6]. All gate operations are carried out by laser beams directed to a fixed location, the laser interaction zone. Here, any gate operation is carried out simultaneously on all ions stored. Identical single qubit gates can be executed in parallel on multiple qubits. Now we will use this to reduce the number of gates. As an additional constraint, we keep the shuttling operations at a minimum. Thus single qubit operations are only parallelized on qubits already situated in the same segment, i. e. before or after performing a two-qubit gate on them. The optimization described in this section deals with the aggregation of single qubit gates. It uses the property that there is a specific structure around certain ZZ gates.
Directly before and/or directly after a ZZ gate ZZ k i,j , there can be sequences of preceding single qubit gates p = (p 0 , . . . , p α−1 ) , p 0 , . . . , p α−1 ∈ C and/or succeeding single qubit gates s = (s 0 , . . . , s β−1 ) , s 0 , . . . , s β−1 ∈ C which are similar on both qubits q i , q j ∈ Q on which the gate ZZ k i,j is acting on. This means that in these sequences the gates as well as the angle parameters exactly match on q i and q j . The advantage of these sequences is that the gates p 0 , . . . , p α−1 , s 0 , . . . , s β−1 can be executed simultaneously for both qubits q i and q j rather than being executed sequentially for each qubit, which reduces the execution time and the required shuttling overhead. Every ZZ gate including the single qubit gates contained in the sequences p and s make up one block A. The block pertaining to ZZ k i,j is denoted as A ZZ k i,j in the following. Iterating over all ZZ gates in their execution order, for every gate ZZ k i,j the algorithm will look if q i and q j undergo an indentical single qubit gate G p directly before ZZ k i,j . If this is the case and G p does not already belong to another block on q i or q j , G p will be added to the predecessor sequence p of block A ZZ k i,j and the procedure is repeated with the gate directly before G p . Otherwise p cannot be increased. The same procedure is repeated with the gates directly after ZZ k i,j to build the sequence s of A ZZ k i,j . Because the ZZ gates are traversed in their execution order, it is guaranteed that candidate gates for s do not already belong to another block. If it is not possible to build p and s, the block will consist only of ZZ k i,j . An example of the block building process is depicted in Fig. 11. After building such blocks around every ZZ gate ZZ k ∈ C, there can exist gate sequences b 0 , . . . , b −1 which do not belong to one block. Each of these blockless sequences consists only of single qubit gates and pertains to exactly one qubit. The aim is now to minimize the number of the blockless sequences. To minimize the amount and length of blockless single qubit sequences, the blocks can be rearranged and single qubit gates can be split. These two approaches will be discussed in the following two subsections.

Rearrangement of blocks
Block rearrangement is possible if before a sequence p of a block A α , both qubits q i and q j undergo the same gate G, but for one qubit, e. g., q j , G already belongs to a preceding block A β and for q i , it belongs to a blockless sequence b µ . Assume A β operates on the qubit q j and a third qubit q k . If the entire blockless sequence b µ is equal to the end s e of the sequence s of block A β , the gates of b µ and s e acting on qubit q j will be appended at the front of the sequence p of A α . Consequently, the blockless sequence b µ is eliminated and the gates of q j in s e are removed from s e , see Fig. 12a and Fig. 12b. Because only the gates of qubit q j in s e are removed from s e , the gates of qubit q k in s e now give rise to a new blockless sequence b ν . To eliminate b ν , it is necessary that b ν borders on a third block A γ operating on qubit q k and a qubit q l . Here, the case q i = q l is possible. If before the sequence p of A γ there exists a blockless sequence b ξ on qubit q l containing the sequence b ν on its end b ξe , b ν and b ξe will be appended at the front of p of A γ and the number of blockless segments on the circuit will be minimized by one. This can be seen in Fig. 12b and Fig. 12c. If a minimization of the number of blockless sequences is not possible, because a matching sequence is missing during the algorithm, the blocks will not be rearranged. The rearranging procedure is repeated for all blocks on which rearrangement is possible.

Angle splitting
After the rearrangement, the number of blockless sequences might be further reduced by splitting the rotation angles of certain gates. Assume that before a sequence p or directly after a sequence s of a block A ZZ k i,j , both qubits q i and q j undergo rotations R i (θ i , φ) and R j (θ j , φ) with the same phase angle but different rotation angles. Then, it is possible to split the gate with the larger rotation angle into two rotations, merge the resulting two identical gates into the respective set s or p of the block and eventually reduce the number of blockless sequences. The phase angle will be omitted from the notation in the following. We now assume G i (θ i ) to belong to the blockless se-(a) Before the block Aα the same gate sequences bµ and se are executed on the qubits q 1 and q 3 . On q 1 the gate sequence bµ is a blockless sequence while on q 3 the gate sequence se belongs to another block A β . To eliminate the blockless sequence bµ, bµ and the gates on q 3 from se can be added as predecessor sequence to Aα.
(b) bµ and the gates on q 3 from se were added as predecessor sequence p to Aα. Consequently, the gates on q 2 from se build now a new blockless sequence bν . This blockless sequence is identical to the blockless sequence b ξe on qubit q 1 . Because bν and b ξe are both directly before a third block Aγ , they can be added as predecessor sequence to Aγ .
(c) bµ and b ξe were added as predecessor sequence p to Aγ . Through the rearranging of the blocks the graph has now one blockless sequence less than in panel (a).
(d) In panel (c) before the block of the gate ZZ 0 0,1 and after the block of the gate ZZ 2 0,2 the same gates are executed, but with different pulse areas θ. When applying the angle splitting approach, the gate with the greater angle is substituted by the two orange gates. Because the gate next to the block as well as the blue gate have the same angle, these two gates can be added to the block. In this way two blockless sequences are eliminated. On the two R gates before the block of gate ZZ 1 2,3 the angle splitting approach cannot be applied because the phase φ differs. quence b i and G j (θ j ) to the blockless sequence b j , and both b i and b j are directly either preceding or succeeding block A. We further assume without loss of generality that θ i < θ j . The gate G j (θ j ) can be split into two subsequent gates G j (θ i ) G j (θ j − θ i ), such that a simultaneous gate G(θ i ) can be merged to either p or s. In the former case, G (θ i ) will be appended at the front of p, while in the latter case, G (θ i ) will be appended at the end of s. In both cases, In this way the blockless sequence b i is reduced by one gate and can be eliminated if the sequence is now empty. If this is not the case and b i cannot be eliminated, the transformation step is rejected and the initial gates G i (θ i ) and G j (θ j ) are retained. The procedure is repeated until no block A can be increased any more. The execution of the angle splitting approach on the circuit from Fig. 12c is shown in Fig. 12d. Afterwards, all sequences b which cannot be eliminated completely are transformed according to Sec. 4.4, such that they consist of a minimal number of native gates from N . The same transformations are applied to the sequences p and s of each block A to minimize the number of used gates. Note that before the angle splitting step, the circuit consists only of gates with rotation angles θ ∈ π 2 , π , therefore the angle splitting preserves the property that all gates are contained in the set of allowed gates N .

Commutations of blocks and blockless sequences
Now, commutations of blocks and blockless sequences are used to reduce the number of required shuttling operations. Blocks and blockless sequences are rearranged, which facilitates the work for the subsequent Shuttling Compiler stage. There are two different commutations, which will be described in the following. An example of the commutation rules is depicted in Fig. 13. The first commutation deals with the order of blocks: If two blocks A α and A β are executed on the qubits q i , q j and in between no other block is executed neither on any of those qubits, then A α and A β are commuted such that between them only blockless sequences acting on q i or q j are executed. The order in which these two blockless sequences are executed is not relevant since it does not influence the total count of required shuttling operations. This commutation affects the Blocks 8 and 11 in Fig. 13b. Both blocks are applied on the qubits q 2 and q 3 . Between these two blocks no other block and only the blockless sequences 9 and 10 are executed. The second commutation sorts the order of the remaining blockless sequences: Blockless sequences acting on q i and q j are commuted so that they are both  and q 3 no other block and only blockless sequences acting on q 2 and q 3 are executed. Because Block 14 is the next block after Block 11 and both gates act on qubit q 2 , the blockless sequences applied after Block 11 are ordered so that the sequence on qubit q 3 is executed before the sequence on qubit q 2 . Consequently, the sequence on qubit q 2 is executed directly before the Block 14. executed directly before or after a block A α which acts on these two qubits. If the next block A β executed after A α also acts on q i , but not on q j , then the blockless sequence of q j will be moved directly after A α and before the blockless sequence of q i . The same rule holds if A β acts on q j , but not on q i , correspondingly. If A β acts neither on q i nor q j then the order of the single qubit gate may be arbitrary. The case in which A β acts on q i and q j is discussed in the previous paragraph. This commutation affects Block 3 in Fig. 13b, which is executed on the qubits q 0 and q 1 . Directly before Block 3 the blockless sequences 1 and 2 and directly after Block 3 the blockless sequences 4 and 5 are executed. All these blockless sequences act on q 0 or q 1 , respectively. The execution order of the sequences 1 and 2 is not strictly defined. The next block which is executed after Block 3 on q 0 or q 1 is Block 14. Because Block 14 is only applied to q 1 out of these two qubits, the blockless sequence 4 on q 0 is executed before the blockless sequence 5 on q 1 .

Transformation of two-qubit gates to our trapped-ion native gate set
During the transformation in Sec. 4.4, the ZZ gates are converted so that they have a phase θ ∈ π 2 , π, 3π 2 . Because the native get set N only contains the gate  Fig. 10 after applying the transformation of two-qubit gates to the restricted native gate set. The ZZ2,0 (π) gate in Fig. 10 is transformed to the two orange ZZ2,0 π 2 gates. All gates of the circuit are in the restricted native gate set N .
ZZ π 2 , the ZZ gates with a phase of π or 3π 2 or must be transformed so that the condition is satisfied. Therefore the following decomposition is used: This transformation is applied to the circuit from Fig. 10 in Fig. 14.
Note, that this transformation could also have been applied earlier. However, not only would that not have any benefits but it would also worsen the block aggregation runtime as there are more two-qubit gates to consider. It shall also be mentioned that the single qubit gates are already part of the restricted native gate set and since the two-qubit gates are so, too, the circuit is now executable on the target quantum computing architecture.

Evaluation
In this section, the evaluation results of our compiler are presented. We test the compiler for a library of 149 quantum circuits [33] which were previously used for benchmarks [20,21,22,23]. Each circuit has between 3 and 16 qubits and 5 to 125,362 gates. The evaluations were executed on a notebook with an Intel Core i7-10750H CPU and 16 GB RAM. We evaluated the impact of the different compilation stages on the result. Additionally, our compiler is compared to standard Pytket [13] and Qiskit [15] passes as well as the results of the Pytket's pytket-aqt extension [34]. This extension was developed by the company AQT targeting an ion trap quantum computer [35]. We employ Pytket version 1.1.0, Qiskit version 0.36.1 and pytket-aqt version 0.19.0. We always determine the runtime averaged over 10 executions of a given circuit. The resulting single qubit and two-qubit gate counts are shown in App. A. All circuits were executed using the compilation flow depicted in Fig. 3. For the macro matching of Sec. 4.3, only the CRy macro given in (7) was used. Since we presented two alternative ways of transforming to the native gate set, as discussed in Sec. 4.4, these approaches are compared. While the first scheme performs additional optimizations using Pytket's CliffordSimp pass, the second scheme transforms based on the ZZ decomposition from (9) and Pytket's SquashTK1 pass without further optimizations. The two different approaches are visualized in Fig. 3, where they constitute the left and the right control paths, respectively, in the uppermost blue box. In the following, these two schemes will be referred to as the CliffordSimp and SquashTK1 approaches.
In the following, first the impact of the different transformation will be analyzed. Afterwards, our compiler will be compared to Pytket, AQT ans Qiskit.

Analysis of the impact of the different transformations
When analyzing the results, the CliffordSimp approach usually produces between 0.96 and 1.40 times lower gate counts for the circuits than the SquashTK1 approach. The single qubit gate count of the Clifford-Simp approach is between 0.94 and 1.35 times less, while the two-qubit gate count is between 1.00 and 1.50 times less, which means that the two-qubit gate count of the CliffordSimp approach is never higher than the one of the SquashTK1 approach. 97 % of the compiled circuits exhibit a higher overall gate count as compared to the original circuits, as all transformed circuits ought to comply with the restricted native gate set N . However, the number of two-qubit gates in the transformed circuits never exceeds the count corresponding to the original circuit. The reason for this is that the original circuits contain some redundant CNOT gates, which can be removed after commuting the single qubit gates between them, and each remaining CNOT gate is substituted by exactly one ZZ gate using the decomposition from (10). Two of the five circuits with lower gate count after transformation are qft_10 and qft_16 which were transformed to empty circuits by the CliffordSimp approach as well as SquashTK1 approach.
The runtime of the CliffordSimp and SquashTK1 approaches versus the number of gates in the original circuit is shown in Fig. 15. The SquashTK1 approach lead to mostly constant compile time of about 1.35 ms Runtime t in milliseconds (a) In this benchmark our CliffordSimp approach was used. It can be clearly seen that the optimization leads to a non-linear runtime scaling.  per gate of the original circuit. In contrast to this, the CliffordSimp approach displays a non-linear growth of the compile time with the number of gates in the original circuit. The reason for this are the additional optimizations executed by Pytket's CliffordSimp pass, which lead to non-linear runtime requirement. Because this pass is not applied by the SquashTK1 approach and all other transformations passes described in this paper have a constant per-gate runtime while also iterating a fixed amount of times over each gate, the runtime scaling of the SquashTK1 approach is linear. The standard deviation for the largest 50 circuits it is strictly under 3 % of the average runtime.
The impact of different compilation stages on the result is depicted in Fig. 16. As a naive compilation, the gates of the original circuit are substituted by using Pytket's RebaseCustom pass as described in Sec. 4.4 and the ZZ decomposition given in (9) and (20). Af- terwards, the circuit is transformed to the restricted native gate set N . When comparing this naive transformation to our compiler, the resulting circuits of our compiler have 2.05 up to 5.38 times less single qubit gates and up to 1.60 times less two-qubit gates. On average our compiler produces the circuits which overall gate count is 3.22 times lower. This naive transformation determines for all evaluated circuits results with a 1.09 times lower gate count when not excluding the Ry from the native gate set before executing the RebaseCustom pass. This is the case because the naive transformation must not take care of commutations and including Ry gates allows to substitute the gates by shorter gate sequences. When comparing our compiler with the naive approach, but additionally removing trivial redundancies via the Pytket RemoveRedundancies pass, the compiled circuits have between 2.35 and 4.84 times less single qubit gates and up to 1.50 times less twoqubit gates. The overall gate count of our compiler is on average 2.80 times lower than the overall gate count of the improved naive transformation. These high factors show the potential of the optimizations our compiler applies. In the improved naive transformation for 98 % of the circuit the result have a lower or equal gate count when excluding the Ry gate from the native gate set before executing the RebaseCustom pass. The reason for this is that excluding gates from the native gate set reduces the number of different gates. Consequently, it is more likely that gates of the same type are next to each other allowing a better removal of redundancies.
In the next evaluation our compiler is executed as depicted in Fig. 3, but with skipping the phase tracking and block aggregation from Sec. 4.7 and Sec. 4.8, respectively. To compare the gate counts, for each circuit the approach (CliffordSimp or SquashTK1) which produces the lowest overall gate count after executing the whole compilation flow was used in all evaluations. If the CliffordSimp and SquashTK1 approach have the same overall gate count, the result with the lower two-qubit gate count was preferred. When comparing the whole compiler flow with the flow skipping these two optimizations, the complete compiler calculates circuits with an 1.35 up to 1.98 times lower single qubit gate count. Because the phase tracking as well as the block aggregation do not change the two-qubit gates, the two-qubit gate count stays the same. The overall gate count of the whole compiler flow is on average 1.59 times lower than in the case of the reduced compiler. Going in further details, in the following the phase tracking, but not the block aggregation is executed. In this case the overall gate count of the whole compilation flow is on average only 1.04 times and the single qubit gate count up to 1.11 times lower than the gate counts of the flow not executing block aggregation. The impact of the phase tracking and block aggregation on the single qubit gate count can be seen in Fig. 17. A compilation without phase tracking and block aggregation has an 1.35 up to 1.84 times higher single qubit gate count than the compilation with phase tracking. This shows that the large part of the improvements, which can be achieved after transforming the single qubit gates to the restricted native gate set N , is realized by phase tracking.
In the opposite case, where block aggregation without phase tracking is performed, the overall gate count of the whole compilation flow is on average 1.43 times and the single qubit gate count is between 0.88 and 1.73 times lower than the counts of the flow not applying phase tracking. While in the previous comparisons all circuits have better gate counts when executing our whole compilation flow, here is one circuit, graycode6_47 , which has a lower single qubit gate count when phase tracking is not applied. The reason for this is the construction of this circuit consisting only of CNOT gates. Consequently, this circuit directly provokes from the symmetric structure of the CNOT decomposition in (10) Fig. 18. This number grows with the number of single qubit gates.

Comparison to other compilers
We benchmark our compiler against built-in Pytket routines, using its FullPeepholeOptimise pass, which is a combination of Pytket's Clifford-Simp, RemoveRedundancies, CommuteThroughMultis, KAKDecomposition and EulerAngleReduction passes. Then, the circuits are rebased to {Rx, Rz, ZZ} using Pytket's RebaseCustom pass with the TK1 decomposition from (8a) and the CNOT decomposition from (10). After rebasing, the repeated removal and commutation of gates based on Pytket's built-in procedures from Sec. 4.2 is applied. As Pytket does not allow to restrict the gates of the native gate set to certain angles, it cannot directly transform the gates to the restricted native gate set N . To render the gate counts to be comparable, the transformation from Sec. 4.6 is applied to the circuit. For the Qiskit compilation, first the ZZ decomposition given in (9) and (20) is applied to C since Qiskit cannot transform ZZ gates with θ = π 2 already in C to ZZ gates with θ = π 2 and a set of single qubit gates. Afterwards, Qiskit's BasisTranslator pass is applied with the target basis {Rx, Ry, Rz, ZZ}. After rebasing, the transpile function of the Qiskit compiler module is executed with optimization level 3. Like Pytket, Qiskit cannot transform the gates to the restricted native gate set N , such that we employ Sec. 4.6 to obtain comparable gate counts. In addition to the standard passes of Pytket and Qiskit, we also benchmark against the Pytket extension pytket-aqt. Because this extension was developed for AQT's ion trap quantum computer, the native gate set supported by this extension is specified for this quantum computer and consists of the set {Rx, Ry, XX}. The circuits were compiled with optimization level 2 provided by the pytket-aqt extension using the sim device which is an ideal simulator of the AQT quantum device. Although the compiled circuits are in a different native gate set after compilation, the circuits were not transformed to the restricted native gate set N in this case. This allows the comparison of the optimization process of two existing ion trap quantum computer architectures. In comparison with the compiler of AQT, our compiler generates circuits with a lower or equal gate count in 96 % of the time. The gate counts of the circuits calculated by our compiler are reduced by a factor from 0.89 up to 1.31 compared to the results of the AQT compiler. For 97 % of the circuits our single qubit gate count and for 79 % our two-qubit gate count is lower than or equal to AQT's gate counts. The reduction of the single qubit gate count is given by a factor between 0.85 and 1.45, the two-qubit gate count reduction by a factor from 0.83 up to 1.20. Comparing the resulting circuits reveals that the difference in gates is in large parts due to our block aggregation (see Sec. 4.8). When not applying block aggregation, the overall and single qubit gate counts are only lower or equal in 89 % of the cases, while the ranges of the reduction factors do not change. The AQT compiler does not perform such a translation since their archi-tecture consists of one large ion chain and not several smaller chains stored at different trap segments. This difference in the target architectures and the resulting block aggregation technique seems to be the main reason for the different compilation results. Like our compiler, the AQT compiler reduces the circuits qft_10 and qft_16 to empty circuits. The runtime needed by our compiler is reduced by a factor of up to 12.47 compared to the AQT compiler. Compared to standard Pytket, our compiler can nearly always find a result with lower gate count in a faster time. In numbers, there are between 2.09 and 3.66 times less gates and a runtime reduction of a factor from 1.08 up to 11.18. Like in the comparison with the AQT compiler the circuits qft_10 and qft_16 are two exceptions because they can be reduced to empty circuits by our compiler as well as Pytket. A more detailed examination reveals that for all sample circuits our compiler produces results with 2.41 to 4.65 times less single qubit gates, while the two-qubit gate count is only for 81 % of the circuits up to 1.33 times less or equal. The comparison to the Qiskit pass shows that our compilation leads to 1.38 up to 2.21 times fewer final gates, when excluding the circuits qft_10 and qft_16 , which Qiskit does not reduce to an empty circuit in contrast to our compiler. Furthermore, when ignoring these two circuits, the single qubit gate count is between 1.55 and 2.41 times fewer for our compilation and the two-qubit gate count between 1.00 and 1.60 times, never being higher than for the Qiskit compilation. Regarding the runtime, for 90 % of sample circuits the Qiskit compiler is faster than our compiler by a factor up to 1.68. For the remaining 13 circuits -excluding the circuits qft_10 and qft_16our compiler is faster by a factor between 1.00 and 1.72. However, Qiskit's faster runtime is paid by a significantly larger number of gates. The gate count reduction that can be achieved by our compiler compared to AQT, Pytket and Qiskit is summarized in Fig. 19. The greatest reduction is achieved compared to Pytket with an average reduction factor of 2.75, followed by Qiskit with 1.68 and AQT with 1.08. As mentioned earlier, the latter is mostly due to the different quantum hardware architecture and is reduced to 1.04 when accounting for that effect. In the case of Pytket and Qiskit, our compiler always yields circuits with a lower gate count.

Conclusion and outlook
We have presented a quantum circuit compiler for a shuttling-based ion trap quantum computer that implements a number of optimization techniques like phase tracking and block aggregation to reduce the number of gates when compiling a quantum circuit into the native gate set. In comparison with other compilation algorithms, our Factor of gate count reduction AQT Pytket Qiskit Fig. 19: The factors of the gate count reduction of our compiler compared to AQT, Pytket and Qiskit. As our compilation result, the better of the two different rebasing approaches is chosen. The circuits are sorted by the number of qubits they operate on. For all circuits which reduction factor is over 1 (the horizontal black line) our approach with the lowest gate count produces a circuit with a lower gate count than AQT, Pytket or Qiskit.
compiler reduces the gate count by a factor of up to 1.31 (AQT), up to 3.66 (Pytket) and up to 2.21 (Qiskit). Also the runtime is reduced by a factor of up to 12.47 for AQT and up to 11.18 for Pytket. Qiskit has by a factor up to 1.68 shorter compilation time, but at the expense of a significantly larger number of gates.
In the future we plan to enhance the functionality of the compiler, to increase its performance using more advanced compilation techniques and to adapt it for more powerful architectures. One particular feature is the utilization of parameterized gates, which will allow the compilation of variational circuits such as the variational quantum eigensolver (VQE) [36]. The next architectural step will be the adaption to a platform for allowing simultaneous addressed manipulation of larger subsets of commonly confined trappedion qubits, where gates can be carried out in parallel. This will allow for low-resource quantum computation on sub-registers, interleaved with time-consuming register reconfiguration steps. Future multiplexed laser addressing units [37] will also allow for carrying out multi-qubit gates, such that e. g., three-qubit Toffoli gates can be realized within a single laser interaction sequence [38] rather than being decomposed into twoqubit gates. This can massively increase the quantum computational power of a trapped-ion platform, but also calls for an advanced compilation layer.  Qiskit  approach  approach  Name  q  1qg  2qg  1qg  2qg  1qg  2qg  1qg  2qg r_g  1qg  2qg r_g  1qg  2qg r_g