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RoC: A Scalable Network on Chip Based on the Token Ring Concept

A recent practice in the development of SoCs is the integration of interconnect networks, since integration offers significant bandwidth increases. This allows implementing multiprocessor systems that communicate more effectively than bus based architectures. This paper proposes a rotator-on-chip (RoC) architecture as a new network-on-chip based on the token ring concept. This scalable network has been integrated into a system level exploration platform for characterization. Increased performance is confirmed and improvements are proposed to decrease packet latency through the network. Results show that the RoC supports a working load of 82%, compared to 58% for the hot potato mesh network and 28% for the SPIN fat tree network