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System Verilog model design for AGC algorithm verification in SoC

In system-on-a-chip (SoC) design, mixed-signal verification is an important but complex process, especially the simulation of the analog part is often slow. The automatic gain control (AGC) algorithm, as a system algorithm, is used in the receiver channel of SoC to control the signal amplitude by adjusting the attenuation of the analog part and the digital part, so it is necessary to use the mixed-signal verification method when verifying the function of the AGC algorithm. To improve the simulation speed of the AGC algorithm, in this paper, the System Verilog models of the analog part are created for the receiver which include analog attenuator, analog peak detector (APD), and Sigma-Delta analog-to-digital converter (ADC). With the help of the proposed models, the mixed-signal verification of AGC can be achieved in an all-digital way and experimental results show that it is much faster than the traditional method using analog solvers.