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Optimizing selective decoupling capacitors by genetic algorithm for multiplayer power bus

How to effectively use the decoupling capacitors to mitigate power/ground noise on high-speed power delivery systems is investigated in this paper. The objective is to determine the minimum number of added decoupling capacitors and their position on the printed circuit boards (PCB). The genetic algorithm (GA) is employed to implement optimizing the accurate choice of the decoupling capacitors and quantities for a pre-defined power/ground noise specification. This can improve design efficiency to reduce the empirical or try-and-error design cycle, and has the advantages of cost reduction and less PCB layout area. In an example of the PCB with dimension of 27 cm by 15 cm, the minimum number of capacitor is five with a specified target impedance of 1Ω and the most effective location of decoupling capacitor is nearby the input port. It can estimate correctly the least number of capacitor used.