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Interconnect Design-Technology Co-Optimization for Sub-3nm Technology Nodes

Semi-damascene has been recently proposed as a candidate to replace dual-damascene for local routing layers in sub-3nm technology nodes. In this work, a block level design-technology co-optimization (DTCO) of semi-damascene is presented, evaluating the impact of different process options and design assumptions on performance, power, area and cost.Results show that semi-damascene not only outperforms dual- damascene in frequency and area, but it also provides a scalable path for further enhancements such as high density airgap and high aspect ratio wires, which promise even greater benefits.