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Comparison of Synchrophasor Estimation Methods in Simulation Environment and Real Hardware Implementation

This paper presents a description and performance comparison of two synchrophasor estimation algorithms proposed in the literature. The theoretical error performance is analyzed and compared with a practical implementation. Both synchrophasor estimators were implemented in a low cost hardware architecture proposed in the paper, with the purpose of showing the inherent estimator errors and the external error factors such as noise, quantization errors and sampling clock affected by jitter. In order to test the estimation algorithms, analysis under steady-state and dynamic conditions were performed. The tests were made under the conditions specified in the IEEE Standard C37.118.1-2011 and the total vector error of the algorithms was considered as the performance index. The studied and implemented algorithms were chosen by its nature, so one is based on frequency-domain analysis making an Interpolated-Discrete Fourier Transform and the other is based on time-domain analysis, implementing frequency mixing and a low pass FIR filter.