{'fraction_non_alphanumeric': 0.019169329073482427, 'fraction_numerical': 0.0010649627263045794, 'mean_word_length': 5.666666666666667, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function

This work presents an adaptation to the definition of the Integral Nonlinear Function (INLF) for distortion analysis of analog multipliers. Up to this time distortion in two-input multipliers has been evaluated by applying a constant signal to one of the inputs and verifying the linearity of the response with respect to the other input. This method however proves to be ineffective for assuring undistorted multiplying operation. Moreover, the conventional procedures, involving noisy and extensive AC measurements or FFT computation, are time-consuming and cumbersome, particularly if both multiplier input signals are taken into account simultaneously. Current-mode CMOS analog multiplier designs are simulated and analyzed concerning distortion by means of the proposed figure of merit (2D-INFL) and through a conventional procedure.