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A pulse-frequency-modulation vision chip using a capacitive feedback reset with an in-pixel 1-bit image processor

We report a low-voltage digital vision chip based on a pulse-frequency-modulation (PFM) photosensor using capacitive feedback reset and pulse-domain digital image processing to explore its feasibility of low power consumption and high dynamic range even at a low power-supply voltage. An example of the applications of the vision chip is retinal prosthesis, in which supplied power is limited. The pixel is composed of a PFM photosensor with a dynamic pulse memory, pulse gates, and a 1-bit digital image processor. The binary value stored at the dynamic pulse memory is read to the 1-bit digital image processor. The image processor executes spatial filtering by mutual operations between the pulses from the pixel and those from the four neighboring pixels. The weights in image processing are controlled by pulse gates. We fabricated a test chip in a standard 0.35-μm CMOS technology. Pixel size and pixel counts were 100 μm sq. and 32 x 32, respectively. In the experiments, four neighboring pixels were considered in image processing. The test chip successfully operated at low power supply voltage around 1.25 V. The frame rate was 26 kfps. Low-pass filtering, edge enhancement, and edge detection have been demonstrated. Relationships between power supply voltages and characteristics of the vision chip are investigated.