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Designing pipelined systems with a clock period approaching pipeline register delay

A novel mesochronous pipelining scheme is described in this paper. The clock period in the proposed pipeline scheme is determined by the pipeline stage with largest difference between its minimum and maximum delays. This is a significant performance gain compared to conventional pipeline scheme where clock period is determined by stage with the maximum delay. Also, in the proposed scheme the number of pipeline stages and pipeline registers is small and the clock distribution scheme is simpler. An 8 times 8-bit carry-save adder multiplier has been implemented in mesochronous pipeline architecture using modest TSMC 180 nm. The multiplier architecture and simulation results are described in detail in this paper. The pipelined multiplier is able to operate on a clock period of 350ps (2.86GHz), with fewer pipeline stages and pipeline registers