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An ultra low power 130nm CMOS direct conversion transceiver for IEEE802.15.4

A fully integrated 2.4 GHz transceiver based on the IEEE802.15.4 specification has been designed using a 130 nm CMOS technology. Concurrent system and design optimizations were required to reach an energy efficiency of 21.5 nJ/bit in RX mode and 32.5 nJ/bit in TX modes, respectively, at a data rate of 250 kbit/s. The circuit includes a -5 dBm transmitter, a -81 dBm sensitivity receiver, an integer N PLL with 5 MHz reference, a dual I/Q 3-bit ADC at 4 MS/s, an analog RSSI with 8-bit ADC at 8 kS/s and an integrated SPDT TX/RX switch to a 100 Omega differential antenna port. The chip consumes 5.4 mW in RX mode and 8.1 mW in TX mode under 1.2 V.