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Programmable Synaptic Chip for Electronic Neural Networks

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32×32 array of "long channel" NMOSFET binary connection elements implemented in a 3-um bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a "cascadable" building block for a multi-chip synaptic network as large as 512×512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silcon area. The performance of a synaptic chip in a 32- neuron breadboard system in an associative memory test application is discussed.