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PLL based implementation of a PMU

We describe the implementation of a single-phase estimation algorithm for phasor measurement unit (PMUs) compliant with the IEEE C37.118.1-2011 standard. It consists of three stages: The fist one is a bandpass FIR filter that allows the relaxation of the requirements of the following stages. The second one is a digital extension on state-space of the pseudo-linear enhanced phase locked loop (PL-EPLL) used for tracking the amplitude, phase, frequency and ROCOF of the input signal. The third stage compensates the FIR filter effects on the signal of interest. The algorithm performance is analyzed on an embedded implementation for ARM Cortex-M3 processors, discriminating the computational cost per stage. Lastly we present a concurrent multichannel implementation, focusing on the synchronization of the reporting times.