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Zero Aliasing Space Compaction with Cellular Automata

Complex integrated circuits produce voluminous test response data. Space compaction reduces the space requirement to store the response data by combining circuit outputs in certain fashion to reduce the number of outputs to be observed. In this paper, we present the design of a zero-aliasing space compactor that utilizes the theory of Cellular Automata based pattern classification to classify the fault-free and the faulty responses. Experimental results with the ISCAS85 benchmark circuits show that the scheme results in 1.26 time more compaction over the earlier zero-aliasing space compaction strategies. Area overhead of the proposed scheme is also much lesser.