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Geometric Influence of High Curvature on the Performance of Thin Film Transistors

The development of thin film transistor (TFTs) based integrated circuits on flexible substrates promise interesting approaches to human interface systems. Recently TFTs have been fabricated on textured surfaces such as textiles, paper, artificially corrugated or dimpled substrates, threads and fibers. This can result in the TFTs metal-insulator-semiconductor (MIS) stack being significantly distorted from a planar zero-curvature geometry to having non zero and potentially high curvature. Although the direct deposition on textured surfaces do not result in mechanical stress (as for example in bending, buckling or wrinkling), the geometry of high curvature can significantly influence the current voltage characteristics of the TFT. Here we present a closed form analytical model describing the geometrical impact of high curvature on the electrical performance of the TFT. Models are obtained from the solution to the Poisson-Boltzmann equation in polar co-ordinates and are verified using TCAD simulations. The techniques to generalize the results to adapt to any texture and semiconducting material are also discussed with experimental verification. This work forms an analytical basis to understand the impact of curvature on the electrostatics of the MIS stack and the current voltage characteristics of the TFT.

High curvature geometry of the MIS stack results in changing the gate electric field distribution from nearly uniform to non-uniform. The importance of geometry on the performance of TFTs is seen from experiments performed on TFTs deposited on artificially engineered rough surfaces [33][34][35][36]. In these experiments, the gate metal of the TFT was undulated in both convex and concave fashions by the use of corrugations or dimples. Since the semiconductor and insulator were deposited conformably on top of this gate metal, the MIS stack did not experience mechanical stress and only experienced the effect of curvature. Experiments showed significant variations in electrical performance in the TFT thereby defining the role of geometry alone to be significant in itself. Corrugated gate a-Si:H TFTs showed almost 200-300% increase in transconductance as compared to planar TFT [33]. Upto ±40% variation in transconductance was observed depending on the texture orientation as compared to conventional planar gate TFTs in a-Si:H technology. Demonstrations of high gain common-source amplifiers using textured TFTs have also been reported [35]. Patterning the gate with dimples in organic (P3HT) TFTs showed almost 400% improvement in current [34]. Therefore, the geometrical impact of curvature on the performance of TFTs is important.
The aim of this work is the development of an analytical model to explain the purely geometrical impact of curvature on electrostatics of the MIS stack and the performance of the TFT. This is accomplished by obtaining the closed form solution to the Poisson-Boltzmann's equation in polar coordinates for positive and negative curvature. We demonstrate the occurrence of a pleasant symmetry in the positive and negative curvature case with the TFT chracteristics being strongly determined by the effective gate capacitance. Models are compared to TCAD simulations and then generalized and compared with experimental data for a corrugated gate TFTs.

Device Physics
The disordered nature of the semiconductor in a TFT results in the appearance of localized states in the energy bandgap. These can be classified as deep states that are present around midgap and tail states that are present close to the mobility edge. In most inorganic disordered semiconductors (eg. amorphous hydrogenated silicon (a-Si:H) [48], amorphous metal oxides [49]), the states in the gap are observed to have an exponential distribution with energy.  For this analysis, we consider n-type TFTs with the electrostatics defined by the Poisson equation as ∇ 2 ϕ = q(n t + n f )/ s where ϕ is the potential profile in the semiconductor measured with reference to the back channel (bulk) potential, q the magnitude of the electron charge, s the semiconductor permittivity and n t , n f are the trapped and free carrier concentration, respectively. To simplify the analysis and preserve physical intuition we represent the contribution of traps at all energies and the effect of the free carrier concentration by defining an effective carrier concentration, n e , and an effective characteristic voltage, φ e , and write the Poisson equation as with n e0 being the effective carrier concentration at flat band. The parameters n e and φ e are influenced by the trapped and free carriers and tend to take values of the specie dominating the physics. This simplifies the analysis without much loss of accuracy and is justified by the simulations and experiments. Although the electrostatics of the device is determined by n e , the current voltage (IV) characteristics is determined by the free carrier concentration, n f .

MIS Geometry
The geometry of the MIS structure used for analysis is shown in Fig. 1. The MIS has an insulator of thickness t i and semiconductor of thickness t s . We define the radius of curvature of the insulator-semiconductor interface to be r si . For zero curvature the MIS stack is planar, r si = ∞ and a Cartesian coordinate system (x, y) is used for analysis with the vector x pointing along the direction from the insulator-semiconductor interface (x = 0) to bulk. When the MIS stack has curvature, a polar coordinate system (r, θ) is used. The curved MIS stack is said to be concave or convex as shown in Fig. 1.
For simulations the arc length of the insulator-semiconductor interface was always kept constant.

Insulator Capacitance Per Unit Area
We also define an effective insulator capacitance per unit area C i0 for the MIS stack with zero curvature, C i+ for the case of concave curvature and C i− for the case of convex curvature. It is seen that, C i0 = i /t i , C i+ = i /(r si ln(r si /(r si − t i ))) and C i− = i /(r si ln((r si + t i )/r si )), where i is the insulator permittivity.

Zero Curvature (or Planar)
We first consider the case when the MIS stack has no curvature. This case has been very well investigated [50]- [51]. Poisson's equation is given by (1) and is solved to identify the electrostatics. Using the boundary condition ξ = 0 at ϕ = 0 and defining a characteristic length l e = ((2 s φ e )/(qn e0 )) 1/2 , the electric field (ξ) in this case can be shown to vary as Defining the surface potential ϕ(x = 0) = ϕ s , the second boundary condition can be set as C i0 (V gs − V f b − ϕ s ) = s ξ(ϕ = ϕ s ), with V f b being the flat-band voltage and V gs the gate to source voltage. In strong above threshold operation with e ϕs/φe >> 1, the solution to the boundary condition is given in terms of the zero order Lambert-W function, W 0 , as Here, the term s /l e can be imagined to be a characteristic trap capacitance per unit area. The approximated form of the above expression is obtained by approximating W 0 (.) = ln(.) − ln(ln(.)) for large V gs [52]. The potential profile, ϕ(x), is obtained using (2) along with the boundary condition ϕ = ϕ s at x = 0,

Non Zero Curvature
In the presence of curvature, r si is finite and the Poisson equation can be defined in polar coordinates (r, θ) as, From the derivation shown in the Supplementary Information, the radial variation of the potential is of the form Here κ is a dimensionless coefficient and l b is a characteristic length. The radial component of the electric field can be shown to vary as with the + for the concave case and − for the convex case. At r = r si , ϕ = ϕ s with ϕ s being the surface potential. This sets the boundary condition , with the + for the concave case (ϕ decreases as r increases) and the − for the convex case (ϕ decreases as r decreases). Again considering strong above threshold operation, e ϕs/φe >> κl e /r si , the solution to (7) can also be presented using the Lambert-W function as was done in the planar case as, Therefore, for all practical purposes the impact of the geometry of curvature on TFT performance is dictated through the cylindrical capacitive component defined by C i± . This model for ϕ s is validated by a good match with simulations.
To obtain a good numerical estimate for complete variation of ϕ(r) as well as the surface potential, ϕ s , we impose another boundary condition permitting the bands to flatten at the back edge of the MIS capacitor. Therefore, ξ(r = r si ± t s ) = 0 and ϕ(r = r si ± t s ) = 0, with the + for the concave case and the − for the convex case. This condition helps identify the parameter κ to be Here the + and − signs are used for the concave and convex cases, respectively. Typically l e ∼ 60 nm and t s ∼ 100 nm and despite the high curvature under consideration, r si is expected to easily exceed these values with it taking a minimum value of about 200 nm for this study. Using the parameter κ in (6) and setting ϕ = ϕ s at r = r si , we can identify the parameter l b . This permits a closed form expression for ϕ(r) as, The function sec −1 yields both negative and positive values for the same argument. The positive and negative values are appropriate for the concave and convex case, respectively. This is enforced as shown in (10). The models developed for the bending case (r si < ∞), must converge to the corresponding models for the planar case (r si = ∞), as r si is increased. This is verified in Appendix I.

Zero Curvature (or Planar)
For a TFT with an applied drain to source bias voltage, V ds , the model for ϕ s still retains its form (Eq. 3) except for the incorporation of the threshold voltage term, V T 0 , and a channel potential term, ). The free electron density per unit area, N f is computed by integrating the free electron concentration per unit volume, n f , along the thickness of the semiconductor, so that where, α = 2φ e /φ th and γ = (n f 0 (qn e0 l e ) 2−α /(n e0 (α − 1))) with φ th being the thermal voltage. Therefore, the I-V characteristics in above threshold operation when the TFT has no curvature can be shown to be with µ 0 being the band mobility, W the channel width and L the channel length.

Non Zero Curvature
With curvature, the change in the effective insulator capacitance per unit area from C i0 to C i± also changes the threshold voltage from V T 0 to V T ± as threshold voltage is the ratio of the trapped charge to the insulator capacitance per unit area. Therefore, the I-V model for the case with the TFT experiencing curvature (details in Supplementary Information) is given by, with the + for the concave case and the − for the convex case. Therefore, the difference of the I-V characteristics in the zero and non-zero curvature case is primarily due to the difference in the effective capacitance per unit area. The IV model can be calibrated for TFTs with different materials by suitably changing the parameters γ, α, µ 0 and V T . Free or trapped carriers which will dominate the electrostatics in the above-threshold region is dictated by the values of α and γ.

Setup
To validate the models, ATLAS TCAD simulations on cylindrical metal-insulatorsemiconductor TFTs were performed. Planar, concave and convex geometries were designed with 100 nm SiO 2 insulator, 100 nm a-IGZO semiconductor and Mo gate metal. The default material properties as defined in the simulator were used for the a-IGZO (electron affinity=4.16 eV, electron band mobility = 15 cm 2 /Vs). The DoS used is as shown in Fig. 2a [49,51,53]. Simulations for MIS with bending were performed for r si /t i = 2, 4, 7, 10, 15, 25, 35, 50. For MIS simulations the source and drain were  (4) and (10), with the inset showing the variation near the interface, (c) Comparison of the electric fields along mid-channel, source edge and drain edge (differentiated by symbols and dashed lines) for different geometries (differentiated by colours) at a channel length L = 4 µm. For TFTs with curvature, r si /t si = 10. All the TFTs were biased at V gs = 10 V and V ds = 0.1 V, (d) variation of surface potential with V gs at r si /t i = 2, (e) variation of surface potential with r si /t i using models (3) and (8), (f) variation of n f at interface (given by n f 0 e ϕs/φ th ) as a function of r si /t i . grounded and the arc length of the semiconductor-insulator interface was 1.2 µm for all structures. For TFT simulations, the arc length of the semiconductor-insulator interface was 4.2 µm, the channel length was 4 µm (large enough to reduce drain induced barrier lowering) and r si /t i was 7 for all geometries.
The measurement of ϕ(r) was done using a precisely defined cut-line. A fine mesh was used in the semiconductor while keeping the number of mesh points constant for the different structures for the sake of accuracy. As the influence of the gate voltage at the back channel was negligible, ϕ s was measured by precisely probing and calculating the difference between the potentials at the interface and the back channel.   11) and (12)) with TCAD simulation. Bold line indicate models and markers indicate simulated data.
The values for n e0 ∼ 8 ± 0.1 × 10 15 cm −3 and φ e ∼ 25.8 ± 0.7 mV were estimated by best fit between the model of (3) and simulation for the case of zero curvature. In the case of IGZO TFTs, calculation of n f and n t using methods described in [54] shows that n f is slightly greater than n t in the above-threshold operation. Therefore φ e is expected to be close to the thermal voltage as corroborated by a good match between analysis and simulation. These parameters were also used for the case of non-zero curvature to obtain good corroboration between model and simulation.
Using the models described in (3) and (8), the surface potential of planar, concave and convex TFTs were compared against simulations. The spatial variation of the potential inside the semiconductor for the case of non zero curvature was calculated using (10). Fig. 2(b) and Fig. 2(c) show the spatial variation of ϕ and the electric field (at V gs = 10V) while moving from the semiconductor-insulator interface to the bulk. The electric field was probed along three cutlines directed radially from the interface towards the bulk at the -mid-channel, edge of source terminal and the edge of drain terminal. Simulation results reveal that the influence of curvature on the electric-field along the three cutlines follow a similar trend for TFTs having L > 4 µm (both markers and dashed lines indicate simulations). This justifies the modeling of the electrostatics of the TFT using the polar Poisson-Boltzmann equation as described and without requiring any consideration with regards to the location along the channel length as the source drain edge does not have any different influence with regards to the general trend. Fig. 2(d) and Fig. 2(e) show the plots of ϕ s vs V gs (for r si /t i = 2) and ϕ s vs r si /t i (at V gs = 9V), respectively. As predicted by the model, the convex TFTs are observed to have a higher ϕ s as compared to planar devices while the concave TFTs have a lower ϕ s as compared to planar TFTs for the same applied gate bias. As discussed, this is attributed to the variation in effective insulator capacitance per unit area. As r si increases, ϕ s of the TFTs with curvature approach the case of TFTs with zero curvature. Therefore, although geometry has an impact for any curvature, the influence becomes significant (>10%) only when the r si /t i < 20. This degree of curvature would appear when the substrate or MIS stack buckles, wrinkles or if the TFTs are deposited on fibers. Fig. 2(f) shows n f (ϕ = ϕ s ) as a function of r si /t i at V gs = 9V. Here, n f 0 ≈ 6.2×10 15 cm −3 . The model and simulations once again show a reasonably good fit. At a given V gs free electron concentration is higher for the convex curvature case as compared to the zero curvature case. On the other hand, the free carrier concentration for the concave curvature case is lower as compared to the zero curvature case. As expected, this follows a trend similar to ϕ s and is strongly dictated by the variation in gate capacitance. Fig. 3 compares the transfer and output characteristics for TFTs with zero curvature, convex curvature and concave curvature cases (r si /t i =7). At low channel lengths (≤ 2 µm), drain induced barrier lowering was observed. Hence the simulations were performed using a channel length of 4 µm to study the impact of curvature. The threshold voltage values used to fit the simulated data are V T 0 = 0.04V, V T − = 0V, V T + = 0.15V. The models based on 12 are compared with simulations and show a reasonably good fit. The best fit was achieved for γ = 1 and α = 2, which indicates the domination of free carriers in the above threshold regime.

Application to Experiment and Generalizations
In this section we detail how the analytical models described above can be used against experiments performed with TFTs of different materials and different surface curvatures. As a test example, we consider previously reported experimental data for an artificially corrugated gate a-Si:H TFT, whose schematic is given in Fig. 4(a) [33].

Generalizations Regarding Geometry
As seen in Fig. 4(a), the architecture of the MIS stack is more complicated than a simple curved surface. Such a corrugated architecture can be expected when developing TFTs on fabrics without full planarization. To apply the models described in this work, we would first need to break down the geometry into surfaces of convex, concave and zero curvature. The cross-section of the corrugated TFT of Fig. 4(a) can be considered to be composed of exactly such a combination of planar, concave and convex TFTs, with spatially varying radius of curvature. If we define y-direction to be along the channel length the z-direction be along the channel-width, the drain current per unit width is given by qN f (y, z)µ 0 (dV ch /dy). Substituting for N f from the models developed earlier, I ds /dz = γµ 0 [(C i(0,±) (V gs − V T 0 − V ch ))] α−1 (dV ch /dy). The term γµ 0 can be considered to be the effective mobility. The term C i(0,±) takes on its appropriate values (with subscript 0, + or -) in the corresponding regions (of zero, concave or convex curvature, respectively). For simplicity, the threshold voltage is kept constant. Since the corrugations stretch from source to drain and are parallel to each other and to the direction of the channel lengt, the capacitance varies spatially as we traverse the direction of the channel width and remains constant as we traverse the channel length. The TFT is thus considered to be a parallel combination of TFTs with different gate capacitance and of width dz. Integrating the above expression along the length from y = 0 to y = L and then along the channel width from z = 0 to z = W , If the capacitance were to be a continuous function it could be directly integrated in the above expression. However for the case of Fig. 4(a), the geometry and the corresponding value of the capacitance needs to be handled piece wise based on the three periodically repeating regions the concave, the convex and the planar. The geometrical parameters influencing capacitance, insulator thickness, height of the side wall, corrugation pitch, radius of convex (20 nm) and concave (120 nm) regions, were extracted (likely or approximate values) from the SEM image of the cross section shown in Fig. 4(b). The integral W 0 C α−1 i(0,±) dz was estimated by the piece-wise summation of the separate capacitances.
Although not used in the case of Fig. 4, the current voltage characteristics when the corrugations are parallel to the channel width can be shown to be I ds = (γµ 0 W/α)(

Generalizations Regarding Materials
Before computing the current, it is also important to consider the material used for the TFT. While the simulations were performed using a-GIZO TFTs, the experiments of Fig. 4 use a-Si:H as the semiconductor. The material properties would be reflected in the values of parameters α = 2φ e /φ th and γ = n f 0 (qn e0 l e ) 2−α /(n e0 (α − 1)) with l e = (2 s φ e /qn e0 ) 1/2 . The value of φ e depends on the region of operation and takes into account the cumulative effect of free carriers and trapped carriers (to aid a single exponential based Poisson equation). The dominant of the two will define φ e . If the free carriers dominate, φ e = φ th ≈ 25.8 mV at 300 K. In a-Si:H, the acceptor like tail states have a characteristic temperature of 325 K and hence a characteristic voltage of about 28 mV [48]. Therefore, in above threshold operation in a-Si:H TFTs, φ e can be expected to take on a value between 25.8 mV and 28 mV. For modeling the experimental data of Fig. 4, we define φ e ≈ φ th . Therefore, α ≈ 2 and γ ≈ n f 0 /n e0 .
The parameter n e0 also takes into account the cumulative effect of free carriers, n f 0 , and trapped carriers. In a-GIZO, the free carriers dominated the trap carriers and n f 0 = n e0 and γ = 1. In a-Si:H [48], the carriers in tail states are quite significant and define n e0 . In a-Si:H, with the band gap of 1.8 eV, effective density of conduction band states of 2.5e20 /cc, exponential acceptor like tail states with density at conduction band mobility edge and characteristic energy of 1e22 /cc and 0.028 eV respectively, acceptor like deep states with density of 1.5e15 /cc at energy 0.62 eV below conduction band mobility edge and with flat band defined at the point when the fermi level is 0.76 eV below the mobility edge, γ = n f 0 /n e0 ≈ 0.02.
The parameter γ can be used to compute the effective mobility. With a band mobility in a-Si:H being µ 0 =20 cm 2 /Vs, the effective mobility is γµ 0 ≈ 0.4 cm 2 /Vs.

Model Parameters and Comparison with Experiment
Based on the above discussion, the values for model parameters used to fit the experimental data are µ 0 = 0.44 ± 0.13 cm 2 /Vs, i = 7.5, γ = 1, α = 2, V T 0 = 3.5 ± 1 V. The model was also corrected for leakage currents as reported in [33]. Fig. 4(c)-(e) show good fitting between the I-V models (bold line) and the experimental data (markers) given in [33]. For best fit µ 0 =0.31 cm 2 /Vs was chosen for Fig. 4c and µ 0 =0.57 cm 2 /Vs was chosen for Fig. 4d and Fig. 4e.

Conclusion
This work presented a closed form analytical model describing the geometrical impact of high curvature on the electrostatics of the MIS stack and the performance of the TFT. The models for TFTs experiencing curvature were obtained from the solution to the Poisson-Boltzmann equation in polar co-ordinates. These models were compared with the case of planar TFTs having no curvature and verified using detailed TCAD simulations. The methods to generalize the results was also discussed using the example of corrugated a-Si:H TFTs. This work forms an analytical basis to understand the behavior of substrate geometry on TFTs, for example with regards to TFTs deposited on rough or textured surfaces such as textiles or paper, surfaces with high curvatures such as fibers or wires and on substrates experiencing buckling, wrinkling or significant bending.
case approaches the field at the interface in the zero curvature case. Next, considering the spatial variation of ξ and ϕ we note that the polar coordinate system (r, θ) maps to the Cartesian coordinate x as x = ±(r − r si )cos(θ) with the interface at x = 0 and r = r si . As all parameters in the non-zero curvature case are invariant with θ, we set θ = 0 and use r = r si ± x in (7) and (10). As r si becomes very large, firstly κl e ≈ r si , secondly l e << r si and finally since x spans from 0 to t s , x/r si << 1. Therefore, r si /(r si ± x) ≈ 1 and κln(1 ± (x/r si )) ≈ ±κx/r si = ±x/l e . Using r = r si ± x along with these approximations we find that (7) and (10) converge to (2) and (4), respectively.