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Implementing image processing algorithms in FPGA hardware

This paper describes an efficient FPGA based hardware design for different image processing, enhancement, and filtering algorithms. FPGAs are often used as implementation platforms for real-time image processing applications because their structure is able to exploit spatial and temporal parallelism. The approach used is a windowing operator technique to traverse the pixels of an image, and apply the filters to them. As image sizes bit depth grow larger, software becomes less useful and real-time hardware systems are needed to take their place. The results are obtained for image size of 585×450, but the approach discussed can be used for images of any size, as long as the FPGA memory will hold it. The implementation was created with the Xilinx Spartan-6 FPGA on a Nexys3 board in mind.