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An ultra-low voltage hearing aid chip using variable-latency design technique

This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 μW at 0.5V and 6 MHz