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Frequency domain testing of general purpose processors at the instruction execution level

In this paper, we put forth a novel frequency domain BIST approach towards instruction execution level testing. This BIST scheme employs number theoretic transform to obtain the spectrum of the control sequences (generated by the processor control unit, the Finite State Machine) of the instructions during execution to detect stuck-at and transient faults and weak logic signals. The scheme involves four level logic to detect weak-0 and weak-1 logic signals. Weak signals lead to degradation of the noise margin, particularly in DSM technology based multi-GHz processors. This novel concept is verified by simulation using FSM benchmark circuits. The four level logic has been successfully simulated in Spice, and the results have been presented. Near 100% fault coverage has been achieved. The overall functioning of this test scheme to detect transient faults and signal integrity faults is also shown.