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Validation of an SRAM Power Model for Architecture Level Power Estimation

As power consumption is becoming a more important issue, several power estimation tools have been proposed. However, effectiveness of a power model is not really known without validating it against a real design. In this work, we validate a recently developed architecture level power estimation tool, PRESTO, against our SRAM design. This tool offers flexibility to adapt to various process technology, through the use of SPICE parameters and metal process parameters to calculate circuit’s parasitic capacitances. Our validation shows that the model gives reasonable accuracy for relative power estimates, but still shows discouraging results for absolute power estimates.