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A Modified Full Adder (MFA) with an introverted unique Design for Low Power VLSI Circuit Applications

The design of low-power devices is ruling the electronics era. The dissipation of power is one of the needed parameters for estimating the performance of the power devices in VLSI circuits. The size of the chip and the design methods are responsible for the generation of low-power devices. In this work, a modified form of the full adder (MFA) is designed by using CMOS gates. For implementing this adder CMOS logic is combined with the Transmission gate logic. The implemented modified full adder (MFA) is a 1-bit adder that consists of an inverted XOR module, NOR module, and sum generator module. The propagation delay is marked to be 15ns which is very low and the power consumption of the circuit is 6.344 μW at 1 volt supply voltage. Hence in the proposed MFA, the product power delay is identified to be 124.63fJ. Only 12 transistors are used in the proposed design. The obtained results show that the new design produces better results in terms of power delay and hence will perform better when used in VLSI circuits.