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Modeling of polysilicide gate resistance effect on inverter delay and power consumption using distributed RC method and branching technique

Two parameters that contribute significantly in a CMOS inverter delay are the output load and propagation of the control signal across the gates of its transistors. The latter one which is due to the polysilicide gate resistance (PGR) is proportional to the gate width, W. The PGR effect causes the inverter transistors remain simultaneously on, for further time in the saturation region during transient instants, so that the short circuit power consumption increases largely. In this paper, we model the PGR resistance effect using the distributed RC approach based on a new proposed technique. Additionally, in order to reduce its negative impact on the circuit performance, we utilize a relevant optimized branching method. The results obtained from our model compared to the HSPICE simulation results verify a good agreement. Furthermore, our modeling technique can be implemented as a CAD tool for a primary estimation of the delay and the power consumption in complex circuits while retains an acceptable accuracy.