{'fraction_non_alphanumeric': 0.009615384615384616, 'fraction_numerical': 0.0, 'mean_word_length': 6.009615384615385, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Relevance of electromigration wafer level test for advanced CMOS interconnects reliability control

The work presented in this paper compares electromigration results from standard wafer level and package level tests. Dual damascene low-k Cu lines with different processes have been tested and correlation between both testing methods is evaluated. Results from wafer level reliability and package level reliability are compared around lifetime variations and standard deviation. Only limited correlation is found, strengthening the need of defining new reliable electromigration testing methods compatible with an industrial environment. Comparison between failures mechanisms involved in each testing method is also addressed.