{'fraction_non_alphanumeric': 0.019184652278177457, 'fraction_numerical': 0.004796163069544364, 'mean_word_length': 4.9714285714285715, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
FPGA prototyping of an ASIP LDPC decoder for the DVB-T2 standard

Forward Error Correction (FEC) consists in the addition of redundancy to the binary information sequence before the transmission. This redundancy allows the FEC decoder to detect and/or to correct the effects of noise and interference encountered during the transmission. An ASIP LDPC decoder compliant with DVB-T2 standard is presented in this paper.