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Local Layout Effect Impact to Single Device in SRAM 6T Cell

As CMOS scaling extends into the Nano scale tech-node, designers need to not only pay attention to the device behavior impact by traditional geometric parameters, such as channel length and width; but also need to be aware on layout implementation details of the device and its surrounding neighborhood. Static Random Access Memories (SRAM) 6T cell is a basic circuit constitute by six single device, including two PMOS and four NMOS. Large SRAM arrays are widely used as cache memory in electric industries and can be applied to monitor process quality and stability in manufacture process. The device performance of single device in SRAM 6T cell determined whether a SRAM cell can function, and seriously influenced the read/write margin of it. As the single device in SRAM 6T cell up against complicated layout surroundings, their performance is largely independent of the neighborhood environment. In this paper, we will focus on three types of local layout effect to SRAM single device, including NW size effect, metal boundary effect and gate extension AA size effect. The change mode of device in SRAM circuit is analyzed and mechanisms is investigated to explain them.