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Modeling the Dynamic Variability Induced by Charged Traps in a Bilayer Gate Oxide

In this paper, we revisit the classic single layer defect centric model (DCM), largely used in reliability studies, in the more realistic case of bilayer gate oxide transistors integrating an interface layer and a high-K dielectric. The Monte Carlo method and 3-D electrostatic simulations are used to determine the impact of the traps present in both layers on the Vt of transistors. It is proved that the DCM is able to capture the trap-induced variability of bilayer transistors but with effective model parameters, which have no more a true physical meaning as in the case of the single layer gate oxide. An extended DCM, accounting for a two trap distributions, is then proposed to better explain the degradation measured on bilayer transistors. Finally, this extended DCM finds another application in the evaluation of the bias temperature instability-induced variability of static RAM cells.