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Charge loss activation during non-volatiles memory data retention

In this paper we develop a method to study and to activate charge loss in a Non-volatile Memories array. We first detail an original date retention test under gate stress on a simple and statistical tool. Then we present the experimental results we obtained after more than 700h at 85°C and 150°C, for six different gate stress conditions. Finally, we extract the activation energy for the observed charge losses, using to different approaches, leading to a discussion on the extracted values and to perspectives for this work.