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SPICE parameter extraction and RO validation of a 65nm SOI technology

Accurate extraction of the SPICE model parameter is critical in the CMOS IC design. However, it faces difficult issues in state-of-the-art MOSFET technology. First, the gate CV parameter extraction is challenging due to small values and many extrinsic components that need to be de-embedded. Second, the systematic offset of the gate critical dimension (CD) exists between test structures and circuits, introducing a significant uncertainty. Thus, it is not uncommon that the validation of a circuit-level SPICE model involves arbitrary adjustments of capacitance parameters that undermine the confidence level of the model parameters. This paper presents seamless methodologies to resolve these issues. Circuit-level validation of the methodology is given for 65nm PD-SOI ring oscillators (ROs), covering a wide range of simulation conditions.