{'fraction_non_alphanumeric': 0.016129032258064516, 'fraction_numerical': 0.02043010752688172, 'mean_word_length': 5.125, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
FPGA Implementation of Fault Tolerant & High Speed Reversible Systolic
Multiplier

Multiplier is one of the essential components in the digital world such as in digital signal
processing, quantum computing, microprocessor and widely used in arithmetic unit. The Reversible
rationale is a used to decrease heat scattering and data misfortune. Contrasted with all essential math
activities, multiplication requests all the more preparing time and look for complex equipment. This
paper presents a plan of low power Systolic Array Multiplier utilizing Reversible logic gates which
performs information handling in parallel. In this paper, we present a high speed 4x4 Systolic
Multiplier design by using peres gate and toffoli gates and source code written in verilog and also
implemented on FPGA Spartan 3s50pq208-4. The synthesis and simulation is done on Xilinx ISE
14.7. The delay is 17.642ns and static power dissipation is 24mW.