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A Layout Methodology For The Synthesis Of High Speed Global Clock Nets

Clock distribution in chips is important. Its importance becomes harder to overlook as the system being designed uses higher clock frequencies and larger number of flip-fiops, and requires careful system partitioning into several chips and fabrication in Multi-Chip Module. In this scenario where several chips are treated as synchronous islands, we will be concerned not only with reducing intra-chip skew but also with minimizing interchip delay. Related topics of this paper are system partitioning, high performance system, clocking schemes, clock distribution structures, clock synthesis and layout, buffer design, boundary scan test, intra-chip skew minimization, and inter-chip synchronization.