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A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects

For optimizations like placement, interconnect synthesis and static timing analysis, efficient interconnect delay computation is critical for RC networks. Because of its simple closed form and fast evaluation, the Elmore delay model has been widely used. The other delay metrics PRIMO and H-gamma match the first three circuit moments to the probability density function (PDF) of a Gamma statistical distribution. Although these methods demonstrate impressive accuracy compared to other delay metrics, their implementations tend to be challenging. In this paper simple and efficient two-parameter analytic expressions for both delay and slew, based on Erlang distribution (ERD) function, are presented under process variations. The effectiveness of the proposed metrics for RC trees is proved through experimental results.