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High-speed image composition with enhanced multiplier structures

Describes an efficient implementation of a fused multiplier-adder-subtracter circuit for image composition. An enhanced multiplier structure achieves high-speed composition with virtually no additional hardware or latency over that of a conventional multiplication cell. Expansion of the multiplier partial product matrix permits the parallel addition of multiple terms without the intrinsic delay incurred with a carry propagation. A modified encoding paradigm allows "on-the-fly" term negation to realize subtraction. An optimal design strategy for carry-save adder arrays performs carry-propagation addition in parallel with reduction of the partial product matrix. The proposed fused-cell architecture is general enough to support a variety of custom functions and exceeds the performance requirements of a full-frame real-time image generation system.