{'fraction_non_alphanumeric': 0.03513150316759455, 'fraction_numerical': 0.016061944071158893, 'mean_word_length': 4.495077355836849, 'pattern_counts': {'":': 0, '<': 4, '<?xml version=': 0, '>': 2, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Integrated CMOS edge voltage quantizer for detection of low-frequency simple waveforms

A novel edge voltage (EV) quantizer with digital-intensive implementation is proposed to detect DC voltage, peak-to-peak magnitude, and frequency of low-frequency simple waveforms (e.g. sinusoidal). The proposed EV quantizer does not need the area-consuming low pass filter. It can be implemented using digital-intensive circuits with little computing complexity, thanks to the simple detection algorithm. A successive approximation register (SAR) version of the EV quantizer was integrated in a monolithic satellite low noise block (LNB) IC in a 65 nm CMOS process to detect low-frequency control signals. And the measurement results validate that the EV quantizer enables low-cost operation for detection of low-frequency simple waveforms.


Introduction
Television broadcast under DVB-S regulations has been in use for many years. The block diagram of a satellite system for DVB-S is shown in Fig. 1. Satellites transmit both horizontal (H) and vertical (V) polarized RF signals in the Ku-band, which is divided into two part, low band (LB: 10.7-11.7 GHz) and high band (HB: 11.7-12.75 GHz). The parabolic dish on roofs or outside windows is used to concentrate the weak satellite signals. And low noise block (LNB), which is set up at the focus of the dish, picks up and translates the signals to IF, ranging within the L-band (0.95-2.15 GHz). Then the L-band signals are transmitted through a coaxial cable to the integrated receiver decoder (IRD), which is more familiarly known as set-top box inside the room. IRD is in charge of the final signal processing before we can watch the TV programs on the TV set.
Actually, the coaxial cable is also used for transmission of power supply and low-frequency control signals from IRD to LNB. Fig. 2  The detected DVoltage and DTone are respectively used to control the bias of off-chip amplifiers and division ratio in PLL. Therefore, the signal of the wanted polarization (H/V) in the wanted band (LB/HB) is picked up and translated to L-band.
The nominal DC voltage of the power supply VDC is 13/18 V. And the nominal peak-to-peak magnitude VPP and frequency fIN of the tone is 0/650 mV and 22 KHz respectively. Due to the unavoidable variances of the circuit devices, the current driven from the supply from LNB and the leakage of the tone, the actual VDC is 13±2/18±2 V. And the actual VPP is 0~0.1/0.22~1 V. Even the frequency fIN is 22±2 KHz. The detector in LNB has to be able to tolerate these signal variances to detect the correct DVoltage and DTone.
References [2,3,4,5] list several products dedicated to the voltage/tone detection. Fig. 3   through a simple one-order RC high-pass filter and a peak detector. DTone can be detected by comparing the extracted VPP with another reference voltage. For low-frequency applications, an obvious shortcoming of the analog detection scheme is the large silicon area occupied by low-pass filters and/or AC coupling capacitors. Moreover, analog circuitry usually suffers from low supply voltages in more advanced CMOS technologies and is not as power-efficient as digital circuits and comparators (CMP) in low-frequency applications due to the huge difference in static power consumption. Traditional electronics has to develop and update using new technology such as integrated circuits on silicon. In early years, LNB is constructed almost all by discrete components [6,7]. With the rapid development of semiconductor, more and more parts can be integrated in the same die [8,9,10]. In recent years the circuits for voltage/tone detection have also been integrated in a monolithic LNB IC [11,12] further cutting the cost. Moreover, only one pin is allocated to input the combined control signal for low package cost.
This paper presents an area/power-efficient digital-intensive detection scheme for low-frequency simple waveforms based on a novel edge voltage (EV) quantizer, which greatly reduces the circuit design complexity compared to the analog scheme. The rest of this paper is organized as follows. Section 2 discusses the idea of digital-intensive detector, including the proposed novel EV quantizer. Circuit implementation of the proposed EV quantizer based on successive approximation register (SAR) architecture is presented in Section 3. Section 4 summarizes the measurement results of the proposed digital-intensive detector using EV quantizer. Finally a brief conclusion is drawn in Section 5.

Digital-intensive detection scheme
As is shown in Fig. 4, a simple waveform SIN can be parted into three regions, i.e., high region (H), middle region (M), and low region (L). Two voltage levels, VHE and VLE, separate these three regions, where VHE is the high side edge voltage and VLE is the low side edge voltage of the input waveform SIN. In observing this, a novel edge voltage (EV) quantizer using "analog" comparators, along with simple digital signal processing, is proposed to extract VDC, fIN and VPP from simple waveforms, completely avoiding traditional sampling and also reducing digital computing complexity without the need for FFT computing. Without loss of generality, we elaborate on EV quantizer by means of a flash version. Fig. 5 shows the block diagram of an N-bit flash EV quantizer and its corresponding coding table. As is expected in a typical flash quantizer, the flash EV quantizer also compares the input with a set of reference voltages simultaneously, indicated by a joint name VDAC in Fig. 5. The comparison output VCMP is fed to a digital square waveform indicator (DSWI), which output VDSWI indicates whether VCMP is a square waveform with a certain frequency.
In a traditional quantizer, a discrete or sampled voltage value from input SIN is used for comparison with a digitized output (either "1" or "0") during one conversion period. In contrast, the proposed EV quantizer compares input SIN continuously with reference voltages using "analog" comparators, i.e., all signals (input, output, and reference) can be treated as continuous analog signals and the comparator behaves more like a limiting amplifier. No sampling is required in the EV quantizer. The comparison result is either continuous DC voltages or a continuous square waveform, which is digitized in the digital square waveform indicator (DSWI).
As can be seen from the coding table in Fig. 5, the quantization codes can be easily obtained by combining the comparator output VCMP and DSWI output VDSWI with simple coding logic. The resulting quantization codes can be further divided into three sections, depending on the values of VCMP and VDSWI. Codes DHE and DLE, separating these three sections, correspond to the quantized results of those two edge voltages VHE and VLE and the quantized code of VPP is obtained by: where Q( ) stands for the operation of quantization. For an input waveform with a VPP less than a quantization step, DHE and DLE, or VHE and VLE, are identical and the input waveform would be detected as a DC signal with a voltage equal to VHE or VLE.

Digital square waveform indicator (DSWI)
The digital square waveform indicator DSWI is actually a digital synchronous sequential counter driven by a clock (CLKF), whose frequency fCLK_F is much higher than fIN. Assume that VPP is larger than a quantization step, which is required for EV quantizer to detect any non-DC signal. When the reference voltage lies between two edge voltages VHE and VLE, "analog" comparator output VCMP becomes a continuous square waveform with the same frequency as fIN. Fig. 6 shows the timing diagram of DSWI. Two counters CNT1 and CNT2 begin to count from 0 when a rising edge of VCMP arrives. When a falling edge of VCMP arrives, CNT1 stops counting with the equivalent counted duration being τ (τHE for DHE and τLE for DLE). When another rising edge of VCMP arrives, CNT2 restarts to count from 0 with the equivalent counted duration being T (same for DHE and DLE). fIN is estimated as: Fig. 7 shows how to detect the rising and falling edges in the comparator's output VCMP using digital synchronous sequential circuits. At every rising edge of CLKF, the real-time value of VCMP is registered by register REG1 and the old value in REG1 is used to update another register REG2. In other words, REG1 and REG2 are detecting two closely-spaced values of VCMP in time domain. As a consequence, the event of "REG1 = 1 & REG2 = 0" represents that a rising edge of VCMP is detected. In a similar way, the arrival moment of the falling edge of VCMP can be CLK F always @(posedge CLK F ){ REG 1 <= V CMP ; REG 2 <= REG 1 ; } detected and represented by the event of "REG1 = 0 & REG2 = 1". The latency of this edge detection scheme is about 1−2 periods of CLKF, which is the exact reason why the counters do not start/stop counting immediately upon the arrival of rising/falling edges, as shown in Fig. 6. After confirming a continuous square waveforms at the comparator output VCMP by counting one or more periods defined by the rising and falling edges, DSWI updates VDSWI to "1", otherwise VDSWI remains to be "0". Value change from "1" to "0" in VDSWI, along with VCMP can be used to determine codes DHE and DLE, and thus the peak-to-peak magnitude VPP. Fig. 8 shows the comparator's input and output waveforms corresponding to codes DHE and DLE. It is obvious that DC voltage VDC of the input waveform SIN can be approximated by averaging the area of the shown trapezoid Atrapezoid over the period T: For sinusoidal or square waveforms with a 50% duty cycle, equation (4) can be further simplified to:

Circuit implementation of SAR EV quantizer
This section describes the circuit implementation of a SAR version of the proposed EV quantizer, employed in a DVB-S television system to detect the control signals from IRD to LNB. The control signals are encoded in a sinusoidal waveform SIN. The expected properties of SIN, which are shown in Fig. 3, are re-summarized as the following: frequency fIN is 22±2 KHz, DC voltage VDC switches between two ranges of 11~15 V and 16~20 V, while peak-to-peak magnitude VPP switches between two ranges of 0~0.1 V and 0.22~1 V. Fig. 9 shows the block diagram of the SAR EV quantizer inside LNB. An off-chip resistive voltage divider is used to shrink the original input voltage to accommodate the operations in a submicron CMOS process. The original VDC is divided by a factor of 9.2. So the new input DC voltage for LNB IC switches between two ranges of 1.2~1.63 V and 1.74~2.17 V. However, the input VPP is unchanged due to the 100-nF bypass capacitor.
The SAR EV quantizer consists of a comparator CMP, a resistor array RX, and digital circuits including a digital square waveform indicator DSWI, a SAR Logic, a DSP block, and a clock divider. A reference current IDAC flowing through RX generates the VDAC. The clock divider divides the on-chip available 25-MHz reference clock signal to generate another two clock signals CLKF and CLKS for the DSWI and the SAR logic respectively. The SAR logic with binary search algorithm adjusts DSAR according to the 2-bit signals-VCMP and VDSWI. Within several binary searching iterations, code DHE or DLE, along with their corresponding high side edge voltage VHE or low side edge voltage VLE, can usually be obtained. Equations (1)-(5), which are implemented in the DSP block, can then be used to obtain the input waveform's DC voltage (VDC), peak-to-peak magnitude (VPP), and frequency (fIN). One can get the detected DVoltage and DTone by comparing the digital VDC and VPP with preset threshold values in digital domain.

Circuits design
The proposed SAR EV quantizer was implemented in a 65nm CMOS technology. The VDAC generation circuit shown in Fig. 9 is developed based on a bandgap reference circuit (BGR) [13]. The bandgap current source IDAC coming from bandgap core circuit is used to set the values of reference voltages for the comparator. A 6-bit setting is realized with reference voltages ranging from 1.05 V to 2.35 V with 1 LSB of roughly 20 mV. With a typical IDAC ≈ 30 μA, RX is chosen to be linearly programmable from 35 to 77.5 KΩ. The equivalent internal preset threshold values for VDC and VPP are designed as VDC_TH = 15.5 V and VPP_TH = 150 mV, respectively. The comparator CMP is a static comparator to simplify the design as much as possible. Fig. 10  A 3.3 V supply voltage is used to accommodate the input DC voltage range and thus thick-oxide transistors in 65nm CMOS are adopted to operate under high supply voltage. The input offset of the comparator is estimated below 10 mV by simulations.
The detection accuracy is also affected by the frequency of CLKF. To avoid detection errors caused by CLKF, its frequency fCLK_F is set high enough, about 780 KHz. And the DSWI is designed to recognize the frequency range of about 22±10 KHz. The SAR logic clock (CLKS) should have a frequency fCLK_S lower than fIN in order to give more time to DSWI for stable VDSWI, which might need more than one-period counting. In this design, fCLK_S is set to about 6 KHz. Based on 6-KHz fCLK_S and 6-bit DAC setting, it takes about 2.4 ms (1÷6000×2×(6+1)) to obtain the final detection results or track any changes of the control signals. This is fast enough for the detection in LNB. As to the specifications in Digital Satellite Equipment Control (DiSEqC) [14], a design with a flash version EV quantizer and a faster CLKS could achieve a detection time of shorter than 100 μs. Fig. 11 shows the die photo of the SAR EV quantizer based low-frequency simple waveform detector, which was integrated in a low-cost LNB IC. It was fabricated in a 65nm CMOS process with a total active area of only 0.0084 mm 2 . The total current consumption is from 120 to 250 μA, depending on the input signal DC voltage and VPP magnitude. To demonstrate the detection of VDC and VPP in the situation that no extra pins are allocated for testing, the input sinusoidal waveform was adjusted continuously until the biasing state or the LO frequency in LNB changes. Statistical measurement results of 8 samples of the proposed EV quantizer are plotted in Fig.  12. The results prove that the proposed detector is able to distinguish whether the input VDC < 15 V or > 16 V, and whether the VPP < 0.1 V or > 0.22 V with a better-than-enough accuracy for satellite television applications. If needed, the accuracy could be improved using a bandgap reference with less variations since reference voltages are the main source of the detection errors. Performance from previous work [2,3,11,12] is summarized and compared with that of our work in Table I. No details about integrated voltage/tone detector are presented in [6,7,8,9,10] and the reason could be that the discrete voltage/tone detector is utilized as in many cases. To the best of the authors' knowledge, this work presents the first low-cost integrated voltage/tone detector for LNB IC, with smallest silicon area, lowest current consumption, and best detection resolution.

Conclusions
This paper presents a novel digital-intensive edge voltage (EV) quantizer, which can be utilized to detect the DC voltage, peak-to-peak magnitude, and frequency of low-frequency simple waveforms (e.g., sinusoidal). Quantizer based detection scheme avoids using low pass filtering and thus saves silicon area. Moreover, the proposed EV quantizer can be implemented using almost all-digital circuits with   little computing complexity, thanks to its simple algorithm for detection results. As a result, the proposed EV quantizer enables low-cost operation for detection of low-frequency simple waveforms.