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An extensive IP reliability evaluation platform

The reliability and robustness of Intellectual Properties (IPs) are the keys to the success of the modern System on Chip (SoC) designs. Therefore, it is very important to implement a rigid IP evaluation platform to ensure the reliability of IPs in the SoC design flow. In this paper, we introduce major aspects of IP reliability and present a XML schema based metric model which is able to describe reliability characteristics of IP cores. An evaluation platform is implemented based on the metric model. The experimental results on three open source IPs demonstrate that the evaluation platform can assess IP reliability quantitatively and locate its bottleneck.