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High-Performance Low-Power Cache Memory Architectures

Recent remarkable advances of VLSI technology have been increasing processor speed and DRAM capacity. However, the advances also have introduced a large, growing performance gap between processor and main memory. Cache memories have long been employed on processor chips in order to bridge the processor-memory performance gap. Therefore, researchers have made great efforts to improve the cache performance. However, the surroundings of processor-chip design have been changing. 1) Recent growing mobile-market strongly requires not only high performance but also low-energy dissipation for expanding the battery life. 2) Recent VLSI technology have made it possible to integrate processor and main memory into the same chip, so that the chip boundary between cache and main memory can be eliminated. The changes suggest that we need to keep considering cache architectures for high-performance, low-energy computer systems. Reducing the frequency of off-chip accesses has mainly two advantages: reducing memoryaccess latency and reducing energy dissipation for driving external I/O pins. The most straightforward way to improve the performance/energy efficiency of memory systems is to invest the increasing transistor budget in the cache memories (increasing cache capacity). Increasing cache capacity improves cache-hit rates, so that more memory accesses can be confined in on-chip. However, it also leads to increase in cache-access latency, which is the time wasted to access the cache, and cache-access energy, which is the energy dissipated for a cache access. Since almost all memory accesses concentrate in cache memories, improving performance/energy efficiency of cache memories is one of the most important challenges. This thesis introduces adaptive cache management techniques for high performance, lowenergy processor chips. The caches proposed in this thesis attempt to eliminate unnecessary operations for reducing energy dissipation and improving performance. In the first part of this thesis, we introduce a cache architecture for reducing cache-access