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Analysis of the effectiveness of multithreading for interrupts on communication processors

High bandwidth of networks demands high performance communication processors that integrate application processing, network processing, and system support functions into a single, low cost System-On-Chip solution. However, conventional processors, when used in network related applications, are beset by the overhead of save/restore of register context, cache misses due to fetching interrupt handler from memory, and the possibility of NIC buffer overflow. Therefore, this paper analyzes the effectiveness of multithreading to service interrupts on an embedded processor simulator enhanced with a multithreaded hardware execution model. Our simulation results reveal that multithreading for interrupts from a single NIC brings only a modest improvement to processing performance. However, our analysis also shows that multithreading for interrupts has a lot of potential when applied to communication processors with multiple interrupt sources, such as Ethernet, ATM, USB, and HDLC.