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Effect of spacer dielectric of asymmetric underlap double gate MOSFET on SRAM performance

Role of high-κ spacer of Asymmetric underlap double gate MOS transistor on SRAM performance is systematically investigated with the help of two-dimensional device simulator. SRAM cell designed using high-κ spacer MOS device shows significant improvement in hold, read and write noise margin. However, due to increase in parasitic capacitance, delay performance of SRAM cell is slightly degraded. Leakage power dissipation of SRAM cell designed using high-κ spacer device is slightly higher than low-κ spacer device because of enhanced subthreshold leakage current.