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An IC design for real-time motion estimation for H.264 digital video

An IC design to achieve real-time motion estimation compensation encoding for H.264 ITU video compression standard is presented. A full-search block matching algorithm has been adapted to a pipelined data flow to enable parallel processing of variable block sized block matching and fractional pixel motion vector generation. High definition TV (HDTV) requires wide bandwidth and a large amount of memory for digital video processing. The SOC is designed with TSMC 0.18mum technology using VHDL and optimized to achieve a 125 MHz clock speed to make real-time processing possible