{'fraction_non_alphanumeric': 0.0324254215304799, 'fraction_numerical': 0.03761348897535668, 'mean_word_length': 4.553956834532374, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design of 100nm Single-Electron Transistor (SET) by 2D TCAD Simulation

One of the great problems in current large-scale integrated circuits (LSIs) is increasing power dissipation in a small silicon chip. Single-electron transistor (SET) which operate by means of one-by-one electron transfer, small size and consume very low power are suitable for achieving higher levels of integration. In this paper, SET is designed with 100 nm gate length and 10 nm gate width is successfully simulated by Synopsys TCAD. The power of SET device that obtained from simulation is 3.771 times 10-9 Watt for fixed current and 3.3565 times 10-9 Watt if fixed the gate voltage, VG, and the capacitance of this device is 0.4297 aF. These results were achieved at room temperature operation.