{'fraction_non_alphanumeric': 0.03, 'fraction_numerical': 0.023333333333333334, 'mean_word_length': 4.61214953271028, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Series-biased CMOS power amplifiers operating at high voltage for 24 GHz radar applications

This paper presents two high power K-band CMOS amplifiers operating at high voltages. The amplifiers employed series-bias technique to increase the operating voltage and achieved a high output power level. The technique also allowed the power amplifiers to operate at a low DC current and thus high efficiency was obtained. The series-bias technique allowed overcoming the low voltage constraint of scaled-down CMOS technology, providing practical solution for realizing high power CMOS amplifier. A two-stage amplifier employing the series-bias technique of four cascode power cells showed a maximum small-signal gain of 25.6 dB, an output power of 20 dBm, and a PAE of 12.5 % at 21 GHz. This is the first CMOS power amplifier delivering 100mW output power above 20 GHz. A three-stage series-bias amplifier having common-source transistor showed a small-signal gain of 17.3 dB, an output power of 17.5 dBm, and a PAE of 8.8% at 23.5 GHz. These amplifiers employing the series-bias technique are shown to have a highly favorable figure-of-merit compared to the results obtained from conventional amplifiers.