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Reliability-aware delay faults evaluation of CMOS flip-flops

Continuously scaling down of CMOS technology brings on low power but also reliability problems such as aging effects and process variations. They can influence and degrade the performance of integrated circuits. In recent years, reliability issues of 65 nm CMOS node has been intensively studied. In this work, a reliability assessment approach considering aging/process variation induced delay fault is proposed in design loop. Typical 65 nm flip-flops are evaluated considering process variations and aging effects. An example with simple logic illustrates this approach for fault probability. It is concluded that process variations are more important comparing to aging effects induced degradation when designing low power digital flip-flops.