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Trap-Tolerant Device Geometry for InAs/Si pTFETs

The influence of channel quantization and interface traps on the performance of InAs/Si pTFETs is analyzed, and a device geometry is predicted which is least sensitive to trap-assisted tunneling (TAT). The good agreement between simulated and measured transfer characteristics validates the reliability of the simulation setup. Simulations show that TAT degrades the sub-threshold swing (SS) of the tunnel field effect transistor (TFET) and that channel quantization reduces its ON-current. The same simulation setup is used to find the device geometry which is least susceptible to interface traps. Scaling down the nanowire diameter below 20 nm inhibits TAT at the oxide/InAs interface. Furthermore, aligning the gate edge with the InAs/Si hetero-junction reduces the degradation of the SS caused by TAT at the hetero-interface. In this way, a gate-aligned InAs/Si nanowire TFET with diameter ~20 nm can deliver sub-thermal sub-threshold swing even in the unavoidable presence of oxide- and hetero-interface traps.