{'fraction_non_alphanumeric': 0.015355086372360844, 'fraction_numerical': 0.003838771593090211, 'mean_word_length': 5.478260869565218, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Layout-Aware Delay Variation Optimization for CNTFET-Based Circuits

Carbon Nanotube Field Effect Transistors (CNTFETs) are attractive alternatives to MOSFET devices as CNTFETs benefit from higher on-current, better gate control and faster switching response. However CNTFET-based technologies suffer from higher process variations compared to MOSFET devices. The CNT density variation is one of the most important sources of variation and directly impacts gate delay variation. The density variations of different gates in the layout are asymmetrically correlated according to their positions with respect to CNT growth direction. In this paper, we take advantage of this asymmetric correlation of CNT density to optimize the circuit layout to reduce the total variation of circuit delay using two heuristic placement methods. Simulation results on ISCAS85 Benchmark circuits show a reduction in total delay variation up to 30%. Our proposed Path Healing technique is up to five orders of magnitude faster than Simulated Annealing placement.