{'fraction_non_alphanumeric': 0.0171473109898675, 'fraction_numerical': 0.001558846453624318, 'mean_word_length': 5.294117647058823, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Reconfigurable Processor PARS and its Compiler

The topics of this paper are the following: (1) to introduce a reconfigurable architecture for general purpose, called as PARS, and (2) its compiler to generate high quality code in a reasonable compile time. PARS architecture can execute various application programs by avoiding the program size problem with the fold-down mechanism and reconfiguration. The mechanism is to fold down the program into fixed size partitions which are partitioned by a compiler. PARS architecture executes these folded partitions one by one. The execution was performed by dynamic reconfiguration. To support such dynamic reconfiguration efficiently, we introduce conditional branch in PARS architecture. To utilize the dynamic reconfiguration ability, PARS architecture requires a good compiler which realize a effective execution flow and achieve high quality on routing and placement. The compiler is required to consider a trade off between compile time and quality of generated code, for avoiding explosion of the compile time, when algorithms used in VLSI CAD are simply applied. In this paper, we show how PARS architecture executes a program effectively and the method how the compiler generates high quality code in a reasonable compile time.