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Virtual register renaming: energy efficient substrate for continual flow pipelines

Continual Flow Pipelines (CFP) allow a processor core to process instruction windows of hundreds of in-flight instructions while keeping its cycle critical scheduler and register file small. CFP defers the execution of instructions that depend on cache misses, moving these instructions to a single ported SRAM buffer outside the pipeline, and continues execution of instructions independent of the cache miss until the miss data is fetched into the cache. This way, the CFP processor core avoids pipeline execution stalls due to cache misses while keeping multi-ported power hungry structures in the pipeline small. However, CFP cores have to wake up and replay the deferred miss dependent instructions through the execution pipeline, again, when the miss data arrives, causing these instructions to increase the circuit activity of the execution pipeline and consequently core energy consumption. In this paper, we present and evaluate virtual register renaming as a substrate for CFP cores that significantly shortens the replay loop and reduces the circuit activity of deferred miss dependent instructions, thus increasing the energy efficiency of Continual Flow Pipelines architectures.