{'fraction_non_alphanumeric': 0.022606382978723406, 'fraction_numerical': 0.0013297872340425532, 'mean_word_length': 5.121951219512195, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Incorporating self-testing capabilities into a systolic array cell for digital signal processing

Techniques for built-in self-test (BIST) are examined. They can be used to modify an existing systolic array controller chip and a multiplier/accumulator chip, called a systolic array cell, so that self-testing can be performed. The goal is to implement a systolic array cell which has self-test capabilities and can efficiently perform various signal processing algorithms such as multiplication, the fast Fourier transform, and convolution. BIST and how BIST can be used in a systolic array are examined. A 2D matrix multiplication algorithm is described. The effects on performance and hardware overhead of incorporating BIST in an array are described