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Design of a 10-bit SAR ADC with enhancement of matching property on C-DAC array

This paper proposes design of a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) reducing device mismatching property driven by MSB node of C-DAC array divided into 4 equal parts. It improves linearity by adding switch for reducing mismatch of MSB node which is the highest portion of mismatch in C-DAC array. The proposed SAR ADC is fabricated in 180nm CMOS and occupies a core area of 850um × 650um. It consumes 66.4uW and achieves an ENOB of 9.3 bits at sampling frequency 800kS/s and power supply of 1.8V. The Figure of Merit (FoM) is simulated to be 134.31fJ/step.