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An Efficient FPGA Implementation of DWT Based Image Data Compression System for Microsatellites

There has been a substantial increase in demand for small satellites. Modern developments in space technology have enabled higher resolution remote sensing sensors in smaller and lighter space crafts. It has led to an increase in the amount of data being generated while putting further constraints on mass, volume and power consumption. This paper presents an efficient FPGA based image compression system suitable for microsatellites, incorporating CCSDS 122.0-B-1 standard. RTAX2000 FPGAs from Microchip have been selected for this implementation. External memory modules are also used as additional storage due to limited internal memory resources of the FPGA. This paper presents brief details of the compression algorithm and the hardware implementation details of the selected compression scheme suitable for micro satellite data rates. The hardware is realized using three levels of two dimensional pipelined DWT, followed by Bit plane encoding using Bit plane parallel architecture. A test setup is made and the functional correctness of the implementation is verified.