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A New Breed of Power-Aware Hybrid Shifters

The paper proposes a smart hybrid of the barrel and logarithmic shifter, to address the hardware complexity issue of the former, and the speed issue of the latter. Transistor level layout of the 16, 32 & 64-bit versions of each shifter was laid out using the state-of-art 70nm processing technology. Simulation results indicate that the proposed shifter easily outsmarts its counterparts in terms of power, delay and area complexities