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A CMOS frequency synthesizer with selfbiasing current source for a 5-GHz wireless LAN receiver

In this work, an integrated 3.2 GHz phase locked loop (PLL) with a selfbiasing current source is presented. The circuit has been designed using a 3.3 V 0.18/spl mu/m CMOS technology. The synthesizer consumes 55 mW of which 20 mW is consumed by the VCO. The PLL has a bandwidth of 100 KHz and a phase noise of -111 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than -70 dBc. These results made the circuit suitable inside a 5 GHz wireless LAN receiver.