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Design and analysis of heterogeneous networks for chip-multiprocessors

Rarely has there been as challenging and exciting a time for research in computer architecture as now. While, the proverbial Moore’s law has consistently helped architects integrate more and more silicon transistors in a single die, device constraints of power, heat, and reliability has forced the computer industry to shift focus from single processor core performance to instantiating multiple processor cores on a chip. In this quest for integrating a large number of cores on a single chip, one particular area of computer architecture that has come into prominence is the interconnection network on a chip (also called network-on-chip or NoC). NoCs seek to provide a scalable, energy-efficient and high-bandwidth communication substrate for future multi-core and many-core architectures—an aspect that critically dictates future chip designs. 
Most of the prior research in NoC has focussed on optimizing the NoC considering it as a homogeneous system i.e. all optimizations proposed, equally affect all the components in the NoC substrate. However, this dissertation demonstrates that the resources in the NoC (precisely, buffers and links) are not always equally utilized, and that not all applications demand similar resources from the underlying interconnection substrate. Hence, this dissertation argues that better and smarter NoCs can be architected by considering the inherent heterogeneity in NoCs from both the network architecture perspective and from the applications’ perspective. Further, considering the fact that future multicores and systems-on-chip architectures will have heterogeneous cores and compute engines, and host diverse applications, it is also inevitable that not all components will demand similar responses from the NoC and neither will these compute engines stress the NoC uniformly. Thus, it is compelling to think of heterogeneous NoCs for such heterogeneous systems. To this end, this dissertation argues in favor of NoCs that factor heterogeneity as a first-order design objective while architecting them for future multi-core systems. 
In this pursuit, this dissertation investigates micro-architectural techniques that exploit heterogeneity at the network resource consumption level (following a bottom-up approach) and from applications’ demand/requirement perspective (following a top-down approach). With the bottom-up approach, heterogeneity is exploited with the key observation that not all resources in an NoC are equally utilized when employing a typical network topology and a network routing protocol. With the top-down approach, heterogeneity is exploited starting from the applications’ demand perspective with the key observation that not all applications require similar resources from the underlying network substrate. Based on these two approaches, this dissertation proposes four techniques with the overall goal of designing high-performance and energy-efficient NoCs. 
The first scheme, called Router Architecture with Frequency Tuning (RAFT), exploits heterogeneity in the buffers of the on-chip routers and proposes a variable- frequency scheme to operate them. This design is the first of its kind to propose a distributed congestion management scheme that is based on operating individual routers at different frequency levels. The second scheme, called HeteroNoC, targets non-uniformity in both buffers and links in the on-chip networks. Using the same amount of link resources and fewer buffer resources compared to a homogeneous network, this proposal demonstrates that a carefully designed heterogeneous network can reduce average latency, improve network throughput and reduce power. The third scheme, argues in favor of designing on-chip networks by taking into account the intrinsic communication requirements of applications. This proposal is based on the observation that, in general, applications can be classified as either network bandwidth sensitive or latency sensitive. Based on this, the proposal consists of two separate heterogeneous networks in the on-chip interconnection substrate, where one network is tailored to optimize for bandwidth sensitive applications and the second network for latency sensitive applications. The fourth scheme presented in this dissertation targets heterogeneity in device technology for improving the memory subsystem performance of multi-cores. This scheme leverages the advantages of an emerging memory technology that is based on spintronics, called spin torque transfer RAM (STT-RAM), for memory subsystem design. STT-RAM can be heterogeneously integrated onto silicon and this proposal argues in favor of designing the NoC in a way that is cognizant of the presence of STT-RAM cache banks. 
This dissertation investigates each of the above proposals at depth and shows that the proposed schemes have minimal overheads in terms of area and power, are simple to implement, and show significant benefits with real applications. Overall, this dissertation makes a strong case for designing heterogeneous networks for improving the performance-power envelope of future multicore processors.