{'fraction_non_alphanumeric': 0.008215085884988798, 'fraction_numerical': 0.0268857356235997, 'mean_word_length': 4.4471544715447155, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
An insulated gate semiconductor device

PURPOSE:To provide an insulating gate semiconductor device in which electric field concentration at a trench bottom is eliminated and withstand voltage between a drain and a source is substantially the same as that of a prior art double diffusion type longitudinal MOS FET, by terminating a trench in which a gate electrode is buried into a base region of substantially the same potential as that of the gate electrode. CONSTITUTION:A silicon substrate 30 comprises an N silicon substrate 30a deposited on the former. There are provided a P base region 31 having a bottom which has a flat junction on a main surface thereof with the N- epitaxial layer 30b and having a top which is exposed to a main surface of the substrate 30, and an N source region 32 which is formed selectively on a surface layer of the P base region 31. There is further provided a trench 40 which is dug from the surface of the N source region 32 in the thickness direction of the substrate 30 and penetrates the N source region 32 and reaches the inside of the P base region 31. There are additionally provided a polysilicon electrode 34 buried in the trench 40 facing the inner surface of the same through a gate oxide film 33, and an N drain region 39 extending from the bottom of the trench 40 to the epitaxial layer 30b.