{'fraction_non_alphanumeric': 0.02363896848137536, 'fraction_numerical': 0.01504297994269341, 'mean_word_length': 4.725409836065574, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design of voltage level shifter for multi-supply voltage design

This paper describes architecture of voltage level shifter used in multi-supply design applications and an application of voltage level shifter. Voltage level shifter is a device which converts one voltage level to another. Voltage level shifters are used to interface various circuit blocks operating at different supply voltages. At the boundaries of different voltage islands on the system-on-chip (SoC) voltage level shifter is used. The proposed voltage level shifter converts low input voltage level into high level voltage output with increased speed and much less power consumption. The architecture is designed with multi-threshold voltage CMOS technique. The multi-threshold voltage CMOS technique is used in the design of voltage level shifter in order to reduce delay and power. Low-threshold voltage devices are used to reduce delay and power dissipation is reduced with the use of high threshold voltage devices. The design has been implemented in a 90-nm BSIM4 level-54 CMOS technology. Simulation is carried in tanner v15.0 software at schematic level. Simulation results show that the design converts minimum of 0.1 V input signal into 1 V output signal. The level shifter has propagation delay of 10.99 ns and power dissipation of 1.52nW. The operating condition for the proposed design: VDDL = 0.2 V, VDDH = 1 V.