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Implementation of a digital ΔΣ modulator and programmable prescaler divider circuit for a fractional-N PLL

This paper presents the design of a HK-MASH 111 digital delta sigma modulator and a programmable prescaler divider circuit for a fractional-N PLL frequency synthesizer. The maximum operating frequency of the divider circuit is 10 GHz and this divider architecture can be used for the noise cancellation in ΔΣ fractional-N PLL frequency synthesizers circuit. Power consumption of the divider block is about 16.5 mW including the high speed synchronization block from a 1.8 V supply. Phase noise floor is -161 dBc/Hz at 1 MHz offset frequency for 5 GHz carrier signal. In addition, proper biasing scheme has been added in the different prescaler divider cell to optimize the power consumption and phase noise. The phase noise analysis has been presented with analytical model and simulation results in 0.18 μm CMOS. The figure of merit (FoM) of the divider is 158.4 dB.