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Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

The design of resistive RAM (ReRAM) faces two major challenges: 1) cell area versus write current requirements and 2) cell read current (ICELL) versus read disturbance. This paper proposes ReRAM macros using logic-process-based vertical parasitic-BJT (VPBJT) switches and a corresponding cell array (VPBJT-CA), resulting in a 4.5× macro density compared to conventional NMOS-switch ReRAM for given write current requirements. To overcome temperature-dependent fluctuations in the base-emitter voltage difference (VBE) of VPBJT, we propose a temperature-aware bitline (BL) voltage bias (VBL-R) (TABB) scheme to provide current-mode sensing with 4.7× larger ICELL and 1.6× faster read speeds. Test results of fabricated 0.18 μm 1 Mb and 65 nm 2 Mb VPBJT ReRAM macros confirm the efficacy of the temperature-aware VBL-R, resulting in sub-5-ns random read access times.