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Stack effect implementation in OPC and mask verification for production environment

With the decrease of the transistors dimensions, process steps usually considered as not critical become challenging. This is the case for implant levels patterning, which can be strongly impacted by reflections from the underlying active and gate patterns, especially when no anti-reflective coating can be used. This stack effect leads to unexpected resist shape on wafer if not taken into account during OPC flow. We propose a solution to integrate stack effect onto existing OPC models by adding fictive layers at mask level in order to allow a stack-aware OPC or mask verification. This method can be implemented in a standard OPC flow offered by EDA OPC software. It provides effective results compatible with production constrains, such as stack-aware full chip simulation and run time efficiency.