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A spread-spectrum clock generator using phase interpolation for EMI reduction

The spurious-free dynamic range of RF DAC’s are limited by the heavy digital domain switching, which interferes with the analog output signal. A design, layout and simulation of a spread-spectrum clock generator (SSCG) is presented. The SSCG modulates the clock frequency used to switch the digital blocks of the DAC in order to reduce electromagnetic interference (EMI) spurs at the analog output signal of the DAC. Leveraging on a phase control architecture rather than a traditional PLL, the SSCG system is shown to reduce the spectral height a divided down clock spur up to 19.6dB. The SSCG is designed in TSMC’s 65nm CMOS process. It takes in quadrature, differential clocks at either 2.5GHz or 5GHz, and provides quadrature output clocks at 625MHz or 1.25GHz. The output spectrum of the clock can be attenuated up to 19.6dB relative to the spectrum of an unspread clock. The core of the SSCG is a phase interpolator, which takes in quadrature input clocks and interpolates between them to move the frequency around. To help process the signals before and after interpolation, the SSCG incorporates input variable gain filters, output restoration buffers and divide by 4 circuits. Extensive transistor and behavioral simulations are used to verify the design. Thesis Supervisor: Prof. Charles G. Sodini Title: LeBel Professor of Electrical Engineering Thesis Supervisor: Matthew L. Courcy Title: Senior Design Engineer, Analog Devices