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Coupling Aware Explicit Delay Metric for On- Chip RLC Interconnect for Ramp input

Recent years have seen significant research in finding closed form expressions for the delay of the RLC interconnect which improves upon the Elmore delay model. However, several of these formulae assume a step excitation. But in practice, the input waveform does have a non zero time of flight. There are few works reported so far which do consider the ramp inputs but lacks in the explicit nature which could work for a wide range of possible input slews. Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However, for typical RLC interconnections with ramp input, Elmore delay can deviate by up to 100% or more than SPICE computed delay since it is independent of rise time of the input ramp signal. We develop a novel analytical delay model based on the first and second moments of the interconnect transfer function when the input is a ramp signal with finite rise/fall time. Delay estimate using our first moment based analytical model is within 4% of SPICE-computed delay, and model based on first two moments is within 2.3% of SPICE, across a wide range of interconnects parameter values. Evaluation of our analytical model is several orders of magnitude faster than simulation using SPICE. We also discuss the possible extensions of our approach for estimation of source-sink delays for an arbitrary interconnects trees.