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V- PMP: A VLIW Packet Manipulator Processor

5G networks are called to efficiently and flexibly support an ever growing variety of heterogeneous middlebox-type functions such as network address translation, tunneling, load balancing, traffic engineering, monitoring, intrusion detection, and so on. This flexibility, together with the increasing demands in terms of packet processing throughput, is extremely difficulty to achieve. One of the best candidates to provide such flexibility is a programmable dataplane based on a pipeline of match/action stages, similar to those proposed for Openflow. Designing an high speed programmable dataplane requires to have both flexible and efficient match tables and high speed programmable blocks for action execution. In particular, the most demanding actions, in terms of processing power, are those related to the manipulation of the data inside the packets, i.e. the set of operations (such as encapsulation or header manipulation) performed on packets after the forwarding decision. These encapsulation and header rewriting actions are key elements to put together heterogeneous networks and to enable flexible slicing, as envisioned by the forthcoming 5G network architecture. In the work presented in this paper we focused on the design of a Very Long Instruction Word (VLIW) processor, based on a custom instruction set, able to perform efficient packet processing operations granting multi-Gbps throughput. In particular, we provide details of the Packet Manipulator Processor (PMP) architecture and its I/O interfaces, which have been designed to accomplish packet manipulation tasks, we discuss the throughput analysis of three use cases (tunneling, NAT, and ARP reply generation) and present FPGA synthesis results.