{'fraction_non_alphanumeric': 0.027662517289073305, 'fraction_numerical': 0.006915629322268326, 'mean_word_length': 5.956730769230769, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Current-Mode Multiple-Resolution Edge-Filtering Complementary Metal Oxide Semiconductor Image Sensor Employing Self-Similitude Processing in Non-Subtraction Configuration

A non-subtraction configuration of the self-similitude image processing architecture has been developed for pixel-parallel multiple-resolution directional edge filtering. In contrast to the subtraction-separated configuration employed in our previous work, the subtraction operation has been entirely eliminated from the computation repertory of processing elements in the present configuration. As a result, the hardware organization of the multiple-resolution edge-filtering complementary metal oxide semiconductor (CMOS) image sensor has been greatly simplified, and a fully pixel-parallel self-similitude processing has been established without any complexity in interconnects. In addition, it has provided an opportunity to further apply the self-similitude architecture to other filtering operation like Gaussian filtering and Laplacian filtering. An analog edge-filtering chip implemented using current-mode computation capable of performing four-directional edge filtering at full, half, and quarter resolutions was designed and fabricated in a 0.18-µm five-metal CMOS technology. The concept has been verified by chip measurements, which show that the four-directional edge filtering at multiple resolutions is accomplished at 910 frames/s for 56×56-input images.