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Fabrication of Graphene p-n Junction Field Effect Transistors on Patterned Self-Assembled Monolayers/Substrate

The field-effect transistors (FETs) with a graphene-based p-n junction channel were fabricated using the patterned self-assembled monolayers (SAMs). The self-assembled 3-aminopropyltriethoxysilane (APTES) monolayer deposited on SiO₂/Si substrate was patterned by hydrogen plasma using selective coating poly-methylmethacrylate (PMMA) as mask. The APTES-SAMS on the SiO₂ surface were patterned using selective coating of PMMA. The APTES-SAMs of the region uncovered with PMMA was removed by hydrogen plasma. The graphene synthesized by thermal chemical vapor deposition was transferred onto the patterned APTES-SAM/SiO₂ substrate. Both p-type and n-type graphene on the patterned SAM/SiO₂ substrate were fabricated. The graphene-based p-n junction was studied using Raman spectroscopy and X-ray photoelectron spectroscopy. To implement low voltage operation device, via ionic liquid (BmimPF 6 ) gate dielectric material, graphene-based p-n junction field effect transistors was fabricated, showing two significant separated Dirac points as a signature for formation of a p-n junction in the graphene channel.