{'fraction_non_alphanumeric': 0.05039193729003359, 'fraction_numerical': 0.03583426651735722, 'mean_word_length': 4.289940828402367, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 2, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A 14-bit 2.5 GS/s digital pre-distorted DAC in 65 nm CMOS with SFDR > 70 dB up to 1.2 GHz

This paper presents a 14-bit 2.5 GS/s current-steering digital-to-analog converter (DAC) in 65 nm CMOS. Small transistors are utilized in this design to reduce the 3rd-order harmonic distortion caused by finite output impedance. However, the adoption of small transistors increases the 2nd-order harmonic distortion and degrades the spurious-free dynamic range (SFDR). Hence a digital pre-distortion (DPD) scheme is proposed for 2nd-order harmonic distortion cancellation. In addition, techniques including dynamic element matching (DEM), double-data-rate (DDR) quad switch and always-on cascode switch are employed in this design to further enhance the SFDR. Simulation results show > 70 dB SFDR for input frequencies from 34 MHz to 1.2 GHz. The DAC consumes 375 mW from a dual 1.2/2.5 V power supply.