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A HW/SW partitioning algorithm for multitask reconfigurable embedded systems

Reconfigurable embedded systems which exploit a processor core in conjunction with a run-time reconfigurable unit (such as FPGA) provide the simultaneous execution of complex applications faster than before. In most of these systems several complex applications run simultaneously and hence we call them multitask reconfigurable system. In this paper we propose a heuristic method for HW/SW partitioning in multitask dynamic reconfigurable systems, with emphasizing multitask feature. In this method, concurrent execution of several task graphs and its effect on overall execution time has been specially considered. We have integrated this algorithm into our HW/SW codesign methodology and carried out a large variety of experiments on it. Obtained results show the benefits of this algorithm.