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Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme

This paper introduces a novel superscalar micro-architecture, called IAS-S, and its related software techniques. We treat two basic problems in superscalar machines. First, we seek a feasible hardware platform which allows the compiler to perform more aggressive instruction scheduling. Second, we develop a good way of communication between the instruction scheduler and register allocator to avoid inadequate register allocation resulting in poor instruction schedules. For the first part, IAS-S employs the Conjugate Register File (CRF) scheme to support multilevel instruction boosting so that a greater amount of instruction-level parallelism in a program can be identified at compile time. For the second part, the instruction scheduling in the IAS-S compiler consists of two passes, prepass and postpass, and a scheduling-conflict graph is built for the register allocator during the prepass scheduling. In this manner, the register allocator can take the potential benefit for later postpass instruction scheduling into account and thus prevents inadequate register allocation.