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A 2-V 40-MS/s 14-bit pipelined ADC for CMOS image sensor

The paper describes the implementation of a 40-MS/s 14-bit pipelined analog-to-digital converter (ADC) for CMOS image sensors in 0.18μm CMOS technology. The pipeline architecture consists of a series of 2.5bit stages, one stage 2-bit flash ADC and time align & digital error correction circuit. The ADC design is provided with a differential input voltage range of ±1V, 3.3 V power supply, and a total power dissipation of 100mW in typical case. The ADC achieves a SNDR of 82.4dB and ENOB of 12.6bits at 40MHz sample rate with a sine wave input of 17 MHz frequency. The entire ADC chip occupies 2.5mm×0.9mm area. The ADC in this design meets the requirement of CMOS image sensors well.