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Equivalent Capacitance and Multilayer Models for Effective Roughness Dielectric in PCBs

Effective Roughness Dielectric (ERD) is used to substitute copper foil roughness in printed circuit board (PCB) interconnects. In this work, the the equivalent capacitance approach is used to get the ERD parameters based on the understanding that there is a gradual variation of concentration of metallic inclusions in the transition layer between the dielectric and foil. The metallic concentration profile can be extracted from scanning electron microscopy (SEM) or high-resolution optical microscopy. The proposed model of equivalent capacitance with gradient dielectric is applied to standard (STD), very-low-profile (VLP), and hyper-very-low profile (HVLP) foils, and the frequency-dependent dielectric parameters of the homogenized ERD are calculated. The analytically calculated ERD parameters are used in 2D-FEM and 3D full-wave numerical models of the stripline structures with various types of foils. There are two types of 3D numerical models: with homogeneous ERD parameters and multilayer “space map” model. All the models show excellent agreement with measurements, and the analysis of the results of different models is provided.