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Area-Time Efficient FAST Corner Detector Using Data-Path Transposition

Corner detection plays an essential role in many computer vision applications, e.g., object recognition, motion analysis, and stereo matching. In this brief, we present a novel data-path transposition strategy for the hardware design of the FAST corner detector. The proposed design transposes the data-path of the conventional architecture to enable partial evaluation of multiple corners in a pipelined manner, which reduces the size of the window buffer. Further area savings were achieved by combining the operations for computing the corner scores and determining the member vectors. We show that the proposed design on 180-nm CMOS technology leads to about 22% reduction in the critical path delay and lesser area compared to the previously reported architecture, without a notable difference in energy consumption.