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Comprehensive evaluation of an instruction reissue mechanism

In this paper, we evaluate a mechanism to reissue instructions on the mispredicted speculation path. An instruction which is once dispatched to a functional unit during mispredicted speculation is issued again inside an instruction window. This scheme is called instruction reissue. We propose to extend register update unit to perform the instruction reissue. The instruction reissue is effective for data dependence speculation, since instructions which are independent of a misspeculated instruction should not be squashed. From an experimental evaluation, we have confirmed that the instruction reissue using the proposed mechanism enhances processor performance without introducing any severe hardware overheads.