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Noise in Al single electron transistors of stacked design

We have fabricated and examined several Al single electron transistors whose small islands were positioned on top of a counter electrode and hence did not come into contact with a dielectric substrate. The equivalent charge noise figure of all transistors turned out to be surprisingly low, (2.5 - 7)*10E-5 e/sqrt(Hz) at f = 10 Hz. Although the lowest detected noise originates mostly from fluctuations of background charge, the noise contribution of the tunnel junction conductances was, on occasion, found to be dominant.

We have fabricated and examined several Al single electron transistors whose small islands were positioned on top of a counter electrode and hence did not come into contact with a dielectric substrate. The equivalent charge noise figure of all transistors turned out to be surprisingly low, (2.5 − 7) × 10 −5 e/ √ Hz at f = 10 Hz. Although the lowest detected noise originates mostly from fluctuations of background charge, the noise contribution of the tunnel junction conductances was, on occasion, found to be dominant.

I. INTRODUCTION
The physics and applications of the small metallic circuits employing the Single Electron Tunneling (SET) have been intensively studied in the past decade. [1,2] During this study, it has become apparent that the fluctuations of the polarization charge offset of small islands of an SET structure present a serious problem.
It is generally agreed that such background charge noise is resulted from stochastic occupation of charge traps in dielectric materials surrounding the island and it is usually characterized by a 1/f power spectrum with a cut-off frequency of f 0 = 100−1000 Hz and a magnitude of (S Q ) Hz at 10 Hz (see, for example, [3][4][5] and references therein). Its lowest value which has been measured by Visscher et al. [6] is accounted for 7 × 10 −5 e/ √ Hz at 10 Hz. At f < f 0 the background charge noise is dominant over the intrinsic SET noise and it dramatically reduces the performance of various devices: electrometers [7], pumps [8], traps [9], etc. For that reason, the better understanding of the nature of this noise and the search for ways of reducing it are very important for the practical realization of reliable SET devices.
Numerous measurements of noise in SET transistors (i.e. the two-junction structures supplied with a gate, capacitively coupled to its island) have revealed a trend towards a noise increase with the size of an island and, hence the contacting area with a "noisy" substrate. [4,10] Recent measurements using two SET transistors (electrometers), closely positioned on the same substrate, showed that their output noise signals were partially correlated. [5] This, as well as other measurements of double [11] and single [12] electrometers, again indicate to a possibly substantial noise contribution of the substrate.
The aim of this work was to eliminate this "substrate" component of the noise by means of sophisticated design, namely by placing a small metallic island of an SET transistor almost entirely on the oxidized base electrode. In this configuration, the base electrode, due to its larger dimensions, efficiently screens the island from polarization caused by the charges both inside and on the surface of substrate. Hence, the noise is mostly setted by processes in the barriers of tunnel junctions. Due to capability of the gate control, we are able to distinguish the charge fluctuations and conductance fluctuations of the barriers in our transistors and we show, in particular, that they can be uncorrelated one with the other. Moreover, this paper reports the data which turned out to be remarkable for the lowest level of the background charge noise measured so far in SET devices. [13]

II. FABRICATION AND CHARACTERIZATION OF THE SAMPLES
The Al structures were fabricated on a Si substrate buffered by a sputtered Al 2 O 3 layer 200 nm thick by the shadow evaporation [14] at three different angles (see Fig. 1). There were three successive deposition cycles in-situ. After the first and second depositions, the Al films were oxidised and the tunnel barriers were thereby formed. Particular attention was given to precise alignment of the edges of a small Al island and a base electrode (shown by the thin line in the mask layout in Fig. 1(a)) with the aim of not allowing straightforward electron tunneling between the outer electrodes. The top electrode, a small finger turned through 90 degrees, did not overlap the island completely, so the area of the upmost junction (about 60 × 40 nm 2 ) was noticably smaller than that of the bottom one (nominally 80 × 100 nm 2 ). By virtue of this arrangement (the top electrode overlaps the island only partially), the electric field induced by the side coplanar gate electrode, penetrated to the island and held the function of electrostatic control.
The characteristics of the sample were measured in a dilution refrigerator at the bath temperature T = 30 mK. The magnetic field B = 1 T was applied to suppress the superconductivity in the Al films. We used the voltage bias configurations in which the current I was measured by op amp functioning as an amperemeter. This setup was characterized by an extended bandwidth (up to 1 kHz) [15] and a low noise floor of the order of 20 fA/ √ Hz at 10 Hz.
We have measured four samples and found their electric parameters (see the equivalent circuit diagram in Fig. 2(a)) to be typical for metallic SET transistors. The total tunnel resistances R Σ = R 1 + R 2 were in the range 200-450 kΩ, the total capacitances of the transistor islands C Σ = C 1 + C 2 + C g ranged from 450 aF down to 350 aF. The gate capacitances C g were found to be rather small and accounted for 0.1-0.2 aF. Due to the design features, the transistor characteristics were asymmetric, Fig. 2(b)). Here index 1 is associated with the bottom, i.e. the larger, junction and index 2 with the top junction. Due to rather small C Σ , the maximum values of the current-to-charge ratio η = max Q0 were sufficiently large, especially for the steeper slopes of the I−V gate curves: η steep ≈ 2−3 nA/e, and this has substantially improved the signal-to-noise ratio of our transistors as electrometers.

III. THE RESULTS OF NOISE MEASUREMENTS
The equivalent charge noise (S Q ) 2 (here S I is the output noise power) measured in all four samples at low currents turned out to be suprisingly low (see Table I). In particular, the best charge sensitivity of the electrometer (sample 1) at 10 Hz was found to be (2.5 ± 0.5) × 10 −5 e/ √ Hz or, in energy units, Note, that this level is still considerably higher than the fundamental noise floor, which we evaluate [7] (assuming the effective electron temperature of the island of 100 mK) as ∼ 3 × 10 −6 e/ √ Hz or ǫ ∼ 4h. However, the obtained noise figure Eq.(1) is substantially better than the best one obtained earlier by Visscher et al. [6]: 7 × 10 −5 e/ √ Hz or 1000h at 10 Hz. Note that desing of their samples with gates positioned beneath the islands, also assisted in partial electric screening of the islands from the substrate charges.
The dependence of noise on the transport current (for the fixed voltage regime) and on the position of the bias point (marked in Fig. 2(b)) is presented in Fig. 3. Panel (a) shows a regular dependence on the bias point by the example of sample 1 (samples 2 and 3 showed a similar behavior). One can see that output noise, measured on the slopes of the modulation curve appreciably exceeds the noise measured in the points of minima and maxima, which are insensitive to the background charge noise, η = 0. The noise power on the slopes first rises with current, although starting from approximately I = 500 pA it reduces. Such behavior at high currents is attributed to the reduction of the current-to-charge ratio η. The equivalent charge noise measured, for example, on the steep slope therewith rises monotonously from 2.5 × 10 −5 e/ √ Hz at 10 pA up to 6 × 10 −4 e/ √ Hz at 2 nA. On the contrary, sample 4 clearly shows an anomalous behavior (see Fig. 3(b)) . Its noise at f = 10 Hz measured in maxima is almost similar to that on the slopes in a wide range of I, except high currents, I ≈ 1 nA. This is in contrast to other our samples and to the observations in conventional SET transistors (see, for instance Refs. [4,15]). The anomalous behavoir of sample 4 is also traced in Fig. 4, which demonstrates the power spectra measured at fixed voltage V = 50 µV, but at different transport currents. As can be seen, the noise on the steep slope at I = 50 pA has approximately a 1/f 2 spectrum for f below several Hz and it dominates over the noise measured in the maximum (I = 100 pA) at f < 1 Hz. At higher frequencies, f > 1 Hz, noise in the maximum is dominant. Its spectrum is almost flat in the frequency range 0.1-100 Hz. (Unfortunately, considerable noise of the setup at higher frequencies did not allow us to investigate its rolloff.) Note, that noise, measured on the gentle slope at the same current I = 50 pA (not shown), slightly exceeds the noise on the steep slope, but is also lower than the noise in the maximum at f < 1 Hz. These observations clearly indicate two different sources of noise. The low-frequency component of noise on the slopes can be unambiguously associated with the background charge fluctuations, whereas noise in maxima, as well as on both slopes at f > 1 Hz, might be attributed to the tunnel conductance fluctuations which resulted in an output noise rising with I (see Fig. 5).

IV. DISCUSSION
Thus, our measurements clearly demonstrate coexistance of two types of noise in the double tunnel junctions: the background charge noise and the conductance noise, and these two noises are characterized by different frequency spectra and, hence seem to be uncorrelated. The former is associated with activity of fluctuators with characteristic switching time of the order of a second or longer. The latter is produced by a faster switching of conductance of the barriers. Earlier, a possible mechanism of the conductance noise observed in single Nb-Nb 2 O 5 -PbBi tunnel junctions of small size was proposed by Rogers and Buhrman. [16] They explained this (usually 1/f ) noise by stochastic charging and discharging of, at least, several natural traps (two-level fluctuators) for single electrons, which are located in the tunnel barriers. According to their picture, if an electron is captured by the trap, it repels other electrons attempting to tunnel nearby. Such trap causes barrier height fluctuations and, hence, it should unavoidably produce a polarization of the electrodes which form this junction. However, their samples (single junctions) were evidently insensitive to this polarization. In our case of a double junction a (noticable) polarization of a small island could then be apparently developed. Our observations, however, do not reveal this effect and hence they cast doubt on the mechanism based on re-charging of traps, located inside the barrier, as the main mechanism responsible for the conductance fluctuations in our Al-Al 2 O 3 -Al junctions. What could be an alternative mechanism of "pure" conductance noise? As a possible mechanism, we suggest that the observed conductance noise originates from fluctuators which are located immediately in the metal-oxide interfaces and influence the local current density but do not polarize the island. In our case of a thin island (d =15 nm) the inner boundaries of the island experience multiple reflections of an electron arrived to the island before its thermalization. (This process is characterized by the inelestic scattering length ∼ µm ≫ d.) In the course of these reflections the confined electron can donate its energy to those ions on the metal-oxide boundary which are not constrained to certain positions in the lattice, causing thereby their slow motion between neighboring minima. This process can possibly cause fluctuations in the effective barrier transparancy and hence in the tunnel current.
However, for the most part of the measured samples the conductance noise did not manifest itself. (This agrees with the fact that for the perfect Al-Al 2 O 3 -Al barriers the measured noise is usually close to shot noise level. [17]) In these cases, we could assume that the observed background charge noise and, possibly, very rare switching of Q 0 originate from re-charging of traps, located inside the barrier. On the other hand, a motion of charges in the natural oxide layer covering the open surface of the island and having more irregular structure can also be a source of background charge noise. These areas do not directly contribute to electron current through the device and hence do not cause conductance fluctuations. Moreover, since the observed perfect Coulomb blockade did not show any sign of a parallel channel for electrons to tunnel between the outer electrodes, we do not rule out the existence of small areas where the edge of an island is in contact with the substrate, that can also contribute to the total noise. This is in confirmity with our observation of substantially larger charge noise in the reference transistors which were fabricated on the same chips such that their islands were partly lying on the substrate. For example, two transistors from the same chip as sample 2 had a contacting area with the substrate of about 20% and 50% of the total island area and they exhibited a noise of 1.2 × 10 −4 e/ √ Hz and 2 × 10 −4 e/ √ Hz at f = 10 Hz respectively [18] (compare with the bare value of 4 × 10 −5 e/ √ Hz presented in Table I). Finally, we have shown that, first, the achieved low level of noise in our transistors is definitely due to their stacked design which eliminates the effect of a substrate. Secondly, the noise of the barrier conductances which was observed in one of such samples, was clearly resolved since it dominated over the background charge noise at f > 1 Hz. Although the mechanism of this conductance noise is not completely understood it might be associated with fluctuations in the metal-oxide interface which almost do not cause polarization of the island. As long as this noise is much lower than the typical background charge noise level, it seems not to be a hindrance for majority of SET devices, operating at low current. Therefore, our experiment encourages us to further study of noise both in devices of traditional design fabricated with new materials for the substrate as well as in devices having an alternative (e.g., stacked) design with a goal to realize the high potentials of metallic SET structures.   FIG. 5. The simulated I − Vgate curves showing the effect of the ±10% variation of the larger resistance R2 (corresponding to the upper junction). Since junction 2 has smaller dimensions, R2 is more subjected to fluctuations due to spatial non-uniformity of the barrier, if all other factors being the same. One can see that fluctuations on the gentle slope are larger than those on the steep slope and they rise with I approaching their maximum near the top of the curve. This agrees qualitatively with the observations of noise in sample 4 at f >1 Hz.