{'fraction_non_alphanumeric': 0.015600624024960999, 'fraction_numerical': 0.0078003120124804995, 'mean_word_length': 4.487179487179487, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A New Full Swing Full Adder Based on New Logic Approach

As full adders are duplicated many times in arithmetic circuits, power consumption of them plays important role in total power consumption of the system. This paper presents a new low power full adder based on a new logic approach. The main aim is implementing full adder with only one XOR module to reduce power consumption. Simulation has been conducted by using HSPICE in 0.18 m bulk technology with 1.8V supply voltage. The results show that the proposed circuit has less power and higher delay than recently proposed full adders in the literature. However, PDP has been improved.