{'fraction_non_alphanumeric': 0.030708661417322834, 'fraction_numerical': 0.0007874015748031496, 'mean_word_length': 5.585492227979275, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Common Recursive Form for Multiple Fundamental Arithmetic Operators and its Automated Synthesis

The common recursive structure of a number of basic arithmetic operators is investigated. Previously, it was shown that fully combinational leading-digit N-bit detector circuits could be generated with a simple dyadic tree recursive structure having minimal complexity, regular and low fan-in and fan-out and log2(N) stages of delay for all outputs. Here, we show that this recursive structure is shared by many common arithmetic functions, including comparison, incrementation, decrementation, and fast parallel-prefix adder. This enables said functions to be described simply and parametrically in VHDL or Verilog using structural recursion. The commonality can also be leveraged to design multi-function circuits which are advantageous compared to separate operators chosen through multiplexers in, e.g., arithmetic-logic units. Preliminary synthesis results for both FPGA and digital CMOS are provided in order to characterize said benefits. This type of multifunction circuit could be employed in the design of fast, low-complexity arithmetic-logic units (ALUs) inside microprocessors, digital signal processors, or application-specific system-on-chip (SoC) designs.