{'fraction_non_alphanumeric': 0.027777777777777776, 'fraction_numerical': 0.015432098765432098, 'mean_word_length': 5.117924528301887, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Pt/BaxSr(1-x)TiO3/Pt Capacitor Technology for 0.15 µm Embedded Dynamic Random Access Memory

A novel capacitor technology has been developed for 0.15 µm embedded dynamic random access memory (DRAM). Platinum as electrodes and barium strontium titanate (BST) as dielectrics are used in the capacitor. The BST dielectrics is a stack of two layers. The nucleating bottom layer is deposited by sputtering and the top bulk layer is deposited by chemical vapor deposition (CVD). The two-step deposition process is established with high reliability without N2 high-temperature annealing. Moreover, both thermal stability and reductive stability of the BST capacitors are improved by introducing modulated oxygen-doping into the Pt top electrodes. The degradation mechanism of the BST capacitors by annealing in the back end process was revealed. Oxygen atoms doped into the top electrode diffuse to the interface between the bottom electrode and the metal nitride barrier layer, and oxidize the metal nitride. The modified BST capacitors maintained low leakage current and sufficient capacitance after 500°C N2 annealing and 400°C H2 annealing. These BST capacitors have been integrated into the 0.15 µm rule-embedded DRAM having a capacitor under bit-line (CUB) structure and four-level metallizations.