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Analysis of reversion losses in charge pumps and its impact on efficiency for low power design

Reversion losses are a major cause in degrading the efficiency of charge pumps (CPs) and a non-overlapping clock scheme is crucial to eliminate these losses and improve the CP's efficiency. However, employing a non-overlapping clock scheme will increase the total Silicon area and can increase the total current consumption of the CP. The increase in CP's current consumption, due to a non-overlap clock scheme, is dependent on the scheme's current consumption and on the improvement in efficiency it provides. The latter depends on the severity of reversion losses' impact on the CP's efficiency and output voltage for a set of design parameters. This paper analyzes reversion losses in cross-coupled CPs and characterizes them with a mathematical model. The model can be used by designers to evaluate the impact of reversion losses on the CP's efficiency and accordingly assess the merit of using a non-overlapping clock scheme for different design parameters. The model is verified through circuit simulations in Cadence environment using a CMOS 0.18µm 6-metal layers technology.