{'fraction_non_alphanumeric': 0.0327683615819209, 'fraction_numerical': 0.005649717514124294, 'mean_word_length': 5.195804195804196, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Non-Uniform Cache Architecture on Networks-on-Chip: A Fully Associative Approach with Pre-Promotion

Global interconnect becomes the delay bottleneck in microprocessor designs, and latency for large on-chip caches will be intolerable in deep submicron technologies. The recently-proposed Non-Uniform Cache Architectures (NUCAs) exploit the variation in access time across subarrays to reduce typical latency. In the dynamic NUCA (D-NUCA) design, a set-associative structure is selected and thus the flexibility of data placement and replacement is limited. This paper investigates one of the unexplored design space; a fully associative approach. In addition, we propose a pre-promotion technique to reduce the number of incremental search in the distributed cache banks. We show that, compared with a traditional multi-level cache, up to 110% improvement in IPC is achieved at 30nm.