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Simulation 3D TSV for stress-strain characteristics under mechanical and thermo-mechanical loading

This paper addresses the key stress and strain characteristics issues in three-dimensional integrated circuit (3D IC) packaging, which arise due to mechanical and thermo-mechanical loading. Although 3D IC packaging is known to suffer critical issues due to the reliance on non-mature technologies, it is valued for its high performance and miniaturization, achieved through the short vertical interconnections between individual chips and multi-chips that are stacked together. However, the reliability of through silicon via (TSV) and micro-bumps is still a significant concern and should thus be investigated further, due to the complexity of the architecture and microstructure. In this work, the 3D IC package used in the simulation model is built, after which the model is investigated under thermal cycle loading and mechanical bending cycle loading. In the analyses, both micro-bump and TSV are considered to exhibit bilinear isotropie hardening behaviors. The simulation results indicate that, under mechanical loading, the critical failure occurs on the outer micro-bump, while it is located on the outer TSV under thermo-mechanical loading. We thus posit that these fatigue failure sites could arise from the coefficient of thermal expansion (CTE) mismatch between the silicon chip and the TSV. Based on these findings, a simulation-based optimization methodology is developed with the aim of improving the overall 3D IC reliability. The main objective is to improve the TSV and micro-bump fatigue life when subjected to mechanical and thermo-mechanical loading by optimizing the design factors.