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Theoretical design and circuit implementation of integer domain chaotic systems

In this paper, a new approach for constructing integer domain chaotic systems (IDCS) is proposed, and its chaotic behavior is mathematically proven according to the Devaney's definition of chaos. Furthermore, an analog-digital hybrid circuit is also developed for realizing the designed basic IDCS. In the IDCS circuit design, chaos generation strategy is realized through a sample-hold circuit and a decoder circuit so as to convert the uniform noise signal into a random sequence, which plays a key role in circuit implementation. The experimental observations further validate the proposed systematic methodology for the first time.


Introduction
Currently, international research works on chaotic systems and their applications are mainly concentrated on real domain, leading to the study and development of the so called Real Domain Chaotic Systems (RDCSs). RDCSs are divided in two categories: continuous-time and discrete-time chaotic systems. Continuous-time systems, including the Lorenz, Chen and Chua systems [14,8,7] are defined by state (differential) equations, while discrete time chaotic systems are given by iterative equations, such as Logistic or Henon map, Chen-Lai algorithm [15,17,6], and so on.
When a chaotic phenomenon is implemented either in digital computers or in some other digital devices, its associated chaotic system is discretized both spatially and temporally. That is, the system becomes both a discrete-time and discrete-valued pseudo chaotic system, defined in discrete time and on finite spatial lattice [9]. Finite words lengths in the digital machines lead to finite precision effects, and may result in consequent dynamic degradation, such as short cycle-length, non-ideal distribution and correlation, low linear complexity, and so on [12]. Since the early implementation of such systems in finite state machines, many researchers have done several improvements to overcome the problems arising from the digitized chaotic systems, like using higher finite precision [13], perturbation-based algorithms to effectively compensate the dynamics degradation [16], and cascading multiple chaotic systems to obtain a greater period [11], but they have not achieved to solve the problem fundamentally.
1 Integer Domain Chaotic Systems (IDCSs), for their part, refer to chaotic systems defined on an integer domain. Their main feature is essentially to solve the problem of dynamics degradation caused by finite precision effects. In 2010, the research team at the University of Franche-Comté (France) has proposed a new IDCS designated as CI (Chaotic Iterations) system [4]. This CI system uses only bitwise operations, thus achieving the speed requirement. Furthermore, theoretical analyses show that these CI systems on integer domains satisfy the Devaney's definition of chaos. Since these systems run on finite sets of integer domains, then the finite precision problem disappears, and there is no need of any transformation from real numbers to binary sequences. CI system is one of effective solutions for the aforementioned problems that occur in the RDCS case.
The first collaborative work has consisted in chaotically combine two random inputs in order to construct a first CI system, called PRIM CI in [1], which has led to better statistical properties for the resulted pseudorandom number generator than each input taken alone. A second category of CI systems called MARK CI has then been introduced in [2]: a mark sequence has been applied to avoid wasteful duplication of values, leading by doing so to an obvious speed improvement. The LUT (Lookup -Table) CI has finally be released and deeply studied in [3]: this last version of the chaotic combination of two input entropic streams has solved flaws exhibited by the MARK CI version of these IDCSs.
In this article, a novel approach for generating IDCS and its proof of the existence of chaos according to Devaney's definition is presented. We focus on the design and circuit implementation of IDCS, with theoretical background and practical details presented for the first time. The IDCS circuit design consists of uniform noise signal generator, noise voltage converter, sample and hold circuit, decoder circuit, iterate function circuit, and digital to analog converter six parts together. The main feature of this kind of IDCS circuit is the use of a sample-hold circuit and a decoder circuit to convert the uniform noise signal into a random sequence, which plays a key role in generating IDCS signals.
The remainder of this research work is organized as follows. The description of IDCS is given in Section 2, while the proof of chaos is provided in Section 3. Circuit design and implementation of IDCS are detailed in the next section. This article ends by a conclusion section in which the contributions are summarized (Section 5).

Description of IDCS
In this section, we first introduce the basic concept of IDCSs.

RDCS
In the traditional RDCS studies, the general form of the iterative equations is: x 0 ∈ R, and ∀n ∈ N * , x n = f (x n−1 ), where f : R → R is the iteration function, while x n−1 and x n are the n − 1-th and n-th iteration respectively. Note that x n−1 and x n are real numbers, which are represented in binary form as 1} and x j 1 , x j 2 , . . . , x j N , . . . ∈ {0, 1} are respectively the integer and fractional parts for x n−1 . Similarly, x k 1 , x k 2 , . . . , x k L ∈ {0, 1} and x l 1 , x l 2 , . . . , x l P , . . . ∈ {0, 1} are respectively the integer and fractional parts for x n . The main features of discrete-time RDCS is that all the bits in x n−1 will be updated by iteration function f at each operation (iteration). Likewise, all the bits in x n will be updated by iteration function f at each operation (iteration).

IDCS
The main ideas of CI systems are summarized thereafter.
Let N ∈ {1, 2, . . .} be a positive integer, B = {1, 0} denotes the set of binary numbers, while B N is the set of binary vectors of size N. For any n = 0, 1, 2, . . ., x n is represented by using N bits in base-2: . . x n 0 ) ∈ B N denote the n − 1-th and n-th iteration respectively. In CI systems, the iterative equation is defined as follows: . . x n−1 0 ), and the following notation is used: . Let us finally remark that, in IDCS, the one-sided infinite sequence of integers s = (s 1 s 2 . . . s n . . .) is usually named a chaotic strategy. Let x k , x j be two binary digits, the corresponding distance be Using the same notations as above, we define the binary variables negation as follows: where j ∈ {0, 1, 2, . . . , N − 1}, and k is usually a term of chaotic strategy s while f is often the vectorial negation recalled previously. With these choices, and according to Equation 4, a more specific formula can be obtained: Let E = (s, x) be a couple constituted by a chaotic strategy and a Boolean vector, that is, Define function G f as follows: With all this material, IDCS is defined as follows: Consider now two real numbers a and b, lesser than 1, which are represented in radix-r format as a = 0.a 1 a 2 a 3 . . . a n . .
where a k , b k ∈ {0, 1, 2, . . . , r − 1}. Then the distance between a and b is given by: The above formula can be generalized to calculate the distance between two onesided infinite sequences of symbols without loss of generality. These remarks lead to the definition of a new distance on the set E, which is defined by: where s = (s 1 s 2 . . . s n . . .) andŝ = (ŝ 1ŝ2 . . .ŝ n . . .) are one-sided infinite sequences of integers, while x andx are binary digits of N bits. More precisely, and in agreement with Equation 7, the distance between s andŝ is: where ∀k ∈ N * , s k ,ŝ k ∈ {0, 1, 2, . . . , N − 1}. Finally, following the 1-norm distance, the distance between x andx is: Remark that d is a distance, as it is defined as the sum of two distances. Before investigating the chaotic properties of IDCS, we have to prove that G f is continuous on the metric space (E, d). In order to do so, the following lemma is first introduced: Conversely, and due to the definition of the proposed distance: for any m n, if To prove that chaotic iterations are an example of chaos, we must first set that G f is continuous on the metric space (E, d).
Theorem 1 G f is a continuous function.
PROOF A continuous function is a function for which, intuitively, "small" changes in the input result in "small" changes in the output. Let ((s, x) n ) n∈N be a sequence of the phase space E, which converges to (ŝ,x). We will prove that (G f (s, x) n ) n∈N converges to G f (ŝ,x). In mathematical notation, ∀((s, Without loss of generality, we assume that δ < 1. According to the previous Lemma 1, if the k 0 first elements of (s) n andŝ are the same, then d s (ŝ,s) < N −k 0 < δ. For instance, k 0 = f loor(−log N δ) + 1 is convenient. Thus ∃n 1 ∈ N, d s ((s) n ,ŝ) < δ for any n n 1 4. According to Equation 5, the corresponding G f ((s, x) n ) and G f (ŝ,x) can be obtained: For n max(n 0 , n 1 ), the k 0 first elements of (s) n andŝ are the same and (x) n =x, so i((s) n ) = i(ŝ) Then, . σ(s) is the result for shifting one integer in the one-sided infinite sequence to the left. So the k 0 − 1 first elements of σ((s) n ) and σ(ŝ) are still the same. So true.
In conclusion, G f is consequently continuous.

Proof of chaos for IDCS
In this section, the chaotic behavior of IDCS is proven according to the Devaney's definition recalled below.
Definition 1 (Devaney's definition of chaos [10]) Let f : X → X be a continuous function on the metrical space (X, d). The dynamical system x 0 ∈ X, x n+1 = f (x n ) is said chaotic if: 1. its periodic points are dense in X;

it is transitive;
3. it has sensitive dependence on initial conditions. The meaning of these properties are detailed thereafter. Let us recall before that.
Theorem 2 [5] If a dynamical system is transitive and has dense periodic points, then it has sensitive dependence on initial conditions.

Dense periodic points
Theorem 3 The periodic points of G f are dense in E.
PROOF We want to show that, for any given ε > 0, a periodic point (s,x) ∈ E can always be found within range ε of any point (ŝ,x) ∈ E.
3. If the k 0 first elements ofŝ ands are the same, then d s (ŝ,s) < N −k 0 according to the previous Lemma 1. So, ∀ε < 1, an integer k 0 can always be found making the relation d s (ŝ,s) < N −k 0 < ε true. For instance, k 0 = f loor(−log N ε) + 1 is convenient.
4. If after k 0 -th iteration, we havex 5. If after k 0 -th iteration, we havex Then, without loss of generality, we can assume that there are i 0 ( N) different bits betweenx andx. These i 0 bits are numbered j 1 < j 2 < . . . < j i 0 respectively. To obtain that, after another k 0 iterations, the following condition is met we must set: Then, within range ε of the point (ŝ,x), one can find the following periodic point In summary, the periodic points of G f are dense in E.

Transitive property
Theorem 4 G f is a transitive map on E.  open ball B b of center (s B , x B ) and radius r B is into U B ). Without loss of generality, we can suppose that r A < 1.
1. We introduce the following notations: 3. If we demand that the k 0 first elements ofs are equal to those from s A , then we obtain d s (s A ,s) < N −k 0 . And for the given r A , an integer k 0 (that is, a sequencẽ s) can always be found to achieve d s (s A ,s) < N −k 0 < r A (for instance, k 0 = f loor(−log N r A ) + 1).
4. If after k 0 iterations, the following condition is satisfied: . .), x A ) ∈ U A has been found that satisfy: 5. If, after the k 0 -th iteration, then, without loss of generality, we can assume that there are i 0 ( N) different bits between x B and the Boolean vector of G k 0 f ((s A , x A )). Once again, these i 0 bits are numbered j 1 < j 2 < . . . < j i 0 respectively. Define now, with n 0 = k 0 + i 0 , making the claim In summary, (G f , E) is transitive, as shown in Figure 1.

Circuit Implementation of IDCS
In this section, IDCS circuit is designed, which consists of several sub-modules: uniform noise signal generator, noise voltage converter, sample-hold circuit, decoder circuit, iterate function circuit, and digital to analog converter. Finally, both the validity and practicability are verified by the experimental results. The uniform noise signal generator is provided in Figure 2. It uses MM5837 broadband white-noise generator with 3dB per octave filter from 10Hz to 40kHz to give noise output ξ(t), which has flat spectral distribution over entire audio band from 20Hz to 20kHz. Output is about 1V P−P of noise riding on 8.5V level. The parameters of components in Figure 2 are capacitances C 1 = 100µF, C 2 = 1µF, C 3 = 0.27µF, C 4 = C 5 = 0.047µF, C 1 = 0.033µF, and resistances R 1 = 6.8kΩ, R 2 = 3kΩ, R 3 = 1kΩ, and R 4 = 300Ω. In Figure 2, output of uniform noise signal generator is about 1V P−P of noise riding on 8.5V level, so it should be converted to 0 ∼ 4V uniform noise signal. Noise voltage converter is shown in Figure 3. The values of each resistance in Figure 3 are R 5 = R 6 = R 8 = R 9 = 10kΩ, R 7 = 40kΩ. The noise output ξ(t) = 0 ∼ 4V.  Figure 4, in which the chip model is LF398. Supply voltage is V + = +15V, V − = −15V. In Figure 4, 3-pin is for analog signal input, 5-pin is an output; capacitor C F = 0.01 ∼ 0.1µF (0.022µF is used here). u c is a square wave signal with frequency 1 ∼ 5kHz (4kHz is used here), the amplitude of output is −5V ∼ 5V. Notice that when C F is enlarged, then the frequency of u c is reduced, Figure 4: The sample-hold circuit and so the iterations are more slower. Conversely, if C F is smaller, then the frequency of u c may be higher, and so the speed of iteration is faster. Due to the speed of the device itself, the speed of iteration has an upper limitation. When doing experiments, C F should be a suitable value, the same for the frequency of u c . That prevents work abnormality. Decoding circuit is shown in Figure 5, while the corresponding comparator circuit is described in Figure 6. The values for each resistance are R 10 = 13.5kΩ, R 11 = 1kΩ, R 12 = 10kΩ, R 13 = 40Ω, and R 14 = R 15 = R 16 = 10kΩ, while the voltage for inverting voltage shifter is E = 4V. According to Figure 6, the logical relationship for input and output of the comparator is as follows: According to Figure 5, input-output relationship of the decoding circuit is: 1. When 3V < η(t) 4V, then η 3 = η 2 = η 1 = η 0 = 1, so 2. When 2V < η(t) 3V, then η 3 = 0, η 2 = η 1 = η 0 = 1, so 3. When 1V < η(t) 2V, then η 3 = η 2 = 0, η 1 = η 0 = 1, so 4. When 0V < η(t) 1V, then η 3 = η 2 = η 1 = 0, η 0 = 1, so It can be seen in Figure 3 that the noise output satisfies 0V < η(t) 4V, and η(t) is the random signal that follows an equal probability distribution (i.e., uniform distribution) within the range [0V, 4V]. In other words, the values in these four intervals ([0V, 1V],[1V, 2V],[2V, 3V],[3V, 4V]) are uniformly distributed, and the correspondence relationship between the size of s n and the four intervals is: Through the above comparison, it is known that both s n and s n 3 s n 2 s n 1 s n 0 follow the uniform distribution, the relationship between them satisfies: 14 which totally corresponds to the chaotic iterations that have been studied in the first part of this article. According to Equation 20, we obtain the corresponding circuit design iteration equation shown in Figure 7. Digital to analog converter is shown in Figure 8, where R 17 = 10kΩ, R 18 = 2kΩ, R 19 = 60kΩ, and R 20 = R 21 = 10kΩ. A DAC0832 is used, it should be configured to allow the analog output x n to continuously reflect the state of an applied digital D 3 D 2 D 1 D 0 = x n 3 x n 2 x n 1 x n 0 on Flow-Through Operation. The logic relationship is: when the input is x n 3 x n 2 x n 1 x n 0 = 0000, the output is x n = 0V; when the input is x n 3 x n 2 x n 1 x n 0 = 0001, the output is x n = 1V; ...; when the input is x n 3 x n 2 x n 1 x n 0 = 1111, the output is x n = 15V. The above correspondence can be adjust by the resistance R 19 . Based on Figure 2-Figure 8, the whole basic IDCS circuit design is shown in Figure 9, with experimental observations of IDCS as shown in Figure 10, respectively.

Conclusions
In order to solve degradation of chaotic dynamic properties by finite precision effect in traditional RDCS, a novel approach for generating IDCS and its proof of the existence of chaos according to Devaney's definition is presented. We then focus on the design and circuit implementation of IDCS, with theoretical background and practical details presented together for the first time. By following these directions, hardware realization method will be further developed in the information hiding field of applications for IDCS.