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1-Bit Full-Adder cell with Optimized Delay for Energy-Efficient Arithmetic Applications

A high speed, low power full-adder cell is proposed using multiplexer logic that has resulted in reduced power-delay product in comparison with other full adder logic styles. The analysis for various full-adder cell designs for propagation delays at 0.06 μm 0.08μm, 0.12μm, 0.18μm, 0.25 μm technologies is carried out. The simulation results depict that the proposed design leads to efficient full-adder cell in terms of propagation delay irrespective of the technology used.