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When are Multiple Gate Errors Significant in Logic Circuits ?

Most recent works on soft errors only address circuit reliability under single gate errors caused by SEUs. In this paper, we compare the probabilities of single and multiple errors. We formulate a criterion based on gate error probabilities for considering multiple gate errors in circuit reliability. Gate error probabilities are increased by technology trends such as the down-scaling of device features and process variation. The probability of multiple errors is generally higher when there is correlation between gate errors. We discuss several examples of correlated errors such as systematic errors and SEUs with a common radiation source. The correlation decreases the number of error combinations to be considered, thereby making multiple gate errors easier to simulate and analyze. We conclude by briefly discussing methods to model multiple errors.