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Implementation of an HSDPA Receiver with a Customized Vector Processor

SIMD paradigm enhances cost and power efficiency of instruction set processors when the executed workload contains appropriate data level parallelism. In this paper, we investigate development of a SIMD ASIP for an HSDPA equalizer receiver for mobile handsets. The ASIP is based on a vector processor template with C-based programming interface. The template is enhanced to capture the 14.4Mbps HSDPA equalizer receiver functionality of the wireless modem. The solution provides improved flexibility compared to the conventional approach while requiring only modest design effort. The template and the design approach can be utilized also for other subsets of modem baseband