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An Analytical Neural Network for Arithmetic Logic Unit of Microprocessors

In this article, we describe a new approach for analog computation using Deep Learning Neural Networks to perform multiple types of mathematical operations within one machine cycle. the weights and biases of the pre-trained ANNs can be used to fabricate the network in hardware either using a FPGA system or discrete components. The trained network has shown the potential to execute simple and complex mathematical operations alongside basic signal processing within an acceptable error limit, without retraining or reconfiguration. Introduction Digital computation offers significant advantages over analog computation, as any mathematical problem can be broken into a set of Boolean primitives that can be operation on by the Arithmetic Logic Unit (ALU) or the Floating Point Unit (FPU) of the microprocessor. Several microprocessors/microcontrollers implement also implement several modifications to operate on more complex mathematical functions in a reduced period of time. Despite these advantages, analog computation offers a greater speed of operation, using reduced number of components but requires application specific circuits for each operation. In this article, we propose a radical redesign of the Arithmetic Logic Unit (ALU) or the Floating Point Unit (FPU) of the microprocessor/microcontroller. Unlike conventional circuits which uses discreet logic sections to perform a specific task, we propose the use of a hardware based Artificial Neural Network (ANN) circuit, which can perform several mathematical operations without retraining or changes in components. ANNs have been fabricated in hardware to perform a variety of tasks including adaptive computation [1] and increasing the interconnection density network-on-chip routers [2]. There have also been several attempts to build mathematical processing circuits using Neural Networks [3], [4]. Several articles have also been fabricated to simulate the properties of artificial neurons [5], [6], [7]. In order to retain the training and adaptive capability of a neuron, the networks have been developed with FPGA kits, which enables a simplified implementation of the ANN, but still uses digital logic to employ the mathematical operations. There have also been several attempts to develop standalone circuits using more conventional hardware [8], [9] and [10]. In the present work, the Neural Network is trained in an application specific manner, using a data preprocessing that is implemented before the training takes place, hence dimensionally increasing the data that is to be input into the ANN. The construction of the ANN is made of standard artificial neurons utilizing tan-sigmoid and linear transfer functions in the hidden and output layers respectively. This also enables simpler circuitry, using a reduced number of components. Once the network is trained, the weights and the biases can be used to construct the electronic circuits for the individual neurons. Simulations have been performed to test several deep learning ANN architectures with two hidden layers employing a maximum of 20 neurons per layer. A single ANN having two hidden layers, trained with the application specific method as mentioned above to perform five mathematical operations (addition, subtraction, multiplication, division and power) alongside denoising of sine, cosine and gaussian profile signals. It has also been necessitated to develop a appropriate analog logic that can be used for practical implementation on a circuit. Efforts are currently underway to develop a practical implementation of the Neural Network circuit. Application Specific Training Method Every ANN is trained for a specific application and hence once trained is incapable of operating successfully for other purposes. Digital circuits reduce any mathematical operation into a set of Boolean primitives, which allows it represent any mathematical operation as a sequence of Boolean addition. Thus, this method only requires the hardware implementation of a Boolean adder. On the contrary, Analog processors require a specific circuit for each separate operation type. Thus the objective has been to train the ANN to operate for several applications, without retraining or reconfiguration. The training set, containing the data vector and the targets of an ANN can be shown as: Trs = {(wi , zi)|wi ∈ R m , zi ∈ tj∀[tj ∈ R]j=1 x }i=1 y (1) where wi is the training vector containing 'm'-attributes, and zi is the training target. All other symbols have their usual meaning. The modified training vector after data pre-processing can be shown as: Trs = { wi ,ak , bl , zi wi ,ak , bl ∈ R , zi ∈ R j=1 x }i=1 y (2) where ak and bl are the extra variables called the 'Decoding Variables' or 'DV'. These variables cycle between various values and the combination of the different values, creates discrete training data sets with the same training vector values. This allows one ANN to train for multiple requirements and generate a trained network that with more post-processing may allow for analytical decision making in the field of intelligent electronics. Simulation Simulation was performed simultaneously using the Matlab Neural Network toolbox and the NeurophStudio software. In order to minimize the number of components that are required, several simulations were performed, to determine the best possible Network architecture as shown in Fig. 1. Figure 1: The architecture of the ANN using two hidden layers containing 20 neurons each. The network chosen was a simple Feed Forward Neural Network, for simplicity of both implementation and further hardware implementation. The values assumed by the DVs are as given in Table 1. Table 1: Decoding Variable Values and the corresponding mathematical operations