{'fraction_non_alphanumeric': 0.03780718336483932, 'fraction_numerical': 0.01606805293005671, 'mean_word_length': 4.693548387096774, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Novel SiC Trench MOSFET with Improved Short-circuit Capability through an Integrated JFET Region

A novel SiC trench gate MOSFET with an integrated JFET region (IJ-TMOS) is presented to improve short-circuit capability in this paper. The integrated JFET consists of an additional P+ source region in the N+ source region and an N-type base region embedded in the P-type base region. In the on-state, electrons will flow through the N-type base region embedded in the p-type base region and the width of the conductive path is regulated by the DC voltage. Under short-circuit conditions, the conduction path of electrons in the integrated JFET region decreases and the effective gate voltage is reduced, resulting in a lower saturation drain (peak short-circuit) current density. Compared to conventional trench MOSFET (TMOS) structure, IJ-TMOS structure reduces 23.2% peak short-circuit current density and improves short-circuit withstanding time from 9.5 μs to 13 μs (enhanced by 36.8%) under 600 V DC bus voltage (for 1200 V-class voltage level design).