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On the scaling of lanthanum oxide gate dielectric film into the subnanometer EOT range

High-k gate dielectric integration had been one of the key technological boosters for 45 nm CMOS technology and beyond. Just a couple technology nodes after adopting the hafnium-based high-k materials, the high-k scaling have already lost its momentum. It is anticipated that the EOT scaling will be in the rate less than 0.03 nm reduction/generation in coming technology nodes. Putting aside the fabrication and reliability issues for high-k integration, high-k films in a couple nanometers are facing scalability issues. For half nanometer EOT gate dielectric, the physical thickness of high-k film will be less than 4 nm, large gate leakage will be encountered again. Meanwhile, the high-k/metal gate and high-k/silicon interfaces will be the primary constraint for achieving gate dielectric film in this EOT range. This work, taking La2O3 as example, demonstrates some of these issues related to the further subnanometer EOT scaling.