{'fraction_non_alphanumeric': 0.029439696106362774, 'fraction_numerical': 0.001899335232668566, 'mean_word_length': 5.16374269005848, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Hardware/Software Co-design of 2D THz SAR Imaging for FPGA-based Systems-on-Chip

This paper presents a novel embedded computing platform for 2D THz synthetic aperture radar (SAR) imaging targeting FPGA-based Systems-on-Chip. One of the key applications of the emerging THz SAR is an unmanned aerial vehicle (UAV) or mobile-robot based high-resolution environment mapping and profiling. Computational power along with energy consumption are the limiting factors with these mobile platforms. In this paper, a computing platform is proposed, which is suitable for stand-alone UAV or mobile-robot based THz SAR sensing. A hardware/software co-design architecture is implemented using multiple hardware accelerators for the THz SAR compute-intensive kernels with a software-managed memory subsystem for large data size transfer between accelerators and external memory. The proposed hardware/software co-design is implemented and evaluated on a Xilinx Zynq MPSoC FPGA board. The experimental results are presented in terms of latency and energy consumption.