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A closed-form energy model for VLSI circuits under wide voltage scaling

This work introduces a closed-form energy model for VLSI circuits that covers a wide voltage range, from deep subthreshold to nominal supply voltage. The model predicts the energy consumption of a given VLSI design based on a few technology- and design-dependent parameters that are obtained from few selected circuit simulations and synthesis reports. The proposed model permits to predict how energy scales down at low voltages (including the minimum energy point), based on the results of place and route at nominal voltage only. The proposed model was applied to a 256-point complex radix-4, Modified Multiple Delay Commutator (MMDC) FFT design in 40nm CMOS. The model was found to capture well the effect of micro-architectural design (e.g., pipe-depth) and technology parameters (e.g., process/voltage/temperature corner). A typical error of less than 5% was observed in the near- and above-threshold voltage region. Overall, the proposed model allows for quick design exploration under wide voltage scaling, while avoiding time-consuming multi-corner and multi-voltage design and simulations. Hence, the proposed model is a useful tool that supports early selection of the best design options having the desired energy profile at low voltages.