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Improved Intrinsic Gettering Technique for High-Temperature-Treated CZ Silicon Wafers

An improved intrinsic gettering (IG) technique for silicon wafers subjected to a high temperature of at least 1200°C is developed. It has been shown that multi-step annealing from low to high temperatures successively can enhance the IG effectiveness for high-temperature-annealed wafers. Moreover, this technique produces the IG ability even in a low oxygen wafer, ∼11×1017 cm-3.