{'fraction_non_alphanumeric': 0.012678288431061807, 'fraction_numerical': 0.0, 'mean_word_length': 5.411167512690355, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A conceptual analysis framework for low power design of embedded systems

The recent growing demand for portable computing and personal communication applications combined with the continuous increment of integration level and operating frequency of VLSI circuits, contributed to increase the importance of power dissipation issues in electronic systems. Most of the available low power design and estimation techniques provides optimization during the last phases of an integrated circuit design, i.e. gate, circuit and layout level. The issue of low power techniques and estimation is almost completely ignored above the gate level. An analysis methodology operating at Register Transfer Level (RTL) is a key factor to obtain early estimation results, while maintaining an acceptable level of accuracy in the results. The goal is to provide the designer the capability of analyzing different solutions in the architectural design space, before proceeding with the synthesis tasks. The aim of this paper is to provide an analysis framework targeting accurate and efficient estimation of power dissipation in embedded systems at RTL level. The proposed model combines the reduced complexity of the RTL description with the accuracy of the gate level description.