{'fraction_non_alphanumeric': 0.03062583222370173, 'fraction_numerical': 0.002663115845539281, 'mean_word_length': 4.7846153846153845, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Statistical Carry Lookahead Adders

Addition techniques are divided into fixed-time and variable-time ones. While variable time techniques can achieve log/sub 2/(N) average addition time for N-bit operands, the hardware overhead have always made fixed-time adders preferable, such as Carry Lookahead and Carry Select. We present a new variable-time addition technique whose average delay is much lower than log/sub 2/(N) and whose overhead is lower than the one of a CLA adder. The new approach is made feasible by a proper application of VLSI dynamic logic design. We show the mathematical proof, the logic implementation, and the VLSI realization of the new adder. We report circuit simulation results and their comparison with the analytical model.