{'fraction_non_alphanumeric': 0.015748031496062992, 'fraction_numerical': 0.0, 'mean_word_length': 5.059523809523809, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Analytical modelling of spurious transitions in adder circuits

Adder architectures are presented here by an unified formalism, and analysed from the delay, complexity and power consumption points of view. An analytical model for the power consumption is derived, assuming that it is proportional to the transition density. Finally, spurious transitions are taken into account when transitions at the input of a cell are separated by one or more cell delays. A redundant to total power ratio is also derived.