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Single-Event Transient (SET) sensitivity into the Clock Networks of FPGAs

In this paper we propose to investigate the impact of Single-Event Transient (SET) on the clock tree resources of field-programmable gate arrays (FPGA) towards radiations. Most of the existing test approaches are focusing on SEU in CRAM, BRAM or DFF and SET in the combinational logic. In this paper we propose to measure the intrinsic sensitivity of the clocks buffers composing the clocks networks of FPGA. A sensor was developed to perform an accurate measurement of the cross section of the different levels of clocks buffers. A review of the clock network is performed, followed by Pulsed Laser investigations on the device layout and accelerators tests.