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Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits

A globally-asynchronous and locally-synchronous (GALS) system has been known as a realistic hardware design solution for many difficulties such as global clock network that arise due to the continuous scaling of semiconductor technology. Although a full scan design method for synchronous circuits is applied to asynchronous circuits to achieve the same testability of their combinational parts, the overhead is extremely high. To reduce the overhead, several full scan design methods have been proposed but they cannot guarantee complete test. In this paper, we propose a bipartite full scan design as a new DFT method for asynchronous circuit where we guarantee complete test for both combinational and sequential parts of circuits with area and performance overhead comparable to the previous best method in terms of overhead.