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Design and Realization of FFT Implementation Unit Based on FPGA

This paper describes the arithmetic principle and discipline of FFT, analyzes rotation factor and data address of the node. It adopts flexible Verilog HDL to design and realize the data address unit of FFT implementation which is 64-point by radix-2. It uses Alter a company's PLD software Quartus II 8.0 (32-Bit) to compile and form top-level entity.