{'fraction_non_alphanumeric': 0.027340513670256836, 'fraction_numerical': 0.0033140016570008283, 'mean_word_length': 5.0703517587939695, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Verification of a VHDL GPS baseband processor using a simulink-based test bench generator

In the last decades, Global Positioning System (GPS) receivers have become more popular and are now incorporated in mobile phone electronics and also in navigation systems, namely in automotive, marine and aerospace equipment. This paper presents the design of various digital signal processing (DSP) and communication blocks which form an integral part of a typical L1-band Coarse/Acquisition (C/A)-code baseband receiver. These modules are designed using synthesizable VHDL code and implemented on a Field Programmable Gate Array (FPGA). Furthermore, a novel satellite signal modulation model is also designed to model how signals are generated by the satellites. This is designed to ultimately generate the VHDL test-bench to verify the functionality of the designed receiver. This model can be extended to cater for second order effects such as Doppler shifts, atmospheric delays and weather conditions. In this work, the noise performance of the receiver is analyzed. It is noted that the minimum signal-to-noise ratio (SNR) that the baseband processor can tolerate is −10 dB given a correlation window of 2 ms.