{'fraction_non_alphanumeric': 0.02252252252252252, 'fraction_numerical': 0.0019305019305019305, 'mean_word_length': 5.617021276595745, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Physical-Model-Based Metal Charging Design Rule Methodology for Integrated Circuits

This paper presents a debut of a physical-model-based (interconnect) metal charging design rule methodology. The methodology promises charging safe for chip transistors with a three-boundary-pinning calibration strategy at the highest, middle, and lowest metal layer. The methodology is demonstrated with a full set of interconnect charging design rules generated for 60-Å gate oxide transistors with gates either unprotected or fully protected. In contrast with the experiment-based methodology, the physical-model-based methodology inherits the advantage of consuming far less test-chip layout space and rule generation time. The methodology would provide benefit in a technology-development environment with its agility in deployment and rule generation. It also makes possible for realizing application-specific charging design rules based on specific emphasis on process or device design. The methodology is fundamental due to the fundamental transistor charging physical models incorporated. It can be implemented universally into different process technologies, such as planar and FinFet-based ones with traditional or HKMG gate oxides of different thickness. The methodology would produce metal charging design rules for technologies developed at advanced process nodes, such as the 7-nm technology or beyond so long as the transistor models, gate oxide characterization data, and backend-process plasma-loading characteristics of the technology are provided.