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A 2-D grouping FIFO based hardware architecture for supporting 36-mode hybrid-radix FFT design in 3GPP-LTE systems

In this paper, we propose a 2-D grouping FIFO based FFT hardware architecture, supporting 36 different FFT sizes defined in 3GPP-LTE systems. Also, the important design foundation is to develop a hybrid-radix computing kernel engine, including 4 configuration types. In a design implementation via TSMC 90-nm CMOS technology, the reconfigurable FFT chip only has a core area occupation of 1.51 mm2, dissipating power of 17.12 mW in average, and achieving speed of 111.11 MHz.