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FPGA bulding blocks for an hybrid base band digital predistorter suitable for 3G power\amplifiers

This paper presents a new implementation of the adaptive digital base band predistortion (DPD) system in order to compensate high power amplifier (HPA) nonlinearities used in third generation systems (WCDMA). The proposed implementation of the predistorter architecture is based on FPGA-based look-up table (LUT) which is filled up by performing an adaptive algorithm on a DSP. In this work the attention is focused in the FPGA design considerations.