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Upgrading obsolete integrated circuits using Field Programmable Gate Arrays (FPGA)

Digital electronics began with relay ladder logic progressing through vacuum tubes, discrete transistors, integrated logic circuits and finally large scale integrated circuits like various computer circuits. The software investment may in some cases outweigh the hardware investment in many computer systems which require software certification, such as Automatic Test Equipment (ATE) or Avionics boxes. Computer circuits with their high levels of software investment are also some of the fastest circuits to become obsolete as newer generations of processor are introduced every two to three years. Legacy hardware usually consists of a central processor unit (CPU), memory chips, and circuit boards that are becoming obsolete, which means that design will require engineering to upgrade the design. Field programmable gate array (FPGA), complex programmable logic device (CPLD), or application specified integrated circuit (ASIC) devices may allow the legacy logic to be embedded, whether a CPU, arithmetic logic unit (ALU), and/or memory storage unit (ROM/RAM). The most commonly used device is FPGAs, which use VHDL and Verilog as the hardware description language in the system. FPGAs reduce production cost, and increase reliability within the ATE. In most cases, a team of engineers will have to reverse engineer the legacy system to understand the purpose of each component. Upgrading an existing system or design can be very challenging, especially when a system interfaces with other complex systems. Poor documentation can cause major setbacks as well. Many companies will hesitate to pursue a reverse engineering project because of the high risk factors. We upgraded the a legacy project that interfaces with multiple subsystems using an Embedded PC and FPGA to interface with legacy drawers or instruments. The FPGA architecture incorporates legacy CPU, memory unit, countdown clock, interrupt controller, serial circuits, parallel circuits, and a runtime module. The runtime module uses a common bus that allows the embedded PC to send an instruction to the processor and a translation module (TM) module to execute the instructions. Our design team analyzed and redesigned the legacy minicomputer based station controller using the same legacy op-codes that interface between the legacy and modern automatic test equipment (ATE). This paper explains our approach on how our design team redesigned and reversed engineered the station controller system architecture using a Virtex-5 FPGA.