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Power, Performance And Thermal Management Using Hardware Performance Counters

CPU Performance, Voltage and Temperature are the primary design constraints for the high compute systems today. With increased demands of high compute and processing capabilities, there is a need to measure and optimize system power requirements wherever possible. Modern Operating systems provide efficient resource managers but those are not working at a lower level and rather are more generic in behavior. Though the chipsets and Operating Systems are providing various techniques like DVFS (Dynamic Voltage and Frequency Scaling), DPM (Dynamic Power Management) but these are generic approaches to power management and agnostic to the use-case impact. System level power management must consider the variable nature of the use case and the effect of environment rather than just applying a single rule to save power. In the way it is also supposed to detect quickly and apply an apt technique based on situation and given environment. Temperature plays a vital role apart from the CPU status during the high compute processing. Thermal management must be taken care before taking an overall decision and not just the processing demands from the peripherals. This paper presents a mechanism where the Hardware Performance Monitoring Counters (PMC) to be used to empirically, yet accurately represent the dynamic power situation in given environment. Results in this paper suggests CPU being the main heat producer and within the CPU Microarchitecture the heat can be empirically co-related to overall power and temperature read during the use case. Cache miss to hit ratio, dram speeds and bus speed are also the contributors of overall CPU heat