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Efficient approaches to design a reversible floating point divider

In this paper, we propose a reversible n-bit divider, where n is the number of bits of the operands of dividend. Two approaches for constructing a compact reversible divider have been presented here. The first approach uses conventional division array and the second approach uses high speed division array. Both of the approaches can handle floating point numbers. Several theorems on the numbers of gates, garbage outputs and quantum cost of the reversible n-bit divider have been shown. The comparative study shows that the proposed designs can work with fractional numbers where as existing designs can not. Proposed designs are also much better than the existing approaches considering all the efficiency parameters of reversible logic design which includes numbers of gates used, quantum cost and garbage outputs.