{'fraction_non_alphanumeric': 0.023492560689115115, 'fraction_numerical': 0.0, 'mean_word_length': 6.3028571428571425, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
HtComp: bringing reconfigurable hardware to future high-performance applications

Current trends in computer architecture are increasingly moving towards heterogeneous platforms, now including FPGAs as first-class components enabling unprecedented levels of performance and power-efficiency. Programming such next-generation machines is however extremely difficult as it requires architecture-specific code and low-level hardware design. This paper describes the main outcomes of the HtComp project, a two-year research programme aimed at exploring methodologies and tools allowing the automated generation of FPGA-based accelerators from high-level applications written in traditional software languages. In particular, the paper describes the main contributions brought by the project, covering the generation of hardware systems from high-level parallel code, the performance-oriented optimisation of memory architectures tailored on the application access patterns, as well as the automated definition of application-driven special-purpose on-chip interconnects. Overall, the above innovations contributed to creating a viable path allowing generic software developers to access tomorrow's hardware-accelerated high-performance platforms with minimum development overheads.