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Hierarchical Optimizations for High Speed Implementation of Modular Exponentiation in ASIC

This paper presents a new arithmetic architecture hierarchically optimized for implementing modular exponentiation in ASIC. We combine a new version of high radix Montgomery multiplication algorithm with a super-pipeline design. With this algorithm, modular exponentiation (ME) can be decomposed into a series of primitive operation (PO) matrixes. All the POs are scheduled on the pipeline by employing column-sharing strategy, and inside the PO the partial results are compressed first by Wallace tree to assure only one carry propagation in the critical path. We also investigates speed/area tradeoffs using a 0.18um library, and gets that the ratio of the increasing in speed to the extra area used decreases as radix length k steps up from 2 to 64. A ME coprocessor SEA-II with k=32 was fabricated, with 140 MHz clock, a decryption rate of 6353 Kb/s can be achieved for 1024-bit RSA.