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A high data-rate, software-defined underwater acoustic modem

Most underwater acoustic modems offer only low data rates. This is largely because they operate at low frequency, which limits the channel bandwidth available, and hence the symbol rate. The low frequency acoustic channel suffers from substantial multipath and doppler effects, which constrain the signal quality at the receiver. As a result only 1 or 2 bits per symbol are achieved, with the effective data rate further reduced by error control coding. High frequency acoustic signals are heavily attenuated in water, severely constraining the range of high frequency links. High frequency signals however offer substantially greater signal bandwidth, and probably improved channel quality which guides our design choice of a high frequency acoustic modem for underwater communication. Contemporary Field Programmable Gate Arrays (FPGAs) can provide good system functionality at low cost and with the flexibility to perform rapid testing and development of communication algorithms. They may also be competitive in production systems. In this paper we describe current progress in development of a high frequency, high data-rate modem which is implemented entirely in FPGA. This differs from most existing modems which are based on DSP processors. Being software defined, the modem is flexible because the parameters can be reconfigured with relative ease, minimising the cost of rework as the design evolves. This modem will not only demonstrate the feasibility of high frequency FPGA based modems, but will also be a valuable tool to provide a better understanding of the high frequency acoustic channel, and demonstrate the utility of absorption to enhance channel re-use rates in underwater acoustic networks. The modulator has been implemented in the FPGA, to produce laboratory and open water tests that conform to modelling. The demodulator has been implemented in Matlab, and recovers the carrier, code synchronisation and data from recordings of both laboratory and open water tests. Coding of the demodulator into the FPGA is currently in progress.