{'fraction_non_alphanumeric': 0.03729146221786065, 'fraction_numerical': 0.019627085377821395, 'mean_word_length': 4.964912280701754, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A spread-spectrum clock generator with FIR-embedded binary phase detection and 1-bit high-order ΔΣ modulation

This paper describes a spread-spectrum clock generation method by utilizing a ΔΣ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order ΔΣ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by nonlinearity of the bang-bang phase detector (BBPD). The ΔΣ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. Based on the proposed architecture, a 3.2GHz spread-spectrum clock generator (SSCG) is implemented in 65nm CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5dB and 11dB with 10kHz and 100kHz resolution bandwidths respectively, consuming 6.34mW from a 1V supply.