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Performance analysis of BMC and Decision Units in the differential analog Viterbi decoder

In modern high-speed telecommunication systems a direct analog approach enables the A/D converter to be excluded from the Viterbi decoder implementation and avoids the speed bottlenecks in digital computation. The differential structure eliminates the need for the conventional trace-back memory thus enabling on-line decoding after initial transitional stages. This paper presents the circuit level analysis of branch metric calculation and decision units for a differential analog Viterbi decoder addressed to a (2,1,7) convolutional code. The speed and power consumption in these units is simulated with 0.13 mum CMOS technology. Further, the impact of inaccuracies in these units on the decoder performance is estimated.