{'fraction_non_alphanumeric': 0.02109300095877277, 'fraction_numerical': 0.0009587727708533077, 'mean_word_length': 5.735483870967742, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Current Transport in Polysilicon-channel GAA MOSFETs: A Modeling Perspective

In this work, we compare different modeling approaches typically adopted to address current transport in polysilicon-channel MOSFETs. The analysis is focused on cylindrical gate-all-around devices with deca-nanometer dimension, due to the strong relevance recently gained by such devices in the field of 3-D NAND Flash memories. Pure drift-diffusion simulations under the effective medium approximation are compared to simulations accounting for polysilicon grains and grain boundaries, either keeping pure drift-diffusion transport or mixing intra-grain drift-diffusion with inter-grain thermionic emission. Some nonnegligible differences among the predictions of the three modeling approaches are highlighted and explained as a function of the device working regime, temperature and average size of the polysilicon grains. Results represent an important step towards a better understanding and a better extraction of the parameters of polysilicon-channel devices.