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A 300MHz direct digital frequency synthesizer based on improved redundant prediction CORDIC in 0.35um CMOS

Direct digital frequency synthesizer (DDFS) plays an important role in modern digital communications. This paper proposes a novel implementation of a 300MHz direct digital frequency based on modified CORDIC in 0.35µm CMOS technology. The CORDIC algorithm is a well-know iteration method for the efficient computation of fundamental functions, but each iterate selects the rotation direction by analyzing the results of the previous iteration. In this paper, an improved redundant method is employed and the rotation directions can be predicted directly from the binary values of the initial input angle. This method allows the parallel CORDIC to making a much faster implementation possible. At the same time, pipelined accumulator and carry-save arithmetic are employed to achieve the maximum speed. The DDFS is fabricated in 0.35um N-well 2P3M CMOS process, occupied an area of 3.2×3.6mm2. The measured SFDR is 64.22dB at 20MHz output of 300MHz clock rate.