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(Invited) Effect of Threshold-Voltage Instability on SiC Power MOSFET High-Temperature Reliability

The gate-bias stress-induced threshold-voltage instability observed in lateral SiC MOSFETs is also present in fully processed SiC DMOSFETs, and the shifts are comparable in magnitude, and similar in their response to bias-stress time, gate-oxide field, and temperature (1). Therefore, it is highly likely that the same near-interfacial oxide trapping mechanisms are the cause of the observed instability in both the ID-VGS and IDVDS characteristics of SiC power MOSFETs.