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Comprehensive Characterization of Warpage and Fatigue Performance of Fan-out Wafer Level Package by Taking into Account the Viscoelastic Behavior of EMC and the Dielectric Layer

In this study, the warpage in step of fan-out wafer level package (FOWLP) manufacturing processes with the chip-first and die face-up is investigated through finite element simulation with the help of element birth and death technique. In order to obtain more accurate and reliable simulation results, the viscoelasticity of epoxy molding compound (EMC) and the dielectric material is considered simultaneously. For warpage issues, the effects of number of re-distribution layers (RDLs) and Cu ratio in the effective RDLs are also analyzed. Further, the influence of material constitutive model on fatigue life of solder joints in thermal cycling tests (TCT) has also been characterized extensively. Simulation results show that a reduced process warpage of reconstituted wafer can be achieved after taking into account the viscoelasticity of EMC and the dielectric material. Wafer warpage increases sequentially during the processes of post mold cure (PMC), backgrinding (BG) and fabrication of the first layer of RDLs. With increasing the number of RDLs, the warpage appears to become much slighter. The same results can be seen in the process with more Cu ratio in RDLs. Using elastic models of EMC and dielectric material leads to underestimation of fatigue life and maximum Mises stress of solder joints. The fatigue life of solder joints increases with the increase of Cu ratio in RDLs.