{'fraction_non_alphanumeric': 0.021346469622331693, 'fraction_numerical': 0.0, 'mean_word_length': 5.288659793814433, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Electron tunnelling from rough surfaces: an application to TPFG EEPROM cells

The endurance of textured polysilicon floating gate (TPFG) EEPROM cells under repeated WRITE/ERASE cycles is studied as a function of the surface roughness. Electron tunnelling from non-planar surfaces is modelled for current injection from a single tip, and the corrugated surface is taken as a distribution of separated tips. A simple degradation model, based on charge trapping at the polysilicon/dielectric interface, is also introduced, and is able to lead to significant conclusions about the reliability of the memory cells.