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Truncated multiply-and-accumulate units for FIR filter implementation with reduced coefficient length

We develop a fused multiply-and-accumulate unit that combines truncated multiplication techniques with the accumulate operation. Such a unit is well-suited for FIR filter implementation. For many signal-processing algorithms, the product of two n-bit numbers is often calculated as an n-bit result. Rather than computing the 2n-bit product and then rounding to n-bits, we can reduce the power and area required by using a truncated multiplier. Several truncated multiplication approaches have been proposed which yield results very close to those obtained when a 2n-bit product is rounded to an n-bit result. These ideas can be expanded to a fused multiply-and-accumulate (MAC) operation.