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Write-assisted subthreshold SRAM by using on-chip threshold voltage monitoring circuit

In this paper, we propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. In subthreshold digital circuits, though the circuits can achieve ultra-low power dissipation, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. In particular, because the write operation of SRAM is prone to fail due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a less write operation failure rate and smaller write time variation than a conventional 6T SRAM.