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Power reduction on clock-tree using Energy recovery and clock gating technique

Power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. Hence, low power clocking schemes are promising approaches for low-power design. We propose four novel energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. These flipflops operate with a single-phase sinusoidal clock which can be generated with high efficiency. In the Tanner 250nm CMOS technology, we implemented these energy recovery clocked flipflops through an H-tree clock network driven by a resonant clock-generator to generate a sinusoidal clock. The proposed flip-flops exhibit more than 80% delay reduction, power reduction of up to 47%, as compared to the conventional energy recovery flip-flop. Simulation results show a power reduction of 90% on the clocktree and total power savings of up to 83% as compared to the same implementation using the conventional square-wave clocking scheme and flip-flops. In this paper, we also propose clock gating solutions for energy recovery clocking. Applying our clock gating to the energy recovery clocked flip-flops reduces their power by more than 1000 times in the idle mode with negligible power and delay overhead in the active mode. A pipelined array multiplier is designed which show a total power savings of 25%–69% as compared to the same multiplier using conventional square-wave clocking scheme and corresponding flip-flops.