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Foundry approach for layout risk assessment through comprehensive pattern harvesting and large-scale data analysis

Semiconductor foundries typically analyze design layouts for criticality as a precursor to manufacturing flows. Risk assessment is performed on incoming layouts to identify and react to critical patterns at an early stage of the manufacturing cycle, in turn saving time and efforts. In this paper, we describe a new bottom-up approach to layout risk assessment that can rapidly identify unique patterns in layouts, and in combination with techniques like feature filters, location mapping and clustering, can pre-determine their criticality. A massive highly performant pattern database of single and multilayer patterns, along with their features and locations, forms the core of the system. While pattern analyses may be pertaining to the short range of design space, silicon defects and simulations extend to a much larger scope. Therefore, the database is extended to defect data extracted from Silicon inspection tools like Bright Field Inspection (BFI) and Scanning Electron Microscopy (SEM). When stored in an optimized manner, it can aid fast and efficient large data analysis and machine learning within critical tapeout review time which is typically a few days. Machine learning combined with design feature filters can then be used for anomaly detection and failure prediction at layout, layer and pattern levels. As a result, outlier patterns can be visually reviewed and flagged for custom targeted simulations and silicon inspection. Further, adding new layout patterns to the pattern database will make it possible to repeat this exercise for subsequent new layouts.