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Exploration of Negative Capacitance in Multi-Gate Junctionless Transistor

In this work, the electrical performance of the negative capacitance gate-all-around nanosheet junctionless transistors (NS-NCJLT) at advanced technology node is studied. The NS-NCJLT shows better performance than NS-JLT such as the higher driving current and steeper subthreshold slope (SS). Besides, the NS-NCJLT is proved has the best performance after benchmarked against its counterparts based on FinFET and nanowire structures. Then it is found that the smaller-size NS-NCJLT benefits more from NC effect, which indicate it could be applied more appropriately to the 7-nm device and beyond. Finally, we have investigated the influence of self-heating effect on NS-NCJLT. The results show that although the introduction of ferroelectric layer increases the heat conduction path, the electrical properties of NS-NCJLT still be enhanced.