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Electrical and geometrical circuit performance using an advanced sea-of-gates philosophy

A sea-of-gates array has been designed to support random and regular logic and analog circuits. Its philosophy is to promote wiring and communication instead of packing as many transistors as possible on the array. At the global level, because of the saved routing area, densities as good as those obtained with a standard cell design style are achieved. Some important results on circuit densities and electrical performance are presented and discussed for the different circuit families. These results are compared with those obtained with other design styles. Several suitable CAD (computer-aided design) tools are presented