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A binary tree architecture for application specific network on chip (ASNOC) design

A mix-mode network on-chip (NOC) interconnection architecture is proposed In this work. The proposed architecture makes use of a globally asynchronous communication network and a locally synchronous bus. Firstly, a local bus is given for a group of cores so that all communications within this local bus are exclusive in time. In order to represent the ratio of communications of this local bus, an user has to provide a communication ratio (CR) of each pair of local bus groups. After that, the two local buses with the highest CR are grouped to be the first switching point for the globally asynchronous network. Then, one can regard the two groups using a switching point as a new group. The new CR hence can be determined from the new and each other local bus group. Similar process is performed to form the next switching point. Finally, a binary tree (BT) is built by setting each internal tree node a switching point while each leaf a local bus. In addition, the switching circuit cost can be decreased while the performance is increased. The simulation results show that the proposed architecture of NOC is better than the general purposed SPIN architecture.