{'fraction_non_alphanumeric': 0.014492753623188406, 'fraction_numerical': 0.0, 'mean_word_length': 5.38655462184874, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
An Embedded Methodology for FPGAs' Digital Distance Relay Design and Analysis

This paper proposes a methodology for distance relay design to detect the fault location and mark out the protective region. We followed the intellectual property (IP) cores concept in system on chip to accomplish the development of an intelligent digital distance relay. Therefore, the field programmable gate arrays (FPGAs) technique was applied to design and implement the digital distance relay associated with the proposed method. In additional to verify the validation of the digital distance relay, we compare the result with Matlab simulation check. Then we concluded the performance of the designed distance relay is indeed superior in speed and accuracy with flexibility