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A Defect-Tolerant Memory Nanoarchitecture Exploiting Hybrid Redundancy

Nanoelectronic devices have emerged as the potential fabrics for future computing systems as well as memories. However, due to the imperfect fabrication process, the excessively high defect rates prevent nano memories from being practically feasible. In this paper, we propose a defect-tolerant memory nanoarchitecture for nanowire crossbar memories. By using soft redundancy (runtime utilization of spatial/temporal access locality) in combination with hardware redundancy (redundant columns and rows), the proposed technique can achieve effective defect tolerance while reduce the cost as compared to the existing defect mapping techniques and ECC-based designs. Simulation results on memory systems running SPEC CPU2000 benchmarks demonstrate the effectiveness in defect tolerance and cost efficiency of the proposed approach.