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A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs

The long latency feature of the conventional lookup tables (LUTs) puts a limit on their applications in a VCO-based continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC). In this paper, a latency-optimized scheme is proposed to break this limitation. The search process of the LUT is achieved by a multi-step procedure to calculate the number of ‘1’ in the address code with low latency. The LUT is designed in a 180-nm CMOS process. Compared to a conventional implementation, the latency can be reduced by 25% with the proposed technique.