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A 40 nm, 454MHz 114 fJ/bit area-efficient SRAM memory with integrated charge pump

In this paper, a 256 kbit high speed, ultra-low power SRAM is presented. It runs at a speed of 454MHz with a power of only 29 pJ/access or 114 fJ/access/bit. Retention mode leakage is only 86 μW. Combining three novel techniques with proven methods assures a design which can cope with the challenges introduced by deep submicron technologies. The first technique, an integrated charge pump, enables low swing signals to be used to save active energy while only one external supply is required. A second novelty is the use of a low swing scheme for both read and write. This results in simplified local periphery which reduces area overhead to a very low 4 %. Last, segmented horizontal control lines ensure correct operation in the presence of large RC-delays on long metal lines. The design was fabricated in a 40nm low standby power technology. Measurements prove the functionality of the proposed techniques.