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Defect isolation using scan path testing and electron beam probing in multilevel high-density ASICs

Electron beam probing is a powerful technique for analyzing functional failures in integrated circuits. A common approach used for isolating defects is to trace a bad signal on a failing pin through the circuit. The inputs and outputs of each logical node can be compared against simulated results to determine functionality. This method has several limitations which are discussed in this paper -- most notably, it is often an extremely time consuming process. Scan- path designs have been introduced which increase the observability and controllability of internal circuit nodes. The use of ASIC scan-path architecture is increasing due to the improved testability compared to non-scan designs. Scan-path architecture also offers opportunities for more efficient failure analysis of functional failures. In this paper we present a successful method of defect isolation using scan-path testing in conjunction with electron beam probing. Using this method, a fault area or node is identified using a test datalog, and the defect is precisely located using an electron beam probe station. This paper discusses in detail the integration of scan testing with electron beam probing for isolating various defects on devices with multi-layer (3+) metallization, 500 K usable gates and 2000 scan elements.