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A fully digital low-power wide-speed-range BPSK demodulator

A novel binary phase-shift keying (BPSK) demodulator architecture is presented. By using fully digital and trigger receiving method, the proposed demodulator can work properly at a wide speed range and hence can be applied in different applications such as wireless communications, biological implants and portable facilities, etc. The proposed demodulator was implemented by a 0.35-μm complementary metal-oxide-semiconductor (CMOS) process and the chip area is about 0.5 mm2. Measurement results reveal that the proposed demodulator can successfully demodulate the 100 MHz/10 Mbps BPSK signal which is the highest performance. While when it is used to demodulate the lowest speed BPSK signal of 10 MHz/1.0 Mbps, the power consumption is only 319 μw, and the bit error rate (BER) is less than the low test bond (10–9). Measurement results also show that the designed demodulator can work at 100% data-rate-to-carrier-frequency (DRCF) ratio with the frequency up to 25 MHz.