{'fraction_non_alphanumeric': 0.03032490974729242, 'fraction_numerical': 0.005776173285198556, 'mean_word_length': 5.328767123287672, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Analysis of pattern density on process proximity compensation

The challenges of ever-smaller CD (Critical Dimension) budget for advanced memory product requires tight ACLV (Across-Chip Line-width Variation) control. In addition to the lithographic MOPC (Model-based Optical Proximity Correction) for DCD (photo CD) control, the process correction for etch proximity effect can no longer be ignored. To meet on our requirement on final CD accuracy for critical layer, a set of test pattern, that represents memory array in one of our critical layers, has been generated for both photo and etch process characterizations. Through the combination of different pattern-coverage areas in the test mask and wafer map design, various local (chip-level) pattern densities of 40%~70% and global (wafer-level) pattern densities of 35%~65% were achieved for optical and etch proximity study. The key contributors to the process proximity effect were identified and voluminous data has been extracted from the memory block like patterns for statistical analysis. The photo and etch proximity effects were hence modeled as function of memory block separation, local pattern density as well as global pattern density. Finally, the respective photo and etch proximity effects through model-based proximity correction and rule-based proximity correction were applied in a multi-step flow to products.