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Survey of Architectures and Performance of ATM Switches Based on Deflection Routing

ATM switch architectures based on deflection routing are here examined, described in terms of a general switch model and compared with regards to their internal operations. Their common feature is the availability of multiple I/O paths through a multistage unbuffered interconnection network where conflicts for the same interstage link are dealt with by deflecting packets onto the wrong path. The main engineering parameter of the architecture, that is the number of network stages that provides a given packet loss performance is studied in depth. In particular it is found that basically all the examined architectures have a complexity on the order of N log 2 N in the range of switch size of usual interest. Furthermore it has been possible to rank the architectures with comparable complexity based on the loss performance they provide. The Shuffleout switch turns out to behave better than other architectures previously known as providing an optimal performance.