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Lessons Learned from Designing a 65 nm ASIC for Evaluating Third Round SHA-3 Candidates

In this paper we present the implementation results for all five SHA-3 third round candidate algorithms, BLAKE, Grøstl, JH, Keccak, and Skein in a standard-cell-based ASIC realized using 65nm CMOS technology. The ASIC includes two sets of implementations developed independently and with different optimization targets, and includes a reference SHA-2 implementation as well. We believe that having the results of two separate sets of implementations allows us to better identify the valid design space for all candidate algorithms. We present data showing the evolution of the solution space for each algorithm from simple synthesis estimations to the final implementation on the ASIC and show that post-layout results can differ by as much as 50% from synthesis results.