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A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog

In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consumed during different iterations of encryption, are generated in parallel with the encryption process. This lowers the delay associated with each round of encryption and reduces the overall encryption delay of a plaintext block. This leads to an increase in the message encryption throughput. The proposed pipelined design was modeled and validated in SystemVerilog hardware description language. The pipelined design was synthesized using the Synopsys Design Compiler tool and LSI_10K technology library. The synthesized gate-level netlist can operate at 40MHz frequency. To get an estimate of the speed gain by the hardware implementation, a virtual system was created using the Virtutech® SimicsTM [7] software to emulate the execution of a “C” program that implements the AES128 encryption in software. The utilized Simics virtual system is based on Intel’s x86 architecture with the 440BX chipset and has a 2GHz Pentium4 processor. The results indicate that the hardware implementation proposed in this paper is at least 60 times faster than the software implementation.