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A digital clock and data recovery architecture for multi-gigabit/s binary links

In this paper we present a general architecture for digital clock and data recovery (CDR) for high speed binary links. The architecture is based on replacing the analog loop filter and VCO in a typical analog PLL-based CDR with digital components. We provide a linearized analysis of the bang-bang phase detector and CDR loop including the effects of decimation and self-noise. Finally, measured results are presented that corroborate the modeled results.