{'fraction_non_alphanumeric': 0.03159609120521173, 'fraction_numerical': 0.011074918566775244, 'mean_word_length': 5.166666666666667, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 2, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Challenges of Finer Particle Detection on Bulk-Silicon and SOI Wafers

Introduction As device geometry continues to shrink and die sizes grow, particulate contamination [1, 2] as well as chemical contamination [3, 4] has an ever-increasing impact on device yields. Of the many potential contamination sources, particle generation within processing equipment is by far the most frequent cause of yield loss in the manufacture of modern ULSI devices. In order to enhance the yield, therefore, more stringent particle control is required throughout wafer-processing operations [1, 2]. Fundamental to the reduction of process/equipment-generated contamination is the monitoring of the wafer-surface particle level [5-8]. Automated laser-scanning particle-detection systems have been used in semiconductor manufacturing lines to determine the quantity, size, and location of the particles on unpatterned silicon wafers. As the size of potentially yield-limiting particles has decreased along with the decrease in the feature size of ULSI devices, a clear need has arisen for systems capable of detecting finer particles. In fact, according to the International Technology Roadmap for Semiconductors (ITRS), the requirements for critical particle-size control in semiconductor manufacturing lines will be tightened in accordance with the trend to shrink the feature size of devices, as is shown in Fig. 1 [9]. Although we have started pilot production of 65-nm CMOS devices, the minimum detectable diameter of the currently available wafer-inspection systems remains under optimized conditions at the 50-60-nm level in optical diameter, almost at the same level of the feature size of leading-edge devices. It is obvious that sub-50 nm particle detection is necessary at advanced technology-nodes. At the 65-nm node and beyond, silicon-on-insulator (SOI) wafers will be required for higher performance devices and/or lower power-consumption devices. In the latest edition of ITRS, however, particle detection on SOI wafers was pointed out as one of the metrological challenges brought about by the additional optical reflections from interfaces within the SOI stack [9], as well as even more light-scattering from rough interfaces [10]. In fact, the minimum detectable defect size of the system for inspecting SOI wafers remains in the >> 100 nm range, much larger than the nominal minimum detectable size for bulk-silicon wafers. Finer particle detection on SOI wafers is also a challenge. This paper focuses on particle detection on bulk-silicon and SOI surfaces and describes several challenges faced in providing finer particle detection to meet the ITRS requirements or even surpass them. Emphasis is placed on the importance of the control of silicon surface morphology, such as crystal-originated pits (COPs), micro-scratches, and micro-roughness, which prevent the detection sensitivity from being raised. A new particle-detection system employing a deep-ultraviolet (266 nm) laser as the light source to raise its sensitivity level both on the bulk-silicon and 10 100