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Parametric nano-electrical analysis for SiC junctions of a packaged device

Precise and accurate electrical characterization of power electronics device die structures at the wafer level is essential to compare device operation to the design and to model reliability issues. In this paper, a parametric analysis for local electrical characterization in two dimensions for a discrete packaged commercial silicon carbide MOSFET is presented. On the cross-sectional sample, electron beam-induced current (EBIC) in a scanning electron microscope (SEM) is used to locate the pn junction of the body diode, evaluating the effect of the electron beam energy on the imaging of this area. Scanning Capacitance Microscopy (SCM) based on an Atomic Force Microscope (AFM) is employed to analyze the junction areas of the packaged silicon carbide MOSFET device. A parametric approach is proposed to reveal the local electrical properties of all layers in the MOSFET (n-, p-type, low, medium and high doping levels of doped SiC epilayers and SiC substrate and the silicon gate). The objective of the paper is to expose the potentialities of EBIC and SCM to perform comprehensive characterization of a SiC packaged device. The influence of the applied voltages (VDC and VAC) during SCM acquisitions is investigated, in order to quantify their effect on the analysis of the doped layers of the MOSFET SiC. The nano-electrical experiments are supported by TCAD simulations of the tip/sample nano-MOS contact to confirm the interpretation in terms of doping levels of the AFM maps of the silicon carbide die.