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A low power based system partitioning and binding technique for multi-chip module architectures

In this paper, we present a low power targeted high-level synthesis framework for the synthesis of Multi-Chip Modules (MCM). This new framework is based on minimizing the switching activity on the functional units as well as the inter-chip buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for system partitioning. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs.