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5T SRAM With Asymmetric Sizing for Improved Read Stability

Conventional 6-transistor (6T) SRAM scaling to newer technologies and lower supply voltages is difficult due to a complex trade-off space involving stability, performance, power, and area. Local and global variation make SRAM design even more challenging. We present a 5-transistor (5T) bitcell that uses sizing asymmetry to improve read stability and to provide an efficient knob for trading off the aforementioned metrics. In this paper, we compare the 5T with the conventional 6T and the 8T and show how it can be a flexible, intermediate alternative between the two. We also investigate single-ended sensing for the 5T. Finally, we present measurement results in a 45 nm test chip that demonstrate the functionality of the 5T. Through a combination of write assists, the 5T can demonstrate comparable writability down to 0.7 V, while showing no read errors down to 0.5 V.