{'fraction_non_alphanumeric': 0.021521906225980016, 'fraction_numerical': 0.006917755572636433, 'mean_word_length': 5.0, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
On-line software-based self-test for ECC of embedded RAM memories

Error Correcting Code (ECC) techniques aims at providing concurrent correction and detection of single and multiple faults that can affect the memory array. The literature largely discusses how to protect the memory content with ECC codes. In this paper, we discuss about faults affecting the ECC logic in charge of encode and decode the ECC codes. It is a common perception that faults in such a calculation unit can only rise the occurrence of false positive behaviors. This assumption is not always true because some latent faults require a careful excitation sequence, including intentional corruption of the memory content to verify detection and correction ability. The manuscript provides a complete taxonomy of failing behaviors. Furthermore, it illustrates how to generate a proper flow of memory accesses to be finally translated into a Software-Based Self-Test (SBST) program. The paper provides an automotive case of study by STMicroelectronics; the analyzed ECC logic implements a Single Error Correction Double Error Detection (SEC-DEC) to protect RAM memories. The proposed method achieves the 93% over around 30K stuck-at faults and the generated SBST test program length is around 0.5 ms at a 128MHz system frequency.