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A full FPGA-based implementation of an adaptive digital predistorter

This paper presents an adaptive Digital Predistorter (DPD) for Power Amplifier (PA) linearization whose implementation and real time adaptation are fully performed in a Field Programmable Gate Array (FPGA) device responsible for the co-processing tasks. We consider the PA as a long-term time-variant (due to aging, heating, load impedance variations) nonlinear system capable to operate in reconfigurable scenarios. Therefore, the PA behavior needs to be periodically monitored in order to eventually adapt the DPD to counteract possible changes in its behavior or in its mode of operation. Unlike in [1], there is no need to stop the transmission and switch into a training mode, because the DPD adaptation can be enabled/disabled by the user in a hot manner. It is thus possible to simultaneously transmit and adapt the DPD thanks to the real-time parallel processing performed by the FPGA. This architecture improves the DPD configuration in [2], where the predistortion function was already implemented in a FPGA by means of a set of basic predistortion cells (BPCs), but the update of the contents of these BPCs (complex gains stored in look-up tables) was performed in a host PC. Following the same principles explained in [3], the adaptation of the DPD is carried out using the Least Mean Square (LMS) algorithm to update all single complex gains that fill a BPC.