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High-Level Architecture Modelling Assisting the Processor Platform Development, Debugging and Simulation

The processor simulator PROSIM introduces an alternative debugging and simulation technique beyond VHDL /Verilog simulation and an on-chip logic analyzer. The simulated architecture model of our embedded bytecode processor SHAP – described in a high-level architecture description language – provides critical insight into the running system for debugging, profiling as well as for feature exploration and evaluation.