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Area‐efficient and high‐speed hardware structure of hybrid cryptosystem (AES‐RC4) for maximizing key lifetime using parallel subpipeline architecture

With the growth of wireless environments, confidential communication has become an important part of daily life. Generally, a wireless medium uses cryptography techniques when transmitting data to provide end‐to‐end protection. Most of the hardware‐efficient cryptosystems do not satisfy the security requirements. In this paper, we concentrate both on security issues and hardware efficiency and present an area‐efficient, high‐throughput hardware structure to implement a hybrid cryptosystem to avoid security problems. The security enhancements are done using a key enhancement process, and it is achieved by using a hybrid encryption cryptosystem. In this paper, we combine block and stream cipher encryption algorithms to frame the hybrid algorithm. We consider advanced encryption standard (AES) as the block cipher and Rivest cipher‐4 (RC4) as the stream cipher. Due to the hybrid systems, performance metrics, such as area, throughput, and power consumptions, are affected. Moreover, advanced arithmetic logic (ie, field arithmetic) combined with the on‐the‐fly key expansion technique is used to minimize area consumption, and parallel subpipeline technique is used to enhance the system throughput. The proposed hybrid architecture (AES‐RC4) is implemented in a field‐programmable gate array with a Xilinx tool.