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CMOS Platform TEG for Development of High Performance Synaptic Devices

In this paper, complementary metal–oxide–semiconductor (CMOS) based test structure platform is proposed for development of high performance synaptic devices. The main idea of this platform is that everyone who has high performance synaptic device solution can form the devices on top of the platform wafers with only three photolithography steps without design burden of CMOS circuits for accurate characterization of huge number of synaptic devices up to 250,000 within 10 minutes. The proposed platform is comprised of 16 × 16, 64 × 64, and 512 × 512 NMOS array chips where each chip has three analog DEMUXs for accurate measurement of the synaptic devices. The CMOS TEGs in the platform was designed using a 0.18 μm CMOS foundry with BEOL up to metal 4 layers. The CMOS test element groups (TEG) can be utilized to evaluate the main characteristics of synaptic devices, such as variability, reliability, statistical analysis and applicability to neuromorphic chips. We demonstrated the performance and the application of the TEG by integrating and characterizing synaptic devices on these TEG.