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An efficient 3D reluctance extractor for on-chip interconnects

Partial reluctance based circuit analysis is efficient in capturing on-chip inductance effect, for its better locality than the partial inductance. But few previous works on reluctance extraction took the high frequency effect into account or were efficient enough for 3D complex structure. In this paper, a new reluctance extraction algorithm is presented considering the high frequency effect. Numerical results demonstrate our algorithm can handle complex 3D interconnect structures with high accuracy, and hundreds of speed-up ratio over FastHenry