{'fraction_non_alphanumeric': 0.017875920084121977, 'fraction_numerical': 0.0010515247108307045, 'mean_word_length': 5.6573426573426575, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
On the efficiency of automatically generated accelerators for reconfigurable active SSDs

Modern high level synthesis (HLS) tools generate Register Transfer Language (RTL) from designs specified in high level languages such as C. By raising the design abstraction level while still promising competitive performance, HLS tools can greatly reduce design effort and time. Contemporary HLS tools can support most manual hardware design optimization techniques such as pipelining and fine-grain data communication. In this paper we study the effectiveness of the Xilinx Vivado HLS tool in generating hardware accelerators for map/reduce kernels, and we compare their performance and logic resource utilization to accelerators generated from hand-coded RTL. Our experimental results show that for most cases, the Vivado tool produces accelerators whose performance is within 9% of handcoded RTL, and whose logic resource utilization is significantly lower.