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Modeling and simulation of single electron transistor with master equation approach

In this paper, we discuss modeling and simulation of single dot Single Electron Transistor (SET) using master equation approximation. For SET modeling and simulation, master equation method treats the electron tunneling and its transition probabilistically. The probability of electron tunneling is used to determine the current density in accordance with selected input parameters. The calculation results show fairly accurate electrical characteristics of SET as compared with experimental data. Staircase pattern from I-V are clearly obtained as the main role of coulomb blockade effect in SET system. We also extend our calculation by introduce some additional parameters such as; the effect of working temperature, gate voltage dependent, and the influence of resistance to the device characteristic. We found that increasing operational temperature will promote higher current density, both in forward and reverse bias region. In the case of using single dot with 30 nm × 80 nm × 125 nm dimension, coulomb blockade effect could be reduced by applying gate voltage higher than 3V and setting drain resistance higher than source's. Our studies show an alternative approach in modeling and simulation of electronic devices and could be potential for development of novel nanoelectronic devices.


Background and Motivation
Single Electron Transistor (SET) is a nanoelectronic device based on quantum effects, such as quantum tunneling and coulomb blockade effects [1]. Nowadays, SET has been researched extensively, since the device consumes less power and has a high performance with large memory [1][2][3][4][5][6]. Moreover, SET may have size below 10 nm. Therefore, it can overcome several problems such as power dissipation and size limitation in Complementary Metal Oxide Semiconductor (CMOS) transistor [1,7].
Single electron transistor has been used for charge sensor applications, infrared radiation detector, ultrasensitive microwave detector, supersensitive electrometer, and single electron spectroscopy because of its capability and sensitivity [8]. However, there are limitations of SET in lithography technique and co-tunneling effect. Moreover, SET has other problems, such as low gain, high output impedance, and background charges at room temperature operation [8,9]. Hence, prior simulation is needed to optimize work function and understanding physics concepts of SET [3,[9][10][11][12].
In this paper, we discuss modeling and simulation of electronic characteristic on single dot SET. The results will be compared with the experimental result [5]. We also extend our calculation in single dot SET by introducing additional parameters such as: the effect of working temperature, gate voltage dependent, and the influence of resistance to the device characteristic. Simulations are performed based on master equation method in Matlab software [4]. Master equation method has been used in modeling and proven to be effective for electrical characteristic of SET [2][3][4]. These simulation results will explain some physical phenomenon behind SET performance and will support further devices development. Figure 1 show a view of SET and its equivalent circuit. One single electron transistor consists of source, drain, gate, and small conductive island (quantum dot). In addition, there are thick insulating layer between gate and dot, and insulating tunnel junction at interaction of source-dot and dot-drain. The size of components affects the value of capacitance and resistance of SET. In single dot SET, total capacitance for dot revealed by sum of source-dot capacitance (C 2 ), gate-dot capacitance (C g ), and dotdrain capacitance (C 1 ). Whereas resistance of SET described by interaction of source-dot (R 2 ) and dotdrain (R 1 ) [11,13,14]. When bias voltage is zero, dot is neutral and Fermi levels of both source and drain in equilibrium state [15]. When bias voltage, such as source-drain voltage (V ds ) and gate voltage (V g ) are applied, charge carriers will tunnel through tunnel junction from source to drain via dot [15,16]. This event creates a charged dot because of its interaction with source (Q 2 ), gate (Q 3 ), and drain (Q 1 ) [11]. Basically, laws of classical electrodynamics prohibit the current flow through a tunnel junction. However, quantum tunneling tells us that there is a non-zero probability for an electron on one side of the barrier tunneling to the other side [17].

Basic Theory
When a carrier tunnels through tunneling junction, probability of others charge to flow will be decreased because of repulsive force between carriers. Thus, carrier will tunnel one by one in SET. This phenomenon called coulomb blockade effect [12,14]. The conditions for coulomb blockade effect to happen, is that tunneling resistance must be higher than quantum resistance (h/e 2 ) and bias voltage must be smaller than the ratio between charge of carrier and capacitance of island (V bias < e/C). In addition, thermal energy of source-island must be lower than charging energy (k B T< e 2 /C). Thus, the carrier will not be able to pass through the QD via thermal excitation [2,3].

Master Equation Method
Master equation is a method for modeling all states of electron tunneling process uniquely and treating their transition probabilistically. This method can describe the time evolution probabilities of the system in occupying discrete state [18]. Hence, master equation can be used to calculate probabilities of electron tunneling which is used to determine current flow in SET. Before calculation, components of SET must be well-defined. Those components include gate capacitance (C g ), capacitances (C 1 and C 2 ) and resistances (R 1 and R 2 ) in tunnel junctions. In addition, we also have to specify several input parameters including Boltzmann constant (k B ) and charge of carrier (e), and some external parameters such as voltage source-drain (V sd ), gate voltage (V G ), temperature (T), charge in quantum dot (N), and background charge (Q 0 ). The iterative algorithm of master equation method is presented in Figure 2. After defining some input parameters, the change of free energy (F) in tunnel junction (F 2 for source-dot tunnel junction and F 1 for dot-drain tunnel junction) can be calculated by Electron tunneling rate in tunnel junction () can be calculated from derivation of Fermi Golden Rule.
Electron tunneling probability of all states in QD can be calculated by steady state Master Equation in (5). The derivative of probability for this state becomes 0. So, electron tunneling probability is For calculating all values of (N), we assume that the value for (N) at the limit (- and ) is 0. Interpretation of the true value of (N) can be obtained from its normalization.
Current flow can be defined from the differences of tunneling rate and probability multiplication from Master Equation Method.

Result and Discussion
From the results in Figure Figure 4 shows the effect of resistance variation to I-V characteristic of SET. The value of drain and source resistance do not affect the threshold voltage. In every variation of drain and source resistances, the value of threshold voltage is always 0.13 V. When the drain resistance is lower than source resistance, higher current will flow and coulomb blockade effect occur. It can be seen from staircase pattern of I-V characteristic in SET. If drain resistance higher than source resistance, staircase effect will decreased and finally disappeared. The effect of gate voltage variation to I-V characteristic of SET can be seen at Figure 5. The value of threshold voltage is 0.13 V in every variation of gate voltage. Hence, the value of gate voltage is not affected by threshold voltage value, but higher gate voltage will make SET works dominantly in forward bias. In addition, increasing gate voltage will promote higher current density. Moreover, coulomb blockade effect will be reduced when gate voltage is increased. In this research, coulomb blockade effect will be completely disappeared when gate voltage is higher than 3 V. This event can be seen from staircase pattern of I-V characteristic in SET.  Figure 6 shows the effect of temperature variation for I-V characteristic of SET. The threshold voltage in every temperature variation is always constant, which is 0.13 V. Moreover, increasing temperature will promote higher current density. There are no significant current differences because numbers of carriers in the dot are exact for certain density of states. So, higher temperature only creates a small thermal vibration of carriers.

Summary
In conclusion, we have demonstrated the electrical characteristic of SET by using Master Equation approach and show a fairly accurate result with experimental data. Evidently, staircase pattern of I-V characteristic are clearly obtained as the main role of coulomb blockade effect in the SET system. Based on various parameter inputs, current density will be higher if the temperature or gate voltage is increased. This is because carriers will vibrate rapidly in these conditions. In our simulation, coulomb blockade effect could be reduced when we apply gate voltage higher than 3V and set a higher resistance for drain than source. So, the staircase pattern, as main characteristic of SET, will be lost.