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Simulating and Designing a PLL Frequency Synthesizer for GSM Communications

Phase locked loops (PLL) are used in almost every communication system. Some of the uses include recovering clock from digital data signals, performing frequency, phase modulation and demodulation, recovering the carrier from satellite transmission signals and as a frequency synthesizer. It is very well known that there are many designs in communication that require frequency synthesizers to generate a range of frequencies; such as cordless telephones, mobile radios and other wireless products. The accuracy of the required frequencies is very important in these designs as the performance is based on this parameter. Using crystal oscillators to generate frequency is not only impractical, but it is impossible to use many crystal oscillators for multiple frequencies. In the last decade, most frequency synthesizers are based on the PLLs, regarding their advantages as minimum complex architecture, low power consumption and integration technology possibilities. In practice, there are three basic types of frequency synthesizer: direct frequency synthesizer, direct digital frequency synthesizer and indirect frequency synthesizer. The indirect frequency synthesizer has advantages over the other two types, including low power consumption, low phase noise, and high stability [1]. Considering the scope of this single circuit, this work is devoted to the design of an indirect frequency synthesizer that can be applied to GSM communications. In the simulation, we include the phase noise in each component in the circuit, and we discuss the reference spurs and their effect on the noise performance of the PLL frequency synthesizer. The success of this design depends crucially on the accuracy of the values calculated for the loop filter. In our case, the loop filter is accurately evaluated by using an efficient estimation technique.