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Statistical leakage estimation for DRAM circuits

Power consumption has become a key constraint in VLSI designs. Leakage current becomes a dominant part of the total power dissipation. In addition, with technology scaling into sub-50nm regime, one of the main design challenges in the presence of process variations is to cope with the uncertainties in timing and power. Since the leakage current is highly dominated by process variations, the statistical leakage estimation is essential for robust circuit design. Process variations can be monitored by analyzing the test element group (TEG). DRAM has power down mode with ICC2P parameter. To obtain ICC2P current, we need a long circuit-level simulation with an accurate transistor modeling. Therefore, to solve this problem, we need a practical framework which is based on switch-level and standby vector dependent statistical leakage analysis. In this paper, we proposed a TEG based analysis methodology to estimate the leakage current at ICC2P mode. Experiments on DRAM benchmark circuits demonstrate that the estimated results with our methodology are very accurate compared to the measurement data from industrial fabrication.