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A hierarchical redundant cube-connected cycle for WSI yield enhancement

To enhance system yield for a large scale cube-connected cycle (CCC), we propose a hierarchical redundant architecture in which a cycle is implemented on two rows at the first level and all cycles at the first level are connected as a block in a two dimensional array at the second level. The hierarchical architecture proposed is investigated in area performance and in yield analysis. We show a semantic structure of the CCC and a previous redundant architecture for CCC. A hierarchical CCC architecture to achieve yield enhancement on a silicon wafer is addressed. Performances of the redundant architecture are discussed with respect to layout area and system yield.