{'fraction_non_alphanumeric': 0.020833333333333332, 'fraction_numerical': 0.010416666666666666, 'mean_word_length': 5.627586206896551, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
IEEE 1588 Transparent Clock architecture for FPGA-based network devices

Apart from traditional test and measurement systems where clock synchronization is required, new emerging application areas like SmartGrids and 4G cellular mobile backhaul networks present strong timing constraints in terms of precise time synchronization. Precision Time Protocol (PTP), as defined in IEEE 1588 standard, offers sub-microsecond synchronization using conventional Ethernet networks. Thus, its acceptance is heavily increasing. However, the protocol performance was reduced in large cascaded networks with varying latencies. This drawback was later softened by the second version of the standard with the introduction of the Transparent Clock (TC) device. In this paper, a general overview of PTPv2 and the utilization of TCs is outlined. The main contribution is a new TC architecture for a FPGA-based network device that benefits from reconfigurable devices flexibility.