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Towards an Improved Model for 65-nm CMOS at Cryogenic Temperatures

Cryogenic CMOS is a crucial subcomponent of quantum-technological applications, particularly as control electronics for quantum computers. Simulation is an important first step in designing any CMOS circuit. However, the standard BSIM4.5 model is only applicable for temperatures between 230 K and 420 K. In this work, N-type MOSFETs with different dimensions in a 65-nm CMOS technology were characterized at room temperature and liquid helium temperature (4.2 K). These measurements were compared with corresponding simulations from the BSIM4.5 model. A model of drain current in the triode region was constructed, where key parameters, such as threshold voltage and effective mobility, were modified. By adjusting these temperature-dependent parameters, the modified model predicted the triode region currents with an error reduced to 7.6%. Thus, the modified model can be utilized to simulate transistor behavior in the triode region at cryogenic temperatures.