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Modeling and analysis of transient latchup in double-well bulk CMOS

Characteristics of transient latchup due to noise excitation through the gate of a parasitic SCR are measured and described by a new simplified model to clarify latchup immunity in a double-well CMOS with a nonepitaxial substrate. The model accounts for the effects of high-level carrier injection and base transit delays of the two parasitic transistors, and it can describe the observed latchup transient faithfully if the model parameters are given according to the predetermined procedure. The noise-pulse-width dependence of the latchup trigger current is obtained as a function of current gain, transit time, and transistor base-emitter shunt resistance to show the last one most sensitive to the trigger current. The optimum parameters with the double well are deduced from study to relate the model to structural parameters.