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An FPGA-based Implementation of Subgraph Isomorphism Algorithm

Many applications can be modeled as subgraph isomorphism problems, which is generally NP-complete and difficult to compute practically. To accelerate the solver, an algorithm that is suited for hardware implementation is proposed and evaluated on FPGA. The prototype accelerator operates at 16.5 MHzon Lucent ORCA 2C15A, which outperforms the software implementation of Ullmann's algorithm on a 400 MHzPentium-II by 20 times in the best case. The performance can be boosted easily by using multiple FPGA chips or multiple boards.