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Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless Receiver

A software-defined radio receiver is designed from a low power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in today use a wideband RF front-end, including the low noise amplifier and a wide tuning-range synthesizer, spanning over 800 MHz-6 GHz is designed. The entire receiver circuits are implemented in 90 nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards