{'fraction_non_alphanumeric': 0.011122345803842264, 'fraction_numerical': 0.0, 'mean_word_length': 5.73469387755102, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Reduction of Redundancy in Directed Random Verification through Checkpointing

The growing complexity of function and gate counts found in modern semiconductor IP designs has made the verification of those designs the dominant cost of their development and implementation. Design teams rarely have the resources to exhaustively verify their designs, leading to a growing number of verification escapes. This thesis will study an optimization for one style of verification, directed random verification, which enables more of a design to be verified using the same amount of simulation resources. The method of optimization seeks to reduce the inherent redundancy found in directed random verification environments by checkpointing user selected, randomly controlled, decision points. Several verification scenarios will be created to explore the optimizations method’s effects on both the efficiency of the verification that can be achieved and the challenges with implementing the method.