{'fraction_non_alphanumeric': 0.026703499079189688, 'fraction_numerical': 0.0, 'mean_word_length': 5.394117647058824, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Finite-Oxide Thickness-Based Analytical Model for Negative Bias Temperature Instability

Negative bias temperature instability (NBTI) in PMOS transistors has become a serious reliability concern in present-day digital circuit design. With continued technology scaling, and reducing oxide thickness, it has become imperative to accurately determine its effects on temporal circuit degradation, and thereby ensure reliable operation for a finite period of time. A reaction-diffusion (R-D)-based framework is developed for determining the number of interface traps as a function of time, for both the dc (static NBTI) and the ac (dynamic NBTI) stress cases. The effects of finite oxide thickness, and the influence of trap generation and annealing in polysilicon, are incorporated. The model provides a good fit with experimental data and also provides a satisfying explanation for most of the physical effects associated with the dynamics of NBTI. A generalized framework for estimating the impact of NBTI-induced temporal degradation in present-day digital circuits, is also discussed.