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Power efficient column operation-based message-passing schedule for regular ldpc decoder

This paper proposes a power efficient column operation-based message passing schedule for an LDPC decoder. Redundant memory accesses and column operations are removed by using the improved column operation-based message passing schedule. Therefore, the number of memory accesses can be significantly reduced, and thus, power consumption can be also reduced. As a result, the experimental results show that the proposed LDPC decoder can save about 27% power consumption and reduce 25% column operations compared with existing designs with the same error correcting performance.