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Finite element modelling and experimental characterisation of paralleled SiC MOSFET failure under avalanche mode conduction

This paper investigates the physics of device failure during avalanche mode conduction for SiC MOSFETs. SiC devices have been shown to have superior electro-thermal ruggedness during unclamped inductive switching (UIS) compared with similarly rated silicon IGBTs [1]. Failure during UIS normally results from parasitic BJT latch-up which is exacerbated at higher temperatures [2, 3]. Measurements show that the total avalanche energy conducted by the device improves when the UIS occurs over longer avalanche duration with a smaller peak avalanche current as opposed to a higher peak avalanche current over a shorter duration. This is due to the fact that cell-to-cell (or die-to-die) variations in electrical parameters are more critical during peak avalanche current conduction. Power MOSFETs are comprised to numerous FET cells internally connected to common source, drain and gate terminals and the density of which is determined by the cell pitch and die area. These FET cells are normally assumed to be uniform in electro-thermal properties, however, there are variations in parameters like thermal resistance, gate resistance, oxide thickness, body doping, etc. Finite element models of 2 FET cells within a MOSFET show how variations in gate resistance and thermal resistance (initial junction temperature) degrade the devices reliability under UIS and that this is more critical for higher avalanche currents. The finite element models are supported by experimental measurements designed to emulate the effect of inter-cell variation.