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A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers

Three-dimensional (3-D) integration technologies have been expected to overcome the limitations of conventional microprocessors, which integrated by two-dimensional (2-D) implementation technologies. This paper focuses on a circuit partitioning strategy for 3-D integrated circuit designs, because it plays important roles to exploit the potential of 3-D integrated circuits. A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers is proposed and evaluated in this paper. The proposed strategy equalizes the area of each layer and avoids the critical path to across different layers as much as possible A double-precision 3-D integrated floating-point multiplier which designed by the proposed circuit partitioning strategy achieves 42% delay reduction compared to the 2-D implementation.