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A 0.35∼6.25 GHz cognitive radio frequency synthesizer architecture

This work presents a frequency synthesizer architecture that can be used in cognitive radio applications. It generates carrier frequencies that are distributed into sixteen continuous sub-bands covering the entire supported frequency range. The proposed architecture covers a frequency range between 350 MHz and 6.25 GHz. The new architecture incorporates a voltage controlled oscillator (VCO) realized in 0.13μm CMOS technology with varactors and a switched inductor in order to achieve a simulated tuning range from 4.75 GHz to 6.25 GHz (27.3%) and from 3.25 GHz to 4.25 GHz (26.7%). The loop bandwidth of the phase locked loop (PLL) is 891 KHz whereas the switching time between bands is 5.75 ns. At 5.5 GHz, the simulated synthesizer phase noise is of -111 dBc/Hz at a 1 MHz offset frequency.