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Processing and Memory Partitioning Enabled by Low Cost Flip-Chip Stacking

This paper presents a partitioning approach for processing and memory units concluding in a low cost flip-chip stacking. Many of nowadays systems comprise at least a processing unit and some memory for storing data. The requirements for rising bandwidth, brings up new types of memory. This is achieved by increasing the clock and/or using broader interfaces. But raising frequency leads to more effort on the communication channel in terms of signal integrity. The packaging approach presented in this paper, results in a very short communication channel between memory and processor and with achieving high-performance while keeping the communication effort low. The requirements for the IO-cells are reduced, because of this short channel, leading to very small interfaces. All together the solution is a low-cost flip-chip stacking in terms of design and packaging costs.