{'fraction_non_alphanumeric': 0.0210016155088853, 'fraction_numerical': 0.008077544426494346, 'mean_word_length': 5.226130653266332, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Multi-GSPS FFTs using FPGAs

This paper describes the implementation of a high throughput FFTs implemented on FPGAs, using a modified version of the Radix 2N architecture. The implementation uses a synthesis method which supports “super-sampling” to provide very high throughput. Special vector structures in the tools and hardware architecture are supported where complex vectors form the input on each clock cycle, and multiple FFT points are computed each clock cycle. Using Intel's floating point Arria 10 FPGAs, multi-GSPS throughput single precision floating point FFTs can be efficiently constructed, and a 10 GSPS, 32K point FFT in excess of 800 GFLOPS example will presented. Floating point eliminates the pruning and bit growth management as well as giving superior SNR. It does change the FFT implementation strategy, as adders are now as expensive as multipliers. A hybrid architecture incorporating both parallel and multiple serial stages is detailed. Special vector structures in the IP and tools are supported to maximize performance. For both fixed and floating point implementations, comparative results for logic, registers, DSP, memory resources and Fmax are shown. FFT throughput and GFLOPS metrics are also provided.