{'fraction_non_alphanumeric': 0.014097744360902255, 'fraction_numerical': 0.0018796992481203006, 'mean_word_length': 5.614906832298137, 'pattern_counts': {'":': 0, '<': 1, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Simulation Study of Non Ionic Implantation Process: Thinner Electrical Interfacial Semiductor Junction Formation Using Ionic Diffusion Process

Further miniaturization of large scaled integrated circuit is hinder by ability to overcome some difficulties with narrower junction formation. A Low energy ion implantation is the most commonly considered the technique of this time but this techniques full with unrealistic limitation where crystal damage is unavoidable and this limitation further aggravated by lacking using for different materials with different grain sizes. To overcome this problem, a simulation study of shallow -ve junction formation was conducted for phosphorous diffusion on a silicon substrate. An ultra high shallow junction formation of <; 40 nm depth was obtained. The study highlight the improvement made over our previous work conducted for the same material. This economical spin-on dopants (SOD) technique is proven as one of promising solution for future generation's device miniaturization with little or no device structural damage.