{'fraction_non_alphanumeric': 0.029, 'fraction_numerical': 0.036, 'mean_word_length': 4.133333333333334, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Viterbi Equalizer Chip for 40 Gb/s optical communication links

A Viterbi Equalizer Chip (VEC) which can be applied in 40 Gb/s optical communication systems is presented. The circuit is designed and fabricated in a standard 90 nm CMOS technology with a seven metal layer stack. The internal Viterbi processing is 32 times parallelized using a sliding window decoding architecture at a clock frequency of 1.34 GHz. The VEC processes incoming samples with a resolution of 3 bit. The resolution of the internal branch metrics is 6 bit. The power dissipation at the targeted bitrate of 43 Gb/s is 2.6 W at a supply voltage of 1 V leading to 16.5 Gb/(W·s) which is a 50 times improvement compared to [1]. The chip size is 4.08 mm × 1.40 mm containing almost 500k transistors. The presented circuit is the world first Viterbi equalizer for such a high data rate in any technology. Due to test limitations the measured data rate is 32 Gb/s which is more than three times as fast as previous published [2].