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Leakage Current Optimization in Sleepy SRAM at 45nm Technology

Every new generation of process technology at Intel is developed and certified using an SRAM-based “X-chip.”X6 is the technology lead vehicle used for the 45nm technology serving as a platform for the co-optimization of circuit design and process technology for SRAMs as well as critical design collaterals for products. As the workhorse of the embedded memory, SRAMs play an essential role in all Intel products in achieving power performance goals. SRAMs are also ideally suited for process-defect sensitivity and detection. The SRAMs on X6 had featured several different SRAM designs and register files that were individually optimized to take advantage of the Hi-K metal gate process for various product applications. Intel’s revolutionary 45nm technology was instrumental for aggressive SRAM scaling. The tile able SRAM array in X6 was architected to directly support product applications. The X6 also served as the vehicle for several critical memory circuit technology developments, including second-generation dynamic sleep control and dynamic Forward Body Bias (FBB). To support process and design learning, X6 includes an infrastructure of advanced test features: for example, an Error Correction Code (ECC) emulator is designed to quantify the benefit of error corrections and a Programmable Built-in Self Test (PBIST) for high-speed testing with raster capability. Fine-granularity InDie-Variation (IDV) oscillators track process variation. Critical circuits such as electrically programmable Fuse, Phase Lock Loop (PLL), Digital Thermal Sensor (DTS), and advanced I/Os allowed technologists and designers to work closely to optimize the process and circuits earlier. The X6 test chip successfully met the goals of process and critical collateral certification to support both process and product development needs and played an essential role in Intel’s rapid product ramp at the 45nm technology node.