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Taming the Stability-Constrained Performance Optimization Challenge of Distributed On-Chip Voltage Regulation

Distributed on-chip voltage regulation is promising for addressing many IC power delivery challenges. However, complex interactions between active regulators and the surrounding parasitic passive RLC network cause stability concern. The recently developed hybrid stability technique provides a unique opportunity for coping with stability of distributed on-chip regulation and enabling efficient localized system design. However, the inherent conservativeness of the hybrid stability theorem (HST) leads to large pessimism in stability evaluation and hence causes overdesign. In this paper, the above challenge is addressed by extending the HST with an optimal frequency-dependent system partitioning technique which can significantly reduce the amount of pessimism in stability analysis. To put the proposed approach on a firm theoretical footing, we prove that the partitioning technique removes the conservativeness without altering the physical system and key theoretical properties of the partitioned blocks are maintained under certain constraints. Upon this, an efficient stability-ensuring power delivery design methodology using an automated design flow is developed to significantly improve power delivery performance. Within a large design space, the proposed approach ensures stability and improves system performance by up to 53%, measured by a figure of merit (FOM), when compared to the classical phase margin design approach, which provides no guarantee of stability. Furthermore, on average our approach boosts the FOM by 113% while consuming 11% less power compared to a reference hybrid stability approach.