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A BDD-based approach to design power-aware on-line detectors for digital circuits

The work in this paper is mainly concerned with the development of an algorithm for designing a power-aware on-line detector (OLD), which is used in digital circuits to check faults concurrently. We have used Binary Decision Diagram (BDD) in our methodology on top of the existing work to reduce the dynamic power of an OLD significantly. Experiments on ISCAS89 benchmark circuits have shown, on an average, 41% reduction in dynamic power compared to the existing technique. This reduction can further be made to 57% with marginal impact on area overhead.