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Improving read performance via selective Vpass reduction on high density 3D NAND flash memory

3D NAND flash memory has been well developed due to its high density and decreasing cost compared with planar flash. However, one issue for 3D NAND flash, which has not been well solved, is its worse read disturb. The worse read disturb of 3D NAND flash stems from its much more word lines in a block. In this case, it receives much more read operations, leading to increased read disturb. Previous work proposed to relax the read disturb on planar flash through reducing the pass-through voltage, Vpass, on the unread word lines. However, this is not viable for 3D NAND flash with the increased number of word lines in a block. In this work, a new read disturb reduction scheme is proposed for 3D NAND flash. First, a read error model is presented, which demonstrates that selective Vpass reduction is a viable approach. Then, a read-hotness aware Vpass reduction scheme is proposed to improve performance without violating the reliability requirement. Simulation shows that the proposed scheme achieves encouraging performance improvement.