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Efficient Analog Defect Simulation

Simulation of defects in industrial analog and mixed-signal (A/MS) circuits has long been regarded as impractical: how to simulate the tens of thousands of potential defects for each test and significant process corner of a PLL or SerDes, for example, when simulating each defect could require hours or days of simulation? Would the results for a subset be useful? This paper shows an efficient flow, consistent with the proposed IEEE P2427 Standard for Analog Defect Modeling and Coverage. The flow describes development of realistic models for hard/catastrophic and soft/parametric defects, introduces analog defect collapsing, discusses coverage results for an ITC'17 A/MS benchmark bandgap voltage reference plus LDO voltage regulator, and a programmable PLL, and shows why the results are applicable to large circuits. The results also show that some strategies are more useful than others.