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Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator

This brief presents a theoretical analysis of the stochastic reference clock generator (SRCG), which creates a clock like periodic signal from a random nonreturn-to-zero data sequence. The output of the SRCG can be utilized as a reference clock for frequency acquisition in dual-loop clock-and-data recovery circuits. A frequency-locked loop (FLL) subsequent to the SRCG guides the voltage-controlled oscillator frequency into the pull-in range of the phase-locked loop while suppressing the high-frequency phase noise of the SRCG. The phase noise and frequency offset of the SRCG-FLL pair are analyzed. The validity of the theoretical analysis is supported by results taken from a test chip.