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Experimental Digital BPSK Modulator Design with VHDL Code for BIODEVICES Applications

In this paper, we propose a new simple design for a BPSK modulator applied to implant telemetry applications as demonstrated. We used hardware description language VHDL (IEEE standard) to generate a BPSK digital signal. The carrier and data are interfaced to the CPLD and FPGAs board for testing, we used the local clock oscillator, which is operating at 25.175 MHz reduced into 12.5 MHz for the carrier and 2Mbps for data source. The modelled modulator has been designed simulated and performance was evaluated by measurements, considering low power consumption and size for medical purpose. Moreover, the advantages of this modulator are it can be reconfigured and upgraded to enhance the bit rate.