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Effect of Sidewall Spacers on the Performance of GaAs Based DG-JLMOSFET

The effects of both the high-k and low-k sidewall spacers on the performance of a GaAs based Double Gate Junctionless Metal Oxide Semiconductor Field Effect Transistor (DG-JLMOSFET) have been investigated. Here, the results have been obtained from SILVACO ATLAS TCAD simulation tool. The proposed DG-JLMOSFET structure shows superior performance when TiO2 is used as the sidewall spacer. Additionally, we observed the improvements in the short channel effects (SCEs), subthreshold swing (SS) and drain induced barrier lowering (DIBL) of 79 mV/decade and 108 mV/decade, respectively. The GaAs based DG-JLMOSFET with sidewall spacer gives high ON current (ION) and low OFF current (IOFF) with high ON-state to OFF -state current ((ION/IOFF) ratio of 9.381×107 compared to the device structure without sidewall spacers. The results have been finally compared with the Si counterpart. The outcomes could be a good insight for fabricating the GaAs based future practical DG-JLMOSFETs for nano-devices.