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A multi-slope CMOS analog to digital converter

This paper describes a new multi-slope analog to digital converter. The algorithm used for the converter is based on relative comparisons, which makes the converter self-calibrated. The calibration is performed without any additional analog or logic circuitry, and the conversion does not need extra clock cycles. The analog circuit is simple and limited to three identical current controlled oscillators. A prototype of a 6-bit multi-slope ADC has been designed. ELDO electrical simulations are presented and commented on.