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Design of Scalable Hardware Architecture for Dual-field Montgomery Modular Inverse Computation

Modular inverse computation is needed in many public key cryptographic applications. In this work, we present two new Montgomery inverse hardware algorithms for GF(p) and GF(2n) field, which are modified from Kaliski algorithm to benefit from multi-bit shifting hardware features. Based on these improved algorithms, a scalable and unified hardware architecture is proposed. The architecture allows the hardware to compute the inverse of long precision numbers in a repetitive way. In addition, the implementation of this design using Xilinx FPGA was compared with other designs. The unified hardware showed better overall performance in area/time than the others, thus it is a very efficient solution whenever arithmetic in the two finite fields is needed.