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Power Estimation of Embedded SRAMs using BIST Algorithms

As more and more memories are used on a chip for graphic rendering and cloud computing purpose, power estimation of memories in a chip on an automatic test equipment (ATE) without the aid of functional patterns is a rarely new practice. Power dissipated by embedded SRAMs under normal operation is critical to power estimation. This paper describes a method that utilizes memory BIST architecture and algorithms to mimic the normal functional operation of embedded SRAMs with various lengths, in order to estimate power consumption as early as wafer level in an ATE environment.