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A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications

This paper presents a 10-bit current-steering digital-to-analog converter (CS-DAC) in a 45-nm CMOS process with a supply voltage of 1 V. This architecture is based on the segmentation of binary and unary DAC architectures for least significant bits (LSBs) and most significant bits (MSBs) respectively. Thus, the circuit consists of an architecture of 9 bit CS-DAC comprising a 3-bit binary weighted and 6-bit unary weighted DAC. Keeping the power constraints approximately same as 9-bit architecture, a 10-bit architecture is designed in this work using a switched capacitor network cascaded with the 9-bit DAC. The proposed architecture is able to reduce the power dissipation by 50% (approximately). A capacitor, CBucket is used to store the output from the 9-bit DAC architecture, which is used to generate the final output voltage corresponding to the 10-bit resolution. The proposed design operates with a sampling rate of 250 MHz. The architecture consumes a power of 4 mW with an effective number of bits (ENOB) of 9.44 bits. Also, the design achieves spurious free dynamic range of 70 dB.