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Building-in reliability and challenges in analysis in sub−100nm devices - An overview

The progression in device technology from deep sub-micron to nanometer regime has a tough and challenging path in terms of physical device analysis and maintaining the device reliability. Even though the process complexity increases alongwith the new materials and new issues, the electrical defect density is found to reduce as every new node matures. The comment “There is plenty of room at the bottom” by Richard Feynman [1] 50 years ago at the very early stages of semiconductor technology seems to be correct even now from an overall perspective. However, in order to accommodate the device performance needs, the statement “There is plenty of difficulty near the bottom” [2] by the device developers and manufacturers seems to be more apt. As followed in the history, the study of the physics of device failures through device analysis is the only method to tackle these difficulties at the bottom.