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A High-Level Compact Pattern-Dependent Delay Model for High-Speed Point-to-point Interconnects

This work introduces an extended linear pattern-dependent model for high-level signal delay estimation in high-speed very deep sub-micron point-to-point interconnects. The proposed model accurately predicts the delay in both inductively and capacitively coupled lines for the complete set of the switching patterns and not only for capacitively coupled lines or worst-case delay as in previous works. We also consider process variations in the formulation of the model and propose a moment-based approach for the inclusion of variations. The accuracy of the model has been assessed by means of extensive experiments. Moreover, we show how the model can be applied at high levels of abstraction in order to explore coding-based alternatives to improve throughput