{'fraction_non_alphanumeric': 0.021146616541353382, 'fraction_numerical': 0.0, 'mean_word_length': 5.780254777070064, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Benchmarking image processing for space: Introducing the SPACER architecture laboratory

In order to better make investment decisions for future space processing, we are equipping an architectures laboratory to investigate the power and computing performance of candidate computing architectures for future space applications. The picture for future space processing is increasingly complicated by ever increasing data rates/sizes and limited communications bandwidth, both of which will require more data processing, in the form of either data reduction or compression, to be performed on orbit rather than on the ground. Candidate architectures for the laboratory are being drawn from a range of COTS processing architectures including low power multicore processors, FPGAs, and GPUs. As the drivers for these investments are likely to be data-intensive image processing applications, we have selected two representative applications, Synthetic Aperture Radar (SAR) and Hyper-Temporal Imaging (HTI), and tested them on a variety of low-power multicore processors, and for comparison, on modern conventional processors. Both applications were parallelized using OpenMP and/or pthreads. The processors employed include from four to eight cores. State-of-the-art numerical libraries were used to extract the most performance possible. The multi-core processors selected included examples of both homogeneous and heterogeneous computing architectures. Effects of varying the parameters such as the amount of memory made available to the processors, which affects how data decomposition is accomplished, are also studied. In general, homogeneous computing architectures performed better than heterogeneous ones. In some cases, better performance could be achieved with a single processor core with large memory than with multiple processors. These results are a function of the employed algorithm's ability to efficiently utilize architecture features, and cannot be attributed to all application/architecture pairings, thus highlighting the need for a concerted effort to explore processing requirements for future space missions.