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Integrated Register Allocation and Software Pipelining

Software pipelining is a powerful and efficient scheduling technique for exploiting instruction level parallelism in loops, it results in high performance but it increases the register requirements. Two methods are available to reduce the register requirements: increase the schedule length or insert spill code. Traditionally instruction scheduling and register allocation are applied in separate phases. However decisions made by one phase may negatively impact the other. In this paper we describe a method that integrates register allocation and software pipelining in a single phase. Also the insertion of spill code is discussed. The results of the experiments show that this integration may result in large performance improve-