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A new k-constraint strategy combined with post-Viterbi processing for perpendicular recording

Run-length limited (RLL) codes used in today's recording products limit runs of like non-return-to-zero (NRZ) bits to (k+1) intervals at a time. While this "k-constraint" facilitates timing recovery and is essential, at issue is the rate penalty associated with its application, which is costly in terms of loss of effective signal-to-noise ratio (SNR) and user density. To avoid this rate penalty, Vasic has proposed a bit-flipping scheme, wherein bit errors are deliberately inserted whenever data contains a long string of like symbols, in lieu of conventional RLL coding. Attempts are then made to correct the errors due to bit flipping relying on the outer error correction code (ECC). Although this method causes no rate penalty, the error correction capability of the ECC is compromised, due to additional burden of handling the deliberate bit errors. In this work, an effective way to remedy this problem is proposed. Namely, the use of inner error detection code that is already available in any post-Viterbi error correction systems. The result is that the rate penalty of the k-constraint is completely eliminated while there is no visible loss of ECC capability at a given sector error rate (SER) target. Also, since the existing inner error detection code is utilized, there is very little extra cost required to implement this scheme. To demonstrate the viability of the proposed approach, the idea is applied to perpendicular recording using a cyclic redundancy check (CRC) code specifically designed for perpendicular recording.