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Gain and noise optimization of a passive sliding IF architecture

This paper presents gain and noise optimization of a passive Sliding IF downconverter as a promising choice for Zero-IF and Low-IF receivers. With detailed mathematical analysis of the architecture we propose a new design that provides 7.6 dB improvement of relative conversion gain with profound noise figure and IIP3 performance. The results of the mathematical derivation are supported by modeling, circuit simulation and measurement of a prototype chip fabricated on a standard 130nm CMOS technology. The chip operates under supply voltage of 1.2V and occupies 750μm × 200μm active area.