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Multiple Automatic Design Vector Generation for Efficient Systolic Architecture using NIC

In nano-era of computing architecture the main emphasis of design has shifted to reducing the overall interconnection complexity and keeping the overall architecture highly regular, parallel and pipelined. These properties can be effectively exploited in the innovative systolic architecture. This paper presents an optimization model from regular iterative algorithm (RIA) description of dependence graph for finding the optimal values for the three fundamental design vectors namely: scheduling, projection and processor vector, so that efficient architecture could be feasible along with that maximum hardware utilizing efficiency. Approach is also having the focus to minimize the total number of delay involved with systolic architecture design. Nature inspired computation (NIC) like Evolutionary programming (EP) with hybrid mutation strategy and Particle swarm optimization (PSO) have applied in discrete form to find the optimal solution. Experiment and performance analysis have given to design systolic architecture vectors for matrix-matrix multiplication.