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Two dimensional analytical model for the threshold voltage of a Gate All Around Nanowire tunneling FET with localized charges

In this paper, we have studied the effect of localized charges on the threshold voltage of a Gate All Around Nanowire TFET and a two dimensional (2D) analytical model is developed for studying these effects. These localized charges are generated in the oxide due to hot carrier effects (HCEs) arising due to high electric fields in the tunneling region of a TFET. The models are derived by dividing the channel into damaged and undamaged regions and then solving for the surface potential using the 2D Poisson's equation in these regions. The threshold voltage is then extracted by using the constant current method. The models proposed are verified with 2D numerical simulations. The model can be used for varying device dimensions and charge densities and can also be utilized to design TFET based charge trapped memory devices.