{'fraction_non_alphanumeric': 0.03273809523809524, 'fraction_numerical': 0.001488095238095238, 'mean_word_length': 5.118181818181818, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Multicore-aware hybrid code positioning to reduce worst-case execution time

Unlike general-purpose programs, it is important to reduce the worst-case performance rather than the average-case performance for real-time systems. In this paper, based on a dual-core processor with a shared L2 cache, we propose a code positioning scheme that can reduce the worst-case execution time (WCET) for real-time threads by minimizing both the intra-thread and inter-thread instruction cache misses. Our experiments indicate that the proposed hybrid code positioning approach can effectively reduce the worst-case performance for real-time threads running on this dual-core processor.