{'fraction_non_alphanumeric': 0.02797588482531713, 'fraction_numerical': 0.009318955516251117, 'mean_word_length': 5.041073069852941, 'pattern_counts': {'":': 0, '<': 4, '<?xml version=': 0, '>': 6, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 2, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Resource-Efficient Neural Networks for Embedded Systems

While machine learning is traditionally a resource intensive task, embedded systems, autonomous navigation, and the vision of the Internet of Things fuel the interest in resource-efficient approaches. These approaches aim for a carefully chosen trade-off between performance and resource consumption in terms of computation and energy. The development of such approaches is among the major challenges in current machine learning research and key to ensure a smooth transition of machine learning technology from a scientific environment with virtually unlimited computing resources into everyday's applications. In this article, we provide an overview of the current state of the art of machine learning techniques facilitating these real-world requirements. In particular, we focus on deep neural networks (DNNs), the predominant machine learning models of the past decade. We give a comprehensive overview of the vast literature that can be mainly split into three non-mutually exclusive categories: (i) quantized neural networks, (ii) network pruning, and (iii) structural efficiency. These techniques can be applied during training or as post-processing, and they are widely used to reduce the computational demands in terms of memory footprint, inference speed, and energy efficiency. We also briefly discuss different concepts of embedded hardware for DNNs and their compatibility with machine learning techniques as well as potential for energy and latency reduction. We substantiate our discussion with experiments on well-known benchmark datasets using compression techniques (quantization, pruning) for a set of resource-constrained embedded systems, such as CPUs, GPUs and FPGAs. The obtained results highlight the difficulty of finding good trade-offs between resource efficiency and predictive performance.


Introduction
Machine learning is a key technology in the 21 st century and the main contributing factor for many recent performance boosts in computer vision, natural language processing, speech recognition and signal processing. Today, the main application domain and comfort zone of machine learning applications is the "virtual world", as found in recommender systems, stock market prediction, and social media services. However, we are currently witnessing a transition of machine learning moving into "the wild", where most prominent examples are autonomous navigation for personal transport and delivery services, and the Internet of Things (IoT). Evidently, this trend opens several real-world challenges for machine learning engineers. Current machine learning approaches prove particularly effective when big amounts of data and ample computing resources are available. However, in real-world applications the computing infrastructure during the operation phase is typically limited, which effectively rules out most of the current resource-hungry machine learning approaches. There are several key challenges-illustrated in Figure 1-which have to be jointly considered to facilitate machine learning in real-world applications: Representational efficiency The model complexity, i.e., the number of model parameters, should match the (usually limited) resources in deployed systems, in particular regarding memory footprint.
Computational efficiency The computational cost of performing inference should match the (usually limited) resources in deployed systems, and exploit the available hardware optimally in terms of time and energy. For instance, power constraints are key for autonomous and embedded systems, as the device lifetime for a given battery charge needs to be maximized, or constraints set by energy harvesters need to be met.
Prediction quality The focus of classical machine learning is mostly on optimizing the prediction quality of the models. For embedded devices, model complexity versus prediction quality trade-offs must be considered to achieve good prediction performance while simultaneously reducing computational complexity and memory requirements.
In this article, we review the state of the art in machine learning with regard to these realworld requirements. We focus on deep neural networks (DNNs), the currently predominant machine learning models. We formally define DNNs in Section 2 and give a brief introduction to the most prominent building blocks, such as dropout and batch normalization. While being the driving factor behind many recent success stories, DNNs are notoriously data and resource hungry, a property which has recently renewed significant research interest in resource-efficient approaches. This paper is dedicated to giving an extensive overview of the current directions of research of these approaches, all of which are concerned with reducing the model size and/or improving inference efficiency while at the same time maintaining accuracy levels close to state-of-the-art models. We have identified three major directions of research concerned with enhancing resource efficiency in DNNs that we present in Section 3. In particular, these directions are: Quantized Neural Networks Typically, the weights of a DNN are stored as 32-bit floating-point values and during inference millions of floating-point operations are carried out. Quantization approaches reduce the number of bits used to store the weights and the activations of DNNs. While quantization approaches obviously reduce the memory footprint of a DNN, the selected weight representation potentially also facilitates faster inference using cheaper arithmetic operations. Even reducing precision down to binary or ternary values works reasonably well and essentially reduces DNNs to hardwarefriendly logical circuits.
Network Pruning Starting from a fixed, potentially large DNN architecture, pruning approaches remove parts of the architecture during training or after training as a post-processing step. The parts being removed range from the very local scale of individual weights-which is called unstructured pruning-to a more global scale of neurons, channels, or even entire layers-which is called structured pruning. On the one hand, unstructured pruning is typically less sensitive to accuracy degradation, but special sparse matrix operations are required to obtain a computational benefit. On the other hand, structured pruning is more delicate with respect to accuracy but the resulting data structures remain dense such that common highly optimized dense matrix operations available on most off-the-shelf hardware can be used.
Structural Efficiency This category comprises a diverse set of approaches that achieve resource efficiency at the structural level of DNNs. Knowledge distillation is an approach where a small student DNN is trained to mimic the behavior of a larger teacher DNN, which has been shown to yield improved results compared to training the small DNN directly. The idea of weight sharing is to use a small set of weights that is shared among several connections of a DNN to reduce the memory footprint. Several works have investigated special matrix structures that require fewer parameters and allow for faster matrix multiplications-the main workload in fully connected layers. Furthermore, there exist several manually designed architectures that introduced lightweight building blocks or modified existing building blocks to enhance resource efficiency. Most recently, neural architecture search methods have emerged that discover efficient DNN architectures automatically.
Evidently, many of the presented techniques are not mutually exclusive, and they can potentially be combined to further enhance resource efficiency. For instance, one can both sparsify a model and reduce arithmetic precision. We complement our literature review with a brief overview of embedded hardware for DNNs in Section 4. These hardware platforms can be categorized into CPUs, GPUs, FPGAs and domain-specific accelerators, where each architecture exhibits different properties for deploying models. We discuss potentials and limitations of such embedded hardware with considerations on vectorization and parallelization, frequency and energy efficiency, as well as their applicability for resource-efficient models.
In Section 5 we substantiate our discussion with experimental results. We provide a comparison of various quantization approaches for DNNs using the CIFAR-100 dataset in Section 5.1.1, followed by an evaluation of prediction quality for different types of pruned structures on the CIFAR-10 dataset in Section 5.1.2. We evaluate the inference throughput of the compressed models on an ARM CPU (Section 5.2.1), Xilinx FPGA (Section 5.2.2) and an embedded NVIDIA GPU (Section 5.2.3). We conclude the experiments with an overall comparison in Section 5.2.4, where the embedded systems (in combination with compression techniques) are studied with respect to throughput and prediction quality.

Background
Before we present a comprehensive overview of the many different techniques for reducing the complexity of DNNs in Section 3, this section formally introduces DNNs and some fundamentals required in the remainder of the paper.

Feed-forward Deep Neural Networks
DNNs are typically organized in layers of alternating linear transformations and non-linear activation functions. A vanilla DNN with L layers is a function mapping an input x 0 to an output y = x L by applying the iterative computation where (1) computes a linear transformation with weight tensor W l and bias vector b l , and (2) computes a non-linear activation function φ that is typically applied element-wise. Common choices for φ are the ReLU function φ(a) = max(a, 0), sigmoid functions, such as tanh(a) = (e a − e −a )/(e a + e −a ) and the logistic function 1/(1 + e −a ), and, in the context of resource-efficient models, the sign function sign(a) = I(a ≥ 0) − I(a < 0), where I is the indicator function.
In this paper, we focus on hardware-efficient machine learning in the context of classification, i.e., the task of assigning the input x 0 to a classĉ ∈ {1, . . . , C}. Other predictive tasks, such as regression and multi-label prediction, can be tackled in a similar manner. For classification tasks, the output activation function φ for computing x L ∈ R C is typically the softmax function φ(a) i = e a i / j e a j . An input x 0 is assigned to classĉ = arg max c x L c . The two most common types of layers are (i) fully connected layers 1 and (ii) convolutional layers. For fully connected layers, the input x ∈ R n is a vector whose individual dimensions-also called neurons 2 -do not exhibit any a-priori known structure. The linear transformation of a fully connected layer is implemented as a matrix-vector multiplication Wx where W ∈ R m×n .
Convolutions are used if the data exhibits spatial or temporal dimensions such as images, in which case the DNN is called a convolutional neural network (CNN). Two-dimensional images can be represented as three-dimensional tensors x l ∈ R C×W ×H , where C refers to the number of channels (or, equivalently, feature maps), and W and H refer to the width and the height of the image, respectively. A K w × K h convolution using a rank-4 filter weight tensor W ∈ R Kw×K h ×C×D mapping x l ∈ R C×W ×H to a l+1 ∈ R D×W ×H is computed as where i is the auxiliary indexing function Each spatial location of the output feature map a l+1 is computed from a K w × K h region of the input image x l . By using the same filter to compute the values at different spatial locations, a translation invariant detection of features is obtained. The spatial size of features detected within an image is bounded by the receptive field, i.e., the section of the input image that influences the value of a particular spatial location in some hidden layer. The receptive field is increased by stacking multiple convolutional layers, e.g., performing two consecutive 3 × 3 convolutions results in each output spatial location being influenced by a larger 5 × 5 region of the input feature maps. Another form of translational invariance is achieved by pooling operations that merge spatially neighboring values within a feature map to reduce the feature map's size. Common choices are max-pooling and average-pooling which combine the results of neighboring values 3 by computing their maximum or average, respectively. Furthermore, pooling operations also increase the receptive field.

Training of Deep Neural Networks
The task of training is concerned with adjusting the weights W such that the DNN reliably predicts correct classes for unseen inputs x 0 . This is accomplished by minimizing a loss 1. Many popular deep learning frameworks refer to fully connected layers as dense layers. 2. For 1 < l < L, we speak of hidden layers and hidden neurons. 3. Typically, a 2 × 2 region to halve the feature map size is used. function L using gradient-based optimization (Nocedal and Wright, 2006). Given some labeled training data D = {(x 0 1 , t 1 ), . . . , (x 0 N , t N )} containing N input-target pairs, a typical loss function has the form where l(y n , t n ) is the data term that penalizes the DNN parameters W if the output y n does not match the target value t n , r(W) is a regularizer that prevents the DNN from overfitting, and λ > 0 is a trade-off hyperparameter. Typical choices for the data term l(y n , t n ) are the cross-entropy loss or the mean squared error loss, whereas typical choices for the regularizer r(W) are the 1 -norm or the 2 -norm of the weights. The loss is minimized using gradient descent by iteratively computing where η is a learning rate hyperparameter. In practice, more involved stochastic gradient descent (SGD) schemes, such as ADAM (Kingma and Ba, 2015), are used that randomly select smaller subsets of the data-called mini-batches-to approximate the gradient. Modern deep learning frameworks play an important role in the growing popularity of DNNs as they make gradient-based optimization particularly convenient: The user specifies the loss L as a computation graph and the gradient ∇ W L is calculated automatically by the framework using the backpropagation algorithm (Rumelhart et al., 1986).

Batch Normalization
The literature has established a consensus that using more layers improves the classification performance of DNNs. However, increasing the number of layers L also increases the difficulty of training a DNN using gradient-based methods as described in Section 2.2. Most modern DNN architecture employ batch normalization (Ioffe and Szegedy, 2015) after the linear transformation of some or all layers by computing where β d and γ d are trainable parameters, and N B is the mini-batch size of SGD. The idea is to normalize the activation statistics over the data samples in each layer to zero mean and unit variance. This results in similar activation statistics throughout the network which facilitates gradient flow during backpropagation. The linear transformation of the normalized activations with the parameters β and γ is mainly used to recover the DNNs ability to approximate any desired function-a feature that would be lost if only the normalization step is performed. Most recent DNN architectures have been shown to benefit from batch normalization, and, as reviewed in Section 3.2.2, batch normalization can be targeted to achieve resource efficiency in DNNs.

Dropout
Dropout as introduced by Srivastava et al. (2014) is a way to prevent neural networks from overfitting by injecting multiplicative noise to the inputs of a layer, i.e., x l d ← x l d · ε. A common choice for the injected noise is ε ∼ Bernoulli(p) where the values x l d are randomly set to zero with probability 1 − p. Another common choice is Gaussian dropout where we have ε ∼ N (1, α). 4 Intuitively, the idea is that hidden neurons cannot rely on the presence of features computed by other neurons. Consequently, individual neurons are expected to compute in a sense "meaningful" features on their own. This avoids that multiple neurons jointly compute features in an entangled way. Dropout has been cast into a Bayesian framework which was subsequently exploited to perform network pruning as detailed in Section 3.2.3.

Modern Architectures
As mentioned in the beginning of this section, most architectures follow the simple scheme of repeating several layers of linear transformation followed by a non-linear function φ. Although most successful architectures follow this scheme, recent architectures have introduced additional components and subtle extensions that have led to new design principles. In the following, we give a brief overview of the most prominent architectures that have emerged over the past years in chronological order.

AlexNet
The AlexNet architecture (Krizhevsky et al., 2012) was the first work to show that DNNs are capable of improving performance over conventional hand crafted computer vision techniques by achieving 16.4% Top-5 error on the ILSVRC12 challenge-an improvement of approximately 10% absolute error compared to the second best approach in the challenge which relied on well-established computer vision techniques. This most influential work essentially started the advent of DNNs, which can be seen from the fact that DNNs have spread over virtually any scientific field and achieved improved performances over wellestablished methods in the respective fields.
The architecture consists of eight layers-five convolutional layers followed by three fully connected layers. AlexNet was designed to optimally utilize the available hardware at that time rather than following some clear design principle. This involves the choice of heterogeneous window sizes K w ×K h and seemingly arbitrary numbers of channels per layer C. Furthermore, convolutions are performed in two parallel paths to facilitate the training on two GPUs.

VGGNet
The VGGNet architecture (Simonyan and Zisserman, 2015) won the second place at the ILSVRC14 challenge with 7.3% Top-5 error. Compared to AlexNet, its structure is more uniform and with up to 19 layers much deeper. The design of VGGNet is guided by two main principles. (i) VGGNet uses mostly 3 × 3 convolutions and it increases the receptive field by stacking several of them. (ii) After downscaling the spatial dimension with 2 × 2 4. The parameters p and α are hyperparameters. max-pooling, the number of channels should be doubled to avoid information loss. From a hardware perspective, VGGNet is often preferred over other architectures due to its uniform architecture.

InceptionNet
InceptionNet (or, equivalently, GoogLeNet)  won the ILSVRC14 challenge with 6.7% Top-5 error with an even deeper architecture consisting of 22 layers. The main feature of this architecture is the inception module which combines the outputs of 1 × 1, 3 × 3, and 5 × 5 convolutions by stacking them. To reduce the computational burden, InceptionNet performs 1 × 1 convolutions as proposed in (Lin et al., 2014a) to reduce the number of channels immediately before the larger 3 × 3 and 5 × 5 convolutions.

ResNet
Motivated by the observation that adding more layers to very deep conventional CNN architectures does not necessarily reduce the training error, residual networks (ResNets) introduced by He et al. (2016) follow a rather different principle. The key idea is that every layer computes a residual that is added to the layer's input. This is often graphically depicted as a residual path with an attached skip connection.
The authors hypothesize that identity mappings play an important role. They argue that it is easier to model identity mappings in ResNets by simply setting all the weights of the residual path to zero instead of simulating them by adapting the weights of several consecutive layers in an intertwined way. In any case, the skip connections reduce the vanishing gradient problem during training and enable extremely deep architectures of up to 152 layers on ImageNet and even up to 1,000 layers on CIFAR-10. ResNet won the ILSVRC15 challenge with 3.6% Top-5 error.

DenseNet
Inspired by ResNets whose skip connections have shown to reduce the vanishing gradient problem, densely connected CNNs (DenseNets) introduced by  drive this idea even further by connecting each layer to all previous layers. DenseNets are conceptually very similar to ResNets-instead of adding the output of a layer to its input, DenseNets stack the output and the input of each layer. Since this stacking necessarily increases the number of feature maps with each layer, the number of new feature maps computed by each layer is typically small. Furthermore, it is proposed to use compression layers after downscaling the spatial dimension with pooling, i.e., a 1 × 1 convolution is used to reduce the number of feature maps.
Compared to ResNets, DenseNets achieve similar performance, allow for even deeper architectures, and they are more parameter and computation efficient. However, the DenseNet architecture is highly non-uniform which complicates the hardware mapping and ultimately slows down training.
Forward path Backward path Figure 2: A simplified building block of a DNN using the straight-through gradient estimator (STE). Q denotes some arbitrary piecewise constant quantization function and id denotes the identity function which simply passes the gradient on during backpropagation. In the forward pass, the solid red line is followed which passes the two piecewise constant functions Q and sign whose gradient is zero almost everywhere (red boxes). During backpropagation, the dashed green line is followed which avoids these piecewise constant functions and instead only passes differentiable functions (green boxes)-in particular, the functions id and tanh whose shapes are similar to Q and sign but whose gradient is non-zero. This allows us to obtain an approximate non-zero gradient for the real-valued parameters W l (blue circle) which are subsequently updated with SGD.

The Straight-Through Gradient Estimator
Many recently developed methods for resource efficiency in DNNs incorporate components in the computation graph of the loss function L that are non-differentiable or whose gradient is zero almost everywhere, such as piecewise constant quantizers. These components prevent the use of conventional gradient-based optimization as described in Section 2.2.
The straight-through gradient estimator (STE) is a simple but effective way to approximate the gradient of such components by simply replacing their gradient with a non-zero value. Let f (w) be some non-differentiable operation within the computation graph of L such that the partial derivative ∂L/∂w is not defined. The STE then approximates the gradient ∂L/∂w by wheref (w) is an arbitrary differentiable function with a similar functional shape as f (w). For instance, in case of the sign activation function f (w) = sign(w) whose derivative is zero almost everywhere, one could selectf (w) = tanh(w). Another common choice is the identity functionf (w) = w whose derivative isf (w) = 1, which simply passes the gradient on to higher components in the computation graph during backpropagation. Figure 2 illustrates the STE applied to a simplified DNN layer.

Bayesian Neural Networks
Since there exist several works for resource-efficient DNNs that build on the framework of Bayesian neural networks, we briefly introduce the basic principles here. Given a prior distribution p(W) over the weights and a likelihood p(D |W) defined by the softmax output of a DNN as we can use Bayes' rule to infer a posterior distribution over the weights, i.e., From a Bayesian perspective it is desired to compute expected predictions with respect to the posterior distribution, i.e., and not just to reduce the entire distribution to a single point estimate. However, due to the highly non-linear nature of DNNs, most exact inference scenarios involving the full posterior p(W |D) are typically intractable and there exist a range of approximation techniques for these tasks, such as variational inference (Hinton and van Camp, 1993;Graves, 2011;Blundell et al., 2015) and sampling based approaches (Neal, 1992). Interestingly, training DNNs can often be seen as a very rough Bayesian approximation where we only seek for weights W that maximize the posterior p(W |D), which is also known as maximum a-posteriori estimation (MAP). In particular, in a typical loss L as in (5) the data term originates from the logarithm of the likelihood p(D |W) whereas the regularizer originates from the logarithm of the prior p(W).
A better Bayesian approximation is obtained with variational inference where the aim is to find a variational distribution q(W |ν) governed by distribution parameters ν that is as close as possible to the posterior p(W |D) but still simple enough to allow for efficient inference, e.g., for computing E q(W | ν) [y(W, x 0 )] by sampling from q. This is typically achieved by the so called mean field assumption, i.e., by assuming that the weights are independent such that q(W |ν) factorizes into a product of factors q(w |ν w ) for each weight w ∈ W. The most prominent approach to obtain the variational distribution q(W |ν) is by minimizing the KL-divergence KL(q(W |ν)||p(W |D)) using gradient-based optimization (Ranganath et al., 2014;Blundell et al., 2015).
The Bayesian approach is appealing as distributions over the parameters directly translate into predictive distributions. In contrast to ordinary DNNs that only provide a point estimate prediction, Bayesian neural networks offer predictive uncertainties which are useful to determine how certain the DNN is about its own prediction. However, the Bayesian framework has got several other useful properties that can be exploited to obtain resourceefficient DNNs. For instance, the prior p(W) allows us to incorporate information about properties, such as sparsity, that we expect to be present in the DNN. In Section 3.1.3, we review weight quantization approaches based on the Bayesian paradigm, and in Section 3.2.3, we review pruning approaches based on the Bayesian paradigm.

Resource Efficiency in Deep Neural Networks
In this section, we provide a comprehensive overview of methods that enhance the efficiency of DNNs regarding memory footprint, computation time, and energy requirements. We have identified three different major approaches that aim to reduce the computational complexity of DNNs, i.e., (i) weight and activation quantization, (ii) network pruning, and (iii) structural efficiency. These categories are not mutually exclusive, and we present individual methods in the category where their contribution is most significant.

Quantized Neural Networks
Quantization in DNNs is concerned with reducing the number of bits used for the representation of the weights and the activations. The reduction in memory requirements are obvious: Using fewer bits for the weights results in a lower memory overhead for storing the corresponding model, and using fewer bits for the activations results in a lower memory overhead for computing predictions. Furthermore, representations using fewer bits often facilitate faster computation. For instance, when quantization is driven to the extreme with binary weights w ∈ {−1, 1} and binary activations x ∈ {−1, 1}, floating-point or fixed-point dot products are replaced by hardware-friendly logical XNOR and bitcount operations. In this way, a sophisticated DNN is essentially reduced to a logical circuit.
However, training such discrete-valued DNNs 5 is difficult as they cannot be directly optimized using gradient-based methods. The challenge is to reduce the number of bits as much as possible while at the same time keeping the prediction accuracy close to that of a welltuned full-precision DNN. In the sequel, we provide a literature overview of approaches that train reduced-precision DNNs, and, in a broader view, we also consider methods that use reduced-precision computations during backpropagation to facilitate low-resource training.

Early Quantization Approaches
Approaches for reduced-precision computations date back at least to the early 1990s. The two works of Höhfeld and Fahlman (Höhfeld and Fahlman, 1992a;Höhfeld and Fahlman, 1992b) rounded the weights during training to fixed-point format with different numbers of bits. They observed that training eventually stalls as small gradient updates are always rounded to zero. As a remedy, they proposed stochastic rounding, i.e., rounding values to the nearest value with a probability proportional to the distance to the nearest value. These quantized gradient updates are correct in expectation, do not cause training to stall, and yield good performance with substantially fewer bits than deterministic rounding. More recently, Gupta et al. (2015) have shown that stochastic rounding can also be applied to modern deep architectures, as demonstrated on a hardware prototype. Lin et al. (2015) propose a method to reduce the number of multiplications required during training. At forward propagation, the weights are stochastically quantized to either binary weights w ∈ {−1, 1} or ternary weights w ∈ {−1, 0, 1} to remove the need for multiplications at all. During backpropagation, inputs and hidden neurons are quantized to powers of two, reducing multiplications to cheaper bit-shift operations, and leaving only a 5. Due to finite precision of computer arithmetic, in fact any DNN is discrete-valued. However, we use this term here to emphasize the extremely small number of values.
negligible number of floating-point multiplications to be computed. However, the speed-up is limited to training since for testing the full-precision weights are required. Courbariaux et al. (2015a) empirically studied the effect of different numeric formats (i.e., floating-point, fixed-point, and dynamic fixed-point) with varying bit widths on the performance of DNNs. Lin et al. (2016) consider fixed-point quantization of pre-trained full-precision DNNs. They formulate a convex optimization problem to minimize the total number of bits required to store the weights and the activations under the constraint that the total output signal-to-quantization noise ratio is larger than a certain prespecified value. A closed-form solution of the convex objective yields layer-specific bit widths.

Quantization-aware Training
Quantization operations, being piecewise constant functions with either undefined or zero derivatives, are not applicable to gradient-based learning using backpropagation. In recent years, the STE (Bengio et al., 2013) (see Section 2.6) became the method of choice to compute an approximate gradient for training DNNs with weights that are represented using a very small number of bits. Such methods typically maintain a set of full-precision weights that are quantized during forward propagation. During backpropagation, the gradients are propagated through the quantization functions by assuming that their gradient equals one. In this way, the full-precision weights are updated using gradients computed at the quantized weights. At test-time, the full-precision weights are abandoned and only the quantized reduced-precision weights are kept. We term this scheme quantization-aware training since quantization is an essential part during forward-propagation and it is intuitive to think of the real-valued weights becoming robust to quantization. In a similar manner, many methods employ the STE to approximate the gradient for the quantization of activations.
In (Courbariaux et al., 2015b), binary weight DNNs are trained using the STE to get rid of expensive floating-point multiplications. They consider deterministic rounding using the sign function and stochastic rounding using probabilities determined by the hard sigmoid function max(0, min(1, (w + 1)/2)). During backpropagation, a set of auxiliary fullprecision weights is updated based on the gradients of the quantized weights. Hubara et al. (2016) extended this work by also quantizing the activations to a single bit using the sign activation function. This reduces the computational burden dramatically as floating-point multiplications and additions are reduced to hardware-friendly logical XNOR and bitcount operations, respectively.  trained ternary weights w ∈ {−a, 0, a}. Their quantizer sets weights whose magnitude is lower than a certain threshold ∆ to zero, while the remaining weights are set to −a or a according to their sign. Their approach determines a > 0 and ∆ during forward propagation by approximately minimizing the squared quantization error of the real-valued weights.  extended this work to ternary weights w ∈ {−a, 0, b} where a > 0 and b > 0 are trainable parameters subject to gradient updates. They propose to select ∆ l based on the maximum full-precision weight magnitude in each layer, i.e., ∆ l = t · max{|w| : w ∈ W l } with t being a hyperparameter. These asymmetric weights considerably improve performance compared to symmetric weights as used by . Rastegari et al. (2016) approximate full-precision weight filters in CNNs by W = αB where α is a scalar and B is a binary weight matrix. This reduces the bulk of floating-point multiplications inside the convolutions to either additions or subtractions and only requires a single multiplication per output neuron with the scalar α. In a further step, the layer inputs x l are quantized in a similar way to perform the convolution using only efficient XNOR and bitcount operations, followed by two floating-point multiplications per output neuron. Again, the STE is used during backpropagation. Lin et al. (2017b) generalized the ideas of Rastegari et al. (2016) by approximating the full-precision weights using linear combinations of multiple binary weight filters for improved classification accuracy.
While most activation binarization methods use the sign function which can be seen as an approximation to the tanh function, Cai et al. (2017) proposed a half-wave Gaussian quantization that more closely resembles the predominant ReLU activation function.
Motivated by the fact that weights and activations typically exhibit a non-uniform distribution, Miyashita et al. (2016) proposed to quantize values to powers of two. Their representation allows getting rid of expensive multiplications, and they report higher robustness to quantization than linear rounding schemes using the same number of bits. Zhou et al. (2017) proposed incremental network quantization where the weights of a pre-trained DNN are first partitioned into two sets. The weights in the first set are quantized to either zero or powers of two. The weights in the second set are kept at full precision and retrained to recover from the potential accuracy degradation due to quantization. They iterate partitioning, quantization, and retraining until all weights are quantized. Jacob et al. (2018) proposed a quantization scheme that accurately approximates floatingpoint operations using only integer arithmetic to speed up computation. During training, their forward pass simulates the quantization step to keep the performance of the quantized DNN close to the performance of using single-precision. At test-time, weights are represented as 8-bit integer values, reducing the memory footprint by a factor of four. Liu et al. (2018) introduced Bi-Real net, a ResNet-inspired architecture where the residual path is implemented with efficient binary convolutions while the shortcut path is kept real-valued to preserve the expressiveness of the DNN. The residual in each layer is computed by first transforming the input with the sign activation, followed by a binary convolution, and a final batch normalization step.
Instead of using a fixed quantizer, in LQ-Net  the quantizer is adapted during training. The proposed quantizer is inspired by the representation of integers as linear combinations v b with v = (2 0 , . . . , 2 K−1 ) and b ∈ {0, 1} K . The key idea is to consider a quantizer that assigns values to the nearest value representable as such a linear combination v b and to treat v ∈ R K as trainable parameters. It is shown that such a quantizer is compatible with efficient bit operations. The quantizer is optimized during forward propagation by minimizing the quantization error objective Bv − x 2 for B ∈ {−1, 1} N ×K and v by alternately fixing B and minimizing v and vice versa. It is proposed to use layer-wise quantizers for the activations and channel-wise quantizers for the weights, i.e., an individual quantizer for each layer and channel, respectively.
Relaxed Quantization (Louizos et al., 2019) introduces a stochastic differentiable soft rounding scheme. By injecting additive noise to the deterministic weights before rounding, one can compute probabilities of the weights being rounded to specific values in a predefined discrete set. Subsequently, these probabilities are used to differentiably round the weights using the Gumbel-softmax approximation (Jang et al., 2017). Since this soft rounding scheme produces only values that are close to values from the discrete set but which are not exactly from this set, the authors also propose a hard variant using the STE. Dong et al. (2019) introduced Hessian-aware mixed-precision quantization for DNNs. Their method quantifies the sensitivity of individual DNN blocks to weight quantization using the largest eigenvalue of the block-wise Hessian matrices which can be computed using the power iteration method. They compute two different orderings of the individual DNN blocks, both of which are based on these eigenvalues. The first ordering determines a relative ordering of the bit widths of individual blocks. This substantially reduces the exponential search space of layer-specific weights and allows them to manually set appropriate bit widths. The second ordering takes these bit widths into account and determines the sequence in which blocks are quantized and fine-tuned using quantization-aware training.
A linear quantizer has three characteristic properties, i.e., (i) a step size Q d , (ii) a dynamic range Q max , and (iii) the number of bits Q b . Since these quantities are interrelated according to a linear quantizer is specified by knowing any two of them (Uhlich et al., 2020). Given fixed layerwise bit widths Q l b , Esser et al. (2020) incorporated layerwise step sizes Q l d as trainable parameters in the computation graph. By training the step sizes Q l d using the STE, they are adapted to the given objective. This is in contrast to previous work, such as XNOR-Net (Rastegari et al., 2016), that determine the step size Q l d using certain statistics obtained from the values to be quantized. Uhlich et al. (2020) extended this idea to mixed-precision quantization. They investigated the three different possibilities to specify a linear quantizer (12) by only two of its characteristic properties and discovered substantial differences in the training behavior. They propose to parameterize the quantizers using the step size Q l d and the dynamic range Q l max and to train these values using backpropagation and the STE to obtain layerwise bit widths Q l b . There also exist works that perform quantization during backpropagation to facilitate resource-efficient training. Zhou et al. (2016) presented several quantization schemes for the weights and the activations that allow for flexible bit widths. Furthermore, they also propose a quantization scheme for backpropagation to facilitate low-resource training. In accordance with earlier work mentioned above, they note that stochastic quantization is essential for their approach. In (Wu et al., 2018b), weights, activations, weight gradients, and activation gradients are subject to customized quantization schemes that allow for variable bit widths and facilitate integer arithmetic during training and testing. In contrast to (Zhou et al., 2016), the work of Wu et al. (2018b) accumulates weight changes to low-precision weights instead of full-precision weights.
While most work on quantization based approaches is empirical, some works gained more theoretical insights Anderson and Berg, 2018). The recent work of Shekhovtsov et al. (2020) has shown that for stochastic binary networks the STE arises from particular linearization approximations.

Bayesian Approaches for Quantization
In this section, we review some quantization approaches, most of which are closely related to the Bayesian variational inference framework (see Section 2.7).
The work of Achterhold et al. (2018) builds on the variational dropout based pruning approach of Louizos et al. (2017) (see Section 3.2.3). They introduce a mixture of loguniform priors whose mixtures are centered at predefined quantization values. Consequently, the approximate posterior also concentrates at these values such that weights can be safely quantized without requiring a fine-tuning procedure.
The following works in this section directly operate on discrete weight distributions and, consequently, do not require a rounding procedure. Soudry et al. (2014) approximate the true posterior p(W |D) over discrete weights using expectation propagation (Minka, 2001) with closed-form online updates. Starting with an uninformative approximation q(W |ν), their approach combines the current approximation q(W |ν) (serving as the prior in Bayes' rule (10)) with the likelihood for a single-sample dataset D n = {(x 0 n , t n )} to obtain a refined posterior. To obtain a closed-form refinement step, they propose several approximations.
Although deviating from the Bayesian variational inference framework as no similarity measure to the true posterior is optimized, the approach of Shayer et al. (2018) trains a distribution q(W |ν) over either binary weights w ∈ {−1, 1} or ternary weights w ∈ {−1, 0, 1}. They propose to minimize an expected loss E q(W | ν) [L(W; D)] for the variational parameters ν with gradient-based optimization using the local reparameterization trick . After training has finished, the discrete weights are obtained by either sampling or taking a mode from q(W |ν). Since their approach is limited to the ReLU activation function, Peters and Welling (2018) extended their work to the sign activation function. This involves several non-trivial changes since the sign activation, due to its zero derivative, requires that the local reparameterization trick must be performed after the sign function. Consequently, distributions need to be propagated through commonly used building blocks such as batch normalization and pooling operations. Roth et al. (2019) further extended these works to beyond three distinct discrete weights, and they introduced some technical improvements.
Van Baalen et al. (2020) propose a Bayesian mixed-precision quantization method for power-of-two bit widths. Their method is based on a recursive view of quantization where residual quantization errors are repeatedly quantized. They introduce gates that determine how many recursive quantization steps should be performed which in turn determines the number of used bits. While the quantization itself is subject to the STE, they propose to train gate probabilities using the Bayesian variational inference framework. The use of fewer bits for quantization is encouraged using a specific prior and, through an additional zero-bit gate, their framework simultaneously allows for weight pruning. Havasi et al. (2019) introduced a novel Bayesian compression technique that we present here in this section although it is rather a coding technique than a quantization technique. In a nutshell, their approach first computes a variational distribution q(W |ν) over realvalued weights using mean field variational inference and then it encodes a sample from q(W |ν) in a smart way. They construct an approximationq(W) to q(W |ν) by importance sampling using the prior p(W) as where δ W i denotes a point mass located at W i . In the next step, a sample W fromq(W) (or, equivalently, an approximate sample from q(W |ν)) is drawn which can be encoded by the corresponding number k ∈ {1, . . . , 2 K } using K bits. Using the same random number generator initialized with the same seed as in (13), the weights W can be recovered by sampling 2 K weights W i from the prior p(W) and selecting W k . Since the number of samples 2 K required to obtain a reasonable approximation to q(W |ν) in (13) grows exponentially with the number of weights, this sampling based compression scheme is performed for smaller weight blocks such that each weight block can be encoded with K bits.

Network Pruning
Network pruning methods aim to achieve parameter sparsity by setting a substantial number of DNN weights to zero. Subsequently, the sparsity is exploited to improve resource efficiency of the DNN. On the one hand, there exist unstructured pruning approaches that set individual weights, regardless of their location in a weight tensor, to zero. Unstructured pruning approaches are typically less sensitive to accuracy degradation, but they require special sparse tensor data structures that in turn yield practical efficiency improvements only for very high sparsity. On the other hand, structured pruning methods aim to set whole weight structures to zero, e.g., by setting all weights of a matrix column to zero we would effectively prune an entire neuron. Conceptually, structured pruning is equivalent to removing tensor dimensions such that the reduced tensor remains compatible with highly optimized dense tensor operations.
In this section, we start with the unstructured case which includes many of the earlier approaches and continue with structured pruning that has been the focus of more recent works. Then we review approaches that relate to Bayesian principles before we discuss approaches that prune structures dynamically during forward propagation.

Unstructured Pruning
One of the earliest approaches to reduce the network size is the optimal brain damage algorithm of LeCun et al. (1989). Their main finding is that pruning based on weight magnitude is suboptimal, and they propose a pruning scheme based on the increase in loss function. Assuming a pre-trained network, a local second-order Taylor expansion with a diagonal Hessian approximation is employed that allows us to estimate the change in loss function caused by weight pruning without re-evaluating the costly network function. Removing parameters is alternated with retraining the pruned network. In this way, the model size can be reduced substantially without deteriorating its performance. Hassibi and Stork (1992) found the diagonal Hessian approximation to be too restrictive, and their optimal brain surgeon algorithm uses an approximated full covariance matrix instead. While their method, similar as in (LeCun et al., 1989), prunes weights that cause the least increase in loss function, the remaining weights are simultaneously adapted to compensate for the negative effect of weight pruning. This bypasses the need to alternate several times between pruning and retraining the pruned network.
However, it is not clear whether these approaches scale up to modern DNN architectures since computing the required (diagonal) Hessians is substantially more demanding (if not intractable) for millions of weights. Therefore, many of the more recently proposed techniques still resort to magnitude-based pruning. Han et al. (2015) alternate between pruning connections below a certain magnitude threshold and re-training the pruned DNN. The results of this simple strategy are impressive, as the number of parameters in pruned DNNs is an order of magnitude smaller (9× for AlexNet and 13× for VGG-16) than in the original networks. Hence, this work shows that DNNs are often heavily over-parameterized. In a follow-up paper,  proposed deep compression, which extends the work in (Han et al., 2015) by a parameter quantization and parameter sharing step, followed by Huffman coding to exploit the non-uniform weight distribution. This approach yields a reduction in memory footprint by a factor of 35-49 and, consequently, a reduction in energy consumption by a factor of 3-5. Guo et al. (2016) discovered that irreversible pruning decisions limit the achievable sparsity and that it is useful to reincorporate weights pruned in an earlier stage. In addition to each dense weight matrix W ∈ R m×n , they maintain a corresponding binary mask matrix T ∈ {0, 1} m×n that determines whether a weight is currently pruned or not. In particular, the actual weights used during forward propagation are obtained as W T where denotes element-wise multiplication. Their method alternates between updating the weights W based on gradient descent, and updating the weight masks T by thresholding the real-valued weights according to where a and b are two thresholds and t refers to the iteration number. Most importantly, weight updates are also applied to the currently pruned weights according to T using the STE, such that pruned weights can reappear in (14). This reduces the number of parameters of AlexNet by a factor of 17.7 without deteriorating performance.

Structured Pruning
In (Mariet and Sra, 2016), a determinantal point process (DPP) is used to find a group of neurons that are diverse and exhibit little redundancy. Conceptually, a DPP for a given ground set S defines a distribution over subsets S ⊆ S where subsets containing diverse elements have high probability. They consider S to be the set of N -dimensional vectors that individual neurons compute over the whole dataset. Their approach samples a diverse set of neurons S ⊆ S according to the DPP and then prunes the other neurons S \ S.
To compensate for the negative effect of pruning, the outgoing weights of the remaining neurons after pruning are adapted so as to minimize the activation change of the next layer.  incorporated group lasso regularizers in the objective to obtain different kinds of sparsity in the course of training. They were able to remove filters, channels, and even entire layers in architectures containing shortcut connections.  proposed to introduce an 1 -norm regularizer on the scale parameters γ of batch normalization and to set γ = 0 by thresholding. Since each batch normalization parameter γ corresponds to a particular channel in the network, this results in channel pruning with minimal changes to existing training pipelines. In (Huang and Wang, 2018), the outputs of different structures are scaled with individual trainable scaling factors. By using a sparsity enforcing 1 -norm regularizer on these scaling factors, the outputs of the corresponding structures are driven to zero and can be pruned.
Rather than pruning based on small parameter values, ThiNet (Luo et al., 2017) is a data-driven approach that prunes channels having the least impact on the subsequent layer. To prune channels in layer l, they propose to sample several activations x l+1 d,w,h at randomly selected spatial locations (w, h) and channels d of the following layer, and to greedily prune channels whose removal results in the least increase of squared error over these randomly selected activations. After pruning, they adapt the remaining filters to minimize the squared reconstruction error by minimizing a least squares problem. Louizos et al. (2018) propose to multiply weights with stochastic binary 0-1 gates associated with trainable probability parameters that effectively determine whether a weight should be pruned or not. They formulate an expected loss with respect to the distribution over the stochastic binary gates. By incorporating an expected 0 -norm regularizer over the weights, the probability parameters associated with these gates are encouraged to be close to zero. To enable the use of the reparameterization trick, a continuous relaxation of the binary gates using a modified binary Gumbel-softmax distribution is used (Jang et al., 2017). They show that their approach can be used for structured sparsity by associating the stochastic gates to entire structures such as channels. Li and Ji (2019) extended this work by using the recently proposed unbiased ARM gradient estimator (Yin and Zhou, 2019) instead of using the biased Gumbel-softmax approximation.

Bayesian Pruning
In (Graves, 2011;Blundell et al., 2015), mean field variational inference is employed to obtain a factorized Gaussian approximation q(W |ν), i.e., instead of learning a deterministic weight w per connection, they train for each connection a weight mean w µ and a weight variance w σ 2 . After training, weights are pruned by thresholding the "signal-to-noise ratio" |w µ /w σ |.
Some pruning approaches are based on variational dropout  which interprets dropout as performing variational inference with specific prior and approximate posterior distributions. Within this framework, the otherwise fixed dropout rates α of Gaussian dropout appear as free parameters that can be optimized to improve a variational lower bound. Molchanov et al. (2017) exploited this freedom to optimize individual weight dropout rates w α such that weights w can be safely pruned if their dropout rate w α is large. This idea has been extended by Louizos et al. (2017) by using sparsity enforcing priors and assigning dropout rates to groups of weights that are all connected to the same structure, which in turn allows for structured pruning. Furthermore, they show how their approach can be used to determine an appropriate bit width for each weight by exploiting the wellknown connection between Bayesian inference and the minimum description length (MDL) principle (Grünwald, 2007).

Dynamic Network Pruning
So far, we have presented methods that result in a fixed reduced architecture. In the following, we present methods that determine dynamically in the course of forward propagation which structures should be computed or, equivalently, which structures should be pruned. The intuition behind this idea is to vary the time spent for computing predictions based on the difficulty of the given input samples x 0 . Lin et al. (2017a) proposed to train, in addition to the DNN, a recurrent neural network (RNN) as decision network which determines the channels to be computed using reinforcement learning. In each layer, the feature maps are compressed using global pooling and fed into the RNN which aggregates state information over the layers to compute its pruning decisions.
In (Dong et al., 2017), convolutional layers of a DNN are extended by a parallel lowcost convolution whose output after the ReLU function is used to scale the outputs of the potentially high-cost convolution. Due to the ReLU function, several outputs of the low-cost convolution will be exactly zero such that the computation of the corresponding output of the high-cost convolution can be omitted. For the low-cost convolution, they propose to use weight tensors W ∈ R 1×1×C×D and W ∈ R K×K×C×1 . However, practical speed-ups are only reported for the K × K convolution where all channels at a given spatial location might get set to zero.
In a similar approach proposed by Gao et al. (2019), the spatial dimensions of a feature map are reduced by global average pooling to a vector a ∈ R C which is linearly transformed to b ∈ R D using a single low-cost fully connected layer. To obtain a sparse vector c ∈ R D , b is fed into the ReLU function, followed by a k-winner-takes-all function that sets all entries of a vector to zero that are not among the k largest entries in absolute value. By multiplying c in a channel-wise manner to the output of a high-cost convolution, at least D − k channels will be zero and need not be computed. The number of channels k is derived from a predefined minimal pruning ratio hyperparameter.

Structural efficiency in DNNs
In this section, we review strategies that establish certain structural properties in DNNs to improve computational efficiency. Each of the proposed subcategories in this section follows rather different principles and the individual techniques might not be mutually exclusive.

Weight Sharing
Another technique to reduce the model size is weight sharing. We note that weight sharing and quantization methods (see Section 3.1) are closely related: Quantization methods often have an inherent weight sharing property since the number of possible quantization values is often much smaller than the number of weights. However, the purpose of a method is typically different depending on which category it belongs to. On the one hand, the focus of weight quantization methods typically lies on the employed numerical formats. The purpose of these formats is to reduce the storage per weight and to facilitate more efficient computations. Furthermore, the number of distinct weight values is typically rather small and fixed, and the particular weight values are often constrained or even fixed in advance. On the other hand, the purpose of weight sharing is to reduce the memory by reducing the overall number of distinct weight values. For these methods, the particular weight values typically remain unconstrained. Note that some methods cannot be clearly attributed to either category, e.g., in deep compression  weight sharing and quantization are in part used synonymously.
In (Chen et al., 2015), a hashing function is used to randomly group network connections into "buckets", where the connections in each bucket share the same weight value. The advantage of their approach is that weight assignments need not be stored explicitly since they are given implicitly by the hashing function. The authors show a memory footprint reduction by a factor of 10 while keeping the predictive performance essentially unaffected.  extended the soft weight sharing approach proposed by Nowlan and Hinton (1992) to achieve both weight sharing and sparsity. The idea is to select a Gaussian mixture model prior over the weights and to train both the weights as well as the parameters of the mixture components. During training, the mixture components collapse to point measures and each weight gets attracted by a certain weight component. After training, weight sharing is obtained by assigning each weight to the mean of the component that best explains it, and weight pruning is obtained by assigning a relatively high mixture mass to a component with a fixed mean at zero. Roth and Pernkopf (2018) utilized weight sharing to reduce the memory footprint of a large Bayesian ensemble of DNNs. The weight sharing is enforced by introducing a Dirichlet process prior over the weight prior distribution. They propose a sampling based inference scheme by alternately sampling weight assignments using Gibbs sampling and sampling weights using Hamiltonian Monte Carlo (Neal, 1992). By using the same weight assignments for multiple weight samples, the memory overhead for the weight assignments becomes negligible and the total memory footprint of an ensemble is reduced.

Knowledge Distillation
Knowledge distillation is a method where the knowledge contained in a large teacher model is transferred to a smaller student model. In the first step, a large teacher model is obtained with conventional training methods on the given training data. Subsequently, the smaller student model is trained on data where the ground truth labels have been replaced by the soft labels obtained from the output of the teacher model, e.g., from the softmax output of a DNN. It has been shown that this substantially increases the accuracy of the student model compared to directly training on the given training data.
This general scheme is model agnostic, and early works applied knowledge distillation to compress ensembles of shallow neural networks (Zeng and Martinez, 2000) and other types of classifiers (Bucila et al., 2006) into a single neural network. Zeng and Martinez (2000) have shown that training on soft labels obtained from the teacher results in higher accuracy than training on the actual hard predictions. The work of Bucila et al. (2006) emphasizes the ability to train the student on unlabeled data to further reduce the accuracy gap between student and teacher. In addition, they presented a method to generate new synthetic inputs from the given training set, which might be useful if additional unlabeled data is limited or not available. They showed that the accuracy of the student can improve substantially when trained on these synthetically generated inputs. Ba and Caruana (2014) applied these ideas to investigate the importance of depth in a DNN. They trained shallower (but not necessarily smaller) neural networks by mimicking the output activations a L produced by a teacher DNN before applying the softmax function. The resulting shallow models perform similar as their deeper counterparts which was not achievable by training the shallow model on the ground truth targets directly. Therefore, the authors conclude that shallower models are as expressive as deeper models but they are more difficult to train.
The work of Li et al. (2014) and Hinton et al. (2015) applied knowledge distillation with the main focus on reducing model complexity of a large teacher DNN. Hinton et al. (2015) proposed to obtain the soft labelsŷ from the teacher by scaling the output activations with a temperature τ > 0 asŷ For τ > 1, the labels tend to become more uniform which has been reported to facilitate training. Furthermore, they propose to utilize the ground truth labels by minimizing a weighted average of the traditional cross-entropy loss based on the ground truth labels t and the knowledge distillation loss based on the soft targetsŷ in (15). Noteworthy, it was the work of Hinton et al. (2015) that coined the term knowledge distillation.
FitNets (Romero et al., 2015) extend these ideas by also transferring knowledge from intermediate layers. They select an intermediate layer from the teacher DNN as the hint layer which they try to mimic in an intermediate guide layer of the student DNN. Since the hint layer and the guide layer are generally of different size, they introduce a regressor that predicts the hint layer from the guide layer. This ensures that the guide layer contains the same information as the hint layer. The proposed procedure operates in two stages. In the first stage, the student is trained up to the guide layer by minimizing the discrepancy between guide and hint layer. In the second stage, the whole student DNN is trained using conventional knowledge distillation as in (Hinton et al., 2015). Kim et al. (2018) argue that matching the raw features of certain intermediate layers as in (Romero et al., 2015) is suboptimal since it is difficult to compare individual layers of different DNNs. Therefore, they propose a method to match more understandable factors extracted from the intermediate layers of the student and the teacher DNNs. Starting from a pre-trained teacher DNN, they first train an autoencoder which they call paraphraser to extract understandable factors from a selected intermediate layer of the teacher DNN. The student DNN is extended by a regressor which they call translator whose purpose is to predict the paraphraser factors from the features of a selected intermediate layer.
The student DNN is then trained to simultaneously minimize the cross-entropy loss on the ground truth labels and the difference between paraphraser and translator output. They employ the paraphraser and the translator after the last convolutional layer in their DNNs.
In the context of quantization, knowledge distillation has been used to reduce the accuracy gap between real-valued DNNs and quantized DNNs (Mishra and Marr, 2018;Polino et al., 2018). In particular, a real-valued teacher DNN is used to improve the accuracy of a quantized student DNN. Mishra and Marr (2018) showed improved results using three different modes of knowledge distillation training, including a mode where the student and the teacher are trained simultaneously from scratch. Phuong and Lampert (2019) transferred knowledge between different parts of the same model. They employ multi-exit architectures which provide anytime predictions after certain intermediate layers; therefore, allowing for a trade-off between accuracy and prediction latency at run-time. The knowledge from the (most accurate) final layer is transferred to the earlier exits to improve their accuracy. Furthermore, they show that the earlier layers can be trained with unlabeled data in a semi-supervised setting.
In a Bayesian context, Korattikara et al. (2015) applied knowledge distillation to condense a large ensemble of DNNs, for instance, obtained by sampling from the posterior distribution p(W |D). In this way, expected predictions (11) obtained by averaging the outputs of the individual models can be transferred to a single DNN. Their method trains a single student DNN using the outputs of teacher DNNs that are generated on the fly using SGLD (Welling and Teh, 2011).

Special Matrix Structures
In this section, we review approaches that aim at reducing the model size by employing efficient matrix representations. There exist several methods using low-rank decompositions which represent a large matrix (or a large tensor) using only a fraction of the parameters. In most cases, the implicitly represented matrix is never computed explicitly such that also a computational speed-up is achieved. Furthermore, there exist approaches using special matrices that are specified by only few parameters and whose structure allows for extremely efficient matrix multiplications. Denil et al. (2013) proposed a method that is motivated by training only a subset of the weights and predicting the values of the other weights from this subset. In particular, they represent weight matrices W ∈ R m×n using a low-rank approximation UV with U ∈ R m×k , V ∈ R k×n , and k < min{m, n} to reduce the number of parameters. Instead of learning both factors U and V, prior knowledge, such as smoothness of pixel intensities in an image, is incorporated to compute a fixed V using kernel-techniques or auto-encoders, and only the factor U is learned.
In (Novikov et al., 2015), the tensor train matrix format is employed to substantially reduce the number of parameters required to represent large weight matrices of fully connected layers. Their approach enables the training of very large fully connected layers with relatively few parameters, and they achieve improved performance compared to simple lowrank approximations. Denton et al. (2014) propose specific low-rank approximations and clustering techniques for individual layers of pre-trained CNNs to reduce both memory footprint and computational overhead. Their approach yields substantial improvements for both the computational bottleneck in the convolutional layers and the memory bottleneck in the fully connected layers. By fine-tuning after applying their approximations, the performance degradation is kept at a decent level. Jaderberg et al. (2014) propose two different methods to approximate pre-trained CNN filters as combinations of rank-1 basis filters to speed up computation. The rank-1 basis filters are obtained either by minimizing a reconstruction error of the original filters or by minimizing a reconstruction error of the outputs of the convolutional layers. Lebedev et al. (2015) approximate the convolution tensor using the canonical polyadic (CP) decomposition-a generalization of low-rank matrix decomposi-tions to tensors-using non-linear least squares. Subsequently, the convolution using this low-rank approximation is performed by four consecutive convolutions, each with a smaller filter, to reduce the computation time substantially.
In (Cheng et al., 2015), the weight matrices of fully connected layers are restricted to circulant matrices W ∈ R n×n , which are fully specified by only n parameters. While this dramatically reduces the memory footprint of fully connected layers, circulant matrices also facilitate faster computation as matrix-vector multiplication can be efficiently computed using the fast Fourier transform. In a similar vein, Yang et al. (2015) reparameterize matrices W ∈ R n×n of fully connected layers using the Fastfood transform as W=SHGΠHB, where S, G, and B are diagonal matrices, Π is a random permutation matrix, and H is the Walsh-Hadamard matrix. This reparameterization requires only a total of 4n parameters, and similar as in (Cheng et al., 2015), the fast Hadamard transform enables an efficient computation of matrix-vector products.

Manual Architecture Design
Instead of modifying existing architectures to make them more efficient, manual architecture design is concerned with the development of new architectures that are inherently resource-efficient. Over the past years, several design principles and building blocks for DNN architectures have emerged that exhibit favorable computational properties and sometimes also improve performance.
CNN architectures are typically designed to have a transition from convolutional layers to fully connected layers. At this transition, activations at all spatial locations of each channel are typically used as individual input features for the following fully connected layer. Since the number of these features is typically large, there is a memory bottleneck for storing the parameters of the weight matrix especially in the first fully connected layer. Lin et al. (2014a) introduced two concepts that have been widely adopted by subsequent works. The first one, global average pooling, largely solves the above-mentioned memory issue at the transition to fully connected layers. Global average pooling reduces the spatial dimensions of each channel into a single feature by averaging over all values within a channel. This reduces the number of features at the transition drastically, and, by having the same number of channels as there are classes, it can also be used to completely get rid of fully connected layers. Second, they used 1 × 1 convolutions with weight kernels W ∈ R 1×1×C×D which can be seen as performing the operation of a fully connected layer over each spatial location across all channels.
These 1 × 1 convolutions have been adopted by several popular architectures  and, due to their favorable computational properties compared to convolutions that take a spatial neighborhood into account, later have also been exploited to improve computational efficiency. For instance, InceptionNet  proposed to split standard K × K convolutions into two cheaper convolutions: (i) a 1 × 1 convolution to reduce the number of channels such that (ii) a subsequent K × K convolution is performed faster. Similar ideas are used in SqueezeNet (Iandola et al., 2016) which employs 1 × 1 convolutions to reduce the number of input channels of subsequent parallel 1 × 1 and 3 × 3 convolutions. In addition, SqueezeNet uses the global average pooling output of per-class channels directly as input to the softmax in order to avoid fully connected layers that typically consume the most memory. On top of that, they also applied deep compression ) (see Section 3.2.1) to reduce the memory footprint of their model even further. Szegedy et al. (2016) extended the InceptionNet architecture by spatially separable convolutions to reduce the computational complexity, i.e., a K × K convolution is split into a K × 1 convolution followed by a 1 × K convolution. In MobileNet (Howard et al., 2017) depthwise separable convolutions are used to split a standard convolution in another way: (i) a depthwise convolution and (ii) a 1 × 1 convolution. The depthwise convolution applies a K × K filter to each channel separately without taking the other channels into account whereas the 1 × 1 convolution then aggregates information across channels. Although these two cheaper convolutions together are less expressive than a standard convolution, they can be used to trade off a small loss in prediction accuracy with a drastic reduction in computational overhead and memory requirements. Sandler et al. (2018) extended these ideas in their MobileNetV2 to an architecture with residual connections. A typical residual block with bottleneck structure in ResNet  contains a 1 × 1 bottleneck convolution to reduce the number of channels, followed by a 3 × 3 convolution, followed by another 1 × 1 convolution to restore the original number of channels again. Contrary to that building block, MobileNetV2 introduces an inverted bottleneck structure where the shortcut path contains the bottleneck and the residual path performs computations in a high-dimensional space. In particular, the residual path performs a 1 × 1 convolution to increase the number of channels, followed by a cheap depthwise 3 × 3 convolution, followed by another 1 × 1 convolution to reduce the number of channels again. They show that their inverted structure is more memory efficient since the shortcut path, which needs to be kept in memory during computation of the residual path, is considerably smaller. Furthermore, they show improved performance compared to the standard bottleneck structure.
While it was more of a technical detail rather than a contribution on its own, AlexNet (Krizhevsky et al., 2012) used grouped convolutions with two groups to facilitate model parallelism for training on two GPUs with relatively low memory capacity. Instead of computing a convolution using a weight tensor W ∈ R K×K×gC×gD , a grouped convolution splits the input into g groups of C channels that are independently processed using weight tensors W g ∈ R K×K×C×D . The outputs of these g convolutions are then stacked again such that the same number of input and output channels are maintained while considerably reducing the computational overhead and memory footprint.
Although this reduces the expressiveness of the convolutional layer since there is no interaction between the different groups, Xie et al. (2017) used grouped convolutions to enlarge the number of channels of a ResNet model which resulted in accuracy gains while keeping the computational complexity of the original ResNet model approximately the same. Zhang et al. (2018b) introduced a ResNet-inspired architecture called ShuffleNet which employs 1 × 1 grouped convolutions since 1 × 1 convolutions have been identified as computational bottlenecks in previous works, e.g., see (Howard et al., 2017). To combine the computational efficiency of grouped convolutions with the expressiveness of a full convolution, ShuffleNet incorporates channel shuffle operations after grouped convolutions to partly recover the interaction between different groups.

Neural Architecture Search
Neural architecture search (NAS) is a recently emerging field concerned with the automatic discovery of good DNN architectures. This is achieved by designing a discrete space of possible architectures in which we subsequently search for an architecture that optimizes some objective -typically the validation error. By incorporating a measure of resource efficiency into this objective, this technique has recently attracted attention for the automatic discovery of resource-efficient architectures.
The task is very challenging: On the one hand, evaluating the validation error is timeconsuming as it requires a full training run and typically only results in a noisy estimate thereof. On the other hand, the space of architectures is typically of exponential size in the number of layers. Hence, the space of architectures needs to be carefully designed in order to facilitate an efficient search within that space.
The influential work of Zoph and Le (2017) introduced a scheme to encode DNN architectures of arbitrary depth as sequences of tokens which can be sampled from a controller RNN. This controller RNN is trained with reinforcement learning to generate well performing architectures using the validation error on a held-out validation set as a reward signal. However, the training effort is enormous since more than 10,000 training runs are required to achieve state-of-the-art performance on CIFAR-10. This would be impractical on larger datasets such as ImageNet which was partly solved by subsequent NAS approaches, e.g., in (Zoph et al., 2018). In this review, we highlight methods that also consider resource efficiency constraints for NAS.
In MnasNet (Tan et al., 2018), a RNN controller is trained by also considering the latency of the sampled DNN architecture measured on a real mobile device. They achieve performance improvements under predefined latency constraints on a specific device. To run MnasNet on the large-scale datasets ImageNet and COCO (Lin et al., 2014b), their algorithm is run on a proxy task by only training for five epochs, and only the most promising DNN architectures were trained using more epochs.  determined the individual bit widths of mixed-precision quantization using a similar reinforcement learning framework. Their controller DNN generates for each layer two bit widths, one for the weights and one for the activations. A pre-trained fullprecision DNN is then quantized using these bit widths and fine-tuned for one epoch to obtain a reward signal that is subsequently used to update the controller. Their method incorporates hardware-specific constraints, such as latency and energy consumption, that must be met by the controller.
Instead of generating architectures using a controller, ProxylessNAS (Cai et al., 2019) uses a heavily over-parameterized model where each layer contains several parallel paths, each computing a different architectural block with its individual parameters. For each layer, probability parameters for selecting a particular architectural block are introduced which are trained via backpropagation using the STE. After training, the most probable path determines the selected architecture. To favor resource-efficient architectures, a latency model is build using measurements done on a specific real device whose predicted latencies are used as a differentiable regularizer in the cost function. In their experiments, they show that different target devices prefer individual DNN architectures to obtain a low latency.
Instead of using a different path for different operations in each layer, single-path NAS (Stamoulis et al., 2019) combines all operations in a single shared weight superblock such that each operation uses a subset of this superblock. A weight-magnitude-based decision using trainable threshold parameters determines which operation should be performed, allowing for gradient-based training of both the weight parameters and the architecture. Again, the STE is employed to backpropagate through the threshold function. Wu et al. (2018a) performed mixed-precision quantization using similar NAS concepts to those used by Liu et al. (2019a) and Cai et al. (2019). They introduce gates for every layer that determine the number of bits used for quantization, and they perform continuous stochastic optimization of probability parameters associated with each of these gates. Liu et al. (2019b) have replicated several experiments of pruning approaches (see Section 3.2) and they observed that the typical workflow of training, pruning, and fine-tuning is often not necessary and only the discovered sparsity structure is important. In particular, they show for several pruning approaches that randomly initializing the weights after pruning and training the pruned structure from scratch results in most cases in a similar performance as performing fine-tuning after pruning. They conclude that network pruning can also be seen as a paradigm for architecture search.
Tan and Le (2019) recently proposed EfficientNet which employs NAS for finding a resource-efficient architecture as a key component. In the first step, they perform NAS to discover a small resource-efficient model which is much cheaper than searching for a large model directly. In the next step, the discovered model is enlarged by a principled compound scaling approach which simultaneously increases the number of layers, the number of channels, and the spatial resolution. Although this approach is not targeting resource efficiency on its own, EfficientNet achieves state-of-the-art performance on ImageNet using a relatively small model.

Embedded Hardware for Deep Neural Networks
Improvements in hardware for deep learning are a key driver for the recent success stories of AI applications through DNNs. Both training and inference have extremely high demands on their targeted platform and certain hardware requirements can be the deciding factor whether an application can be realized. This section briefly introduces the most important hardware for deep learning and discusses their potentials and limitations. While this discussion is generic and independent from training or inference, it should be noted that all processor concepts are available in different scales, ranging from mobile to server variants.

CPUs
CPUs were originally designed to optimize single-thread performance in order to execute an individual computation within the shortest possible latency. Unfortunately, single-thread performance is stagnating since the end of Dennard scaling (Dennard et al., 1974), and now performance scaling usually requires parallelization. While multithreading is a rather obvious solution for parallelization that is applicable to many tasks, vectorization is a technique that promises great potential for certain applications. Vectorization applies a single instruction to multiple pre-selected data elements and, thus, avoids costly at-runtime dependency checking while maximizing instruction reuse. CPUs show excellent properties of exploiting sparse DNNs due to their short vector units and the low amount of multithreading together with high frequency. Furthermore, they usually support 8-bit integer formats and feature certain instructions for extremely low representation and, consequently, they are well suited for quantization operations.

GPUs
GPUs were initially designed to accelerate image and video processing only and are nowadays the most popular general-purpose accelerators for many tasks, such as scientific and AI computations. The architecture consists of many streaming multiprocessors which are highly parallel and each implements many lightweight cores. Thus, GPUs are massively parallel processors with large memory that provides extremely high bandwidth and throughput, but significantly lower frequency in comparison to CPUs. The extremely high amount of parallelism and the resulting demand on structured computations, however, virtually prevents the deployment of sparse computations. Modern GPU designs and their respective software stack implement support for reduced-precision computations, such as 8-bit integer and half-precision floating-point formats, which are very well suited for deep learning. More extreme forms of quantization are not yet supported and do not result in more efficient inference or training.

FPGAs
Field-programmable gate arrays (FPGAs) are a family of processors that implement a large array of configurable logic blocks which can be programmed using hardware description languages (e.g., VHDL, Verilog, HLS). This concept is the main difference to ASICs in terms of technology since the hardware can be designed for specific functional or application requirements. While this reconfigurability enables various opportunities that go beyond the capabilities of CPUs and GPUs, it comes at the cost of much lower frequency and reduced on-chip memory. FPGAs are in principle very well suited for DNNs, since compute units can be specifically tailored to fit the diverse computations while also enabling massive amounts of parallelism. Reconfigurable hardware is especially interesting for compressed DNNs due to their flexibility to implement any data format as well as sparse logic.

Domain-Specific Accelerator
Recent interest in deep learning has motivated to push advancements in the development of custom accelerators, such as Google's TPUs and Graphcore's IPU. The key feature of the TPU (and most of the other deep learning accelerators) is a 256×256 matrix-multiplication unit that is referred to as systolic array. Systolic arrays are a variant of massively parallel processor arrays that are very suitable for regular tasks, such as linear algebra operations, and a promising candidate to address the increasing costs of data movements. The objective of such arrays is to minimize instruction fetch and data access costs by constraining the data flow to matrix and vector operations. However, data movements can only be reduced if locality effects are sufficiently exploited and the data flow constraints of a systolic array may result in poor utilization and latency increase. Such domain-specific accelerators are usually highly constrained when aiming to optimize DNNs through compression. For instance, the TPU supports 8-bit integer and half-precision floating-point formats while other (potentially lower-precision) representations are not efficiently supported by hardware. Furthermore, the dense structure of the systolic arrays demands for similarly dense computations and cannot exploit fine-grained sparsity patterns.

Loop-Back vs. Data-Flow Architectures
One can roughly categorize hardware platforms for deep learning inference into loop-back and data-flow architectures. Loop-back architectures use a fixed processor and memory system to move data from off-chip memory to the processor and leverage the available compute resources. This is performed for each layer or operation sequentially until inference computation has finished. The drawback of loop-back architectures is that they potentially require many data movements from and to off-chip memory, which is time and energy consuming. CPUs aim to reduce these memory accesses by featuring large on-chip caches and reuse data as much as possible. Similar are domain-specific accelerators, such as TPUs, which usually feature a large and programmable scratch pad memory on chip. On the contrary, GPUs feature large register files and aim to hide memory latency by leveraging parallel slackness. Another critical aspect of loop-back architectures is low compute utilization, which can potentially occur if certain layer or operation types do not fit the static compute array (i.e., if operation size is too low). The advantage of such a generic compute architecture is that they allow arbitrary operations in combination with productive code generation since the hardware does not need to be optimized for a certain task. Continuous improvements in semi-conductor and processor technology are the main improvement factor of such inference engines.
In contrast to this, data-flow architectures use a reconfigurable processor and memory system for computing the inference. Here, each layer or operation within a neural architecture is assigned a dedicated compute engine and its own memory subsystem in order to enable inference in a pipelined fashion. This avoids off-chip accesses for intermediate operations completely by simple forwarding the computed results to the next hardware layer. Furthermore, data-flow architectures achieve excellent utilization of the available hardware logic, since several compute engines can be tailored to the required operation type and latency. One drawback of this data-flow architecture is, however, that it requires long development costs because it does not only require software but also hardware optimizations. In addition, reconfigurable hardware comes at the cost of reduced absolute compute power in comparison to ASIC designs. The main limitation of data-flow architectures is that they demand the entire neural architecture (weights and activations) to be put on chip, which is highly restrictive for large models.

Experimental Results
We provide experimental results for modern DNN architectures trained on well-known benchmark datasets. The focus of our experiments is on quantization (see Section 3.1) and structured pruning approaches (see Section 3.2.2) since they are among the earliest and most efficient approaches to enhance the computational efficiency of DNNs.
We compare several quantization approaches discussed in this paper in terms of prediction quality in Section 5.1.1. Next, we compare different DNN architectures and pruning structures (i.e., the type of structure considered for pruning, such as channels) using model metrics such as number of computations and memory requirements in Section 5.1.2. Furthermore, we benchmark the compressed models on mobile variants of CPU (Section 5.2.1), FPGA (Section 5.2.2), and GPU (Section 5.2.3), and provide an overall comparison in Section 5.2.4.
The main focus of this section is to showcase the difficulty of finding good trade-offs between resource efficiency and predictive performance. As this paper is mainly dedicated to giving a comprehensive literature overview of the current state of the art, an extensive evaluation of the many presented methods in Section 3 would be infeasible and it is also not within the scope of this paper.

Prediction Quality using Different Quantization Approaches
In the first experiment we compare the performance of several quantization approaches. We use a DenseNet architecture  consisting of 100 layers with bottleneck and compression layers, i.e., a DenseNet-BC-100. We select the default growth rate of k = 12 for the model, i.e., the number of feature maps added per layer. We conduct our experiments on the CIFAR-100 dataset where the task is to classify RGB images of size 32×32 pixels to one of 100 object categories. The CIFAR-100 dataset is split into 50,000 training images and 10,000 test images. We selected some of the most popular quantization approaches (see Section 3.1) for our comparison: binary weight networks (BWN) (Courbariaux et al., 2015b), binarized neural networks (BNN) (Hubara et al., 2016), DoReFa-Net (Zhou et al., 2016), trained ternary quantization (TTQ) , and LQ-Net . For this experiment, we quantize the DNNs in three different modes: (i) weightonly, (ii) activation-only, and (iii) combined weight and activation quantization. However, note that some quantization approaches are designed for a particular mode, e.g., BWN and TTQ only consider weight quantization whereas BNN only considers combined weight and activation quantization. Figure 3 reports the test errors for different bit widths of the selected quantization approaches. The horizontal red line shows the test error of the real-valued baseline DenseNet-BC-100. For combined weight and activation quantization we use the same bit widths for the weights and the activations.
As expected, the test error decreases gradually with increasing bit widths for all quantization modes and for all quantization approaches. Furthermore, the results indicate that prediction performance is more sensitive to activation quantization than to weight quantization, which is in line with the results reported by many works reviewed in Section 3.1.
The more advanced LQ-Net approach clearly outperforms the rather simple linear quantization of DoReFa-Net and the specialized binary and ternary approaches. However, this performance improvement comes at the cost of longer training times. For instance, the training time per iteration increases-in relation to training without quantization-for DoReFa-Net by a factor of 1.5 compared to a factor of up to 4.6 (depending on the bit width) for LQ-Net. Figure 3: Comparison of several popular quantization approaches (see Section 3.1) using the DenseNet-BC-100 architecture trained on the CIFAR-100 dataset. The horizontal red line shows the error of the real-valued baseline. Quantization is performed using different bit widths in three different modes: activation-only (blue), weight-only (green), and combined weight and activation quantization (purple).

Prediction Quality using Different Pruning Structures
In the next experiment, we explore the performance metrics of different DNN architectures (ResNet and DenseNet) and pruning structures (such as channels, kernels and groups) on the CIFAR-10 task. CIFAR-10 is similar to CIFAR-100 used in the previous section (i.e., image size and size of training and test sets are equal) except that it contains only ten object classes. We use wide residual networks (WRNs) by Zagoruyko and Komodakis (2016) with a depth of 28 layers, one of the top performing architectures on this task. This architecture is identical to the original ResNet model except that it is scaled in width rather than depth. Additionally, we create a DenseNet variant for this experiment which is scaled in depth to 28 layers and the width is varied until it approximately matches the number of parameters and computations of the WRN model in order to guarantee a fair comparison. We apply parameterized structured pruning (PSP) by Schindler et al. (2020), a method that allows to dynamically learn the shape of DNNs through structured sparsity. PSP parameterizes arbitrary structures in a weight tensor and leverages weight decay to detect unimportant structures that can be pruned. In this experiment, we select pruning structures that are in line with commonly used DNN libraries for convolutions: we use channel pruning to learn the number of input and output feature maps, kernel pruning to learn the size of the convolution kernel, and group pruning to learn heterogeneous group sizes for grouped convolutions (see Section 3.3.4 for a discussion on grouped convolutions). In a first step, channel (WRN: Channel ), kernel (WRN: Kernel ), and group pruning (WRN: Group) are evaluated separately on the WRN architecture. The results for number of floating-point operations (FLOPs), parameters, activations, and memory (= parameters + activations) are reported in Figure 4. When considering the number of FLOPs and parameters, which are the main metrics in the literature on resource-efficient DNNs, it is clear that channel and group pruning significantly outperform kernel pruning. This indicates a high sensitivity of the kernel size to the overall accuracy. Group and channel pruning perform very similar with respect to FLOPs and parameters, especially for highly compressed models. However, when also considering the number of activations and overall memory consumption (i.e., parameters and activations), group pruning performs significantly worse since grouped convolutions only remove connections from input channels to output channels while keeping the overall number of channels the same. As a result, channel pruning is the best performing compression structure when applied in isolation.
In a next step, the group size is set to 64 and channel pruning is applied (WRN: G=64 Channel ), in order to evaluate the performance when different sparse structures are combined. This combination performs worse than pure channel pruning for all metrics and requires a large amount of activations. Ultimately, it can be stated that group convolutions are excellent at reducing FLOPs and parameters but can harm the overall memory requirements by increasing the amount of activations.
Last, the DenseNet variant is compressed using channel pruning (Dense: Channel ). The dense architecture outperforms the residual blocks in terms of number of FLOPs as well as parameters. In terms of number of activations, however, residual blocks are clearly more beneficial, which also influences the overall memory consumption. In summary, one can observe that DenseNets are more parameter/computation-efficient and ResNets are more memory-efficient.

Evaluating Compressed DNNs on CPU
Section 5.1 explored the impact of several network quantization approaches and structured pruning on the prediction quality. In this section. we use the well-performing LQ-Net approach for quantization and PSP (for channel pruning) to measure the inference throughput of the quantized and pruned models separately on an ARM Cortex-A53 CPU. The WRN model on the CIFAR-10 task is used again as a baseline, with a depth of 28 layers, varying widths of the model, and weights/activations quantized to different bit widths. Figure 5 reports test accuracies and throughput for different WRN variants and compression methods. Please note that multiple points for the same bit width correspond to a different width scaling of the model.
The results reveal that quantization does not provide throughput improvements on this processor. This is mainly caused by the efficient floating-point units within the CPU in combination with fast on-chip memory and the high overhead caused by performing low-bit-width computations. Moreover, the dimensions of some layers are too small to fit well to the bit level vectorized instructions and these layers limit the overall performance. Together with the accuracy reduction, low-bit-width quantization does not yield convincing results on this processor. Quantized DNNs with 1-bit weights and activations are the worst Figure 5: Throughput-accuracy trade-off of pruned and quantized WRN models on the CIFAR-10 task for an ARM CPU.
performing models, which is due to the severe implications of extreme quantization on prediction performance. As can be seen, however, the overall performance of the quantized models increases considerably when the bit width of activations is increased to 2-3 bit whilst the bit width of the weights is kept low. On the contrary, channel pruning consistently performs equally to the baseline model with respect to accuracy and throughput. Pruning is therefore the more suitable compression technique for this embedded processor, especially when considering that CPUs could potentially leverage a much finer sparsity granularity.

Evaluating Quantized DNNs on FPGAs
While the previous section indicates that quantized DNNs do not provide throughput improvements on general-purpose processors without explicit hardware support, there are other hardware platforms where quantization is mandatory. Data-flow architectures, as found typically on FPGAs, where the main objective is to keep all required data for inference in on-chip memory, are usually constrained by the requirements for weight as well as activation storage. This section evaluates quantized DNNs on FPGAs using the FINN framework (Umuroglu et al., 2017) for generating data-flow architectures on reconfigurable hardware. Figure 6 shows test accuracy over throughput of the FINN data-flow architectures mapped to a XILINX Ultra96 FPGA using different bit combinations. A variant of the VGG architecture is used on the CIFAR-10 task for evaluation because FINN does not support residual connections yet, and the configuration of the FINN framework is adjusted so that highest throughput is targeted with respect to the available resources of the device (BRAM, LUTs, etc). Figure 6: Throughput-accuracy trade-off of different quantized VGG models on the CIFAR-10 task for an FPGA data-flow architecture.
As expected, the test accuracy increases gradually with high bit widths while the throughput decreases accordingly. Following the Pareto front starting from the bottom right indicates that the best performing models use a combination of 1 bit for the weights and a gradual increase of activations up to 3 bits. Afterwards the models perform best if the weights are scaled to 2 bits and the activation bit width is further increased to 4 bits. This supports the observation of the previous sections, showing that model accuracy is sensitive to activation quantization rather than weight quantization.

Evaluating Pruned DNNs on GPU
Section 5.1.2 explored several pruning structures and DNN architectures which indicate different potential with respect to computation and memory efficiency. This section evaluates how these metrics impact the inference speed in terms of throughput. The same models are used as in Section 5.1.2, i.e., different WRN variants and DenseNet on the CIFAR-10 task. Figure 7 reports key inference metrics using the TensorRT framework targeting a Jetson Nano GPU. Half-precision floating-point precision is used for weights as well as activations and other reduced precision formats are omitted because the accelerator and its software infrastructure do not support arbitrary precision types.
As can be seen, the various models in each regime (pruning structure or DNN architecture) show similar behavior for throughput. The worst performing regimes are group and kernel pruning as well as the combination of fixed grouping and channel pruning. Especially interesting is group pruning: although it greatly reduces FLOPs and parameters, it fails at translating this reduction into faster computations. Opposed to this, pure channel pruning Figure 7: Throughput-accuracy trade-off of different pruning methods for an embedded GPU on the CIFAR-10 task.
using residual and dense architectures achieve the best performance. These results highlight the importance of reducing memory (or more specifically activations) rather than FLOPs in order to reduce latency or increase throughput.

Overall Comparison
The previous sections studied several compression methods with considerations on targeted software and hardware stack. Each section had a focus on leveraging compression to accelerate inference computations as much as possible while maintaining the prediction quality of the uncompressed model. In this section we compare these specialized forms of compression on their respective hardware in terms of absolute performance to identify the most promising compute concepts for DNNs. Notably, whilst fundamentally different in architecture, from a system-level view these three processors, namely ARM Cortex-A57 CPU, NVIDIA Nano GPU, and XILINX Ultra96 FPGA, are comparable as they all exhibit a power consumption in the range of about 5 Watts. Figure 8 reports throughput and accuracy for these devices using different compression methods.
CPUs are well suited for mapping compressed DNNs. However, the comparison to massively parallel processors shows that they lack the necessary amount of parallelism to achieve competitive throughput. The benefit of CPUs is that they feature a relatively large memory, allowing large and accurate models to be deployed.
FPGAs excel at extremely-high-throughput inference and high utilization of the available hardware resources. Such data-flow architectures, however, demand the entire model (including activations) to stay on chip, possibly preventing larger and more accurate models to be deployed.
GPUs are relatively constrained in terms of flexibility when deploying compressed models, due to the requirement of using optimized libraries and their respective software stack. However, they show a good compromise of programmable, general-purpose processing, enabling high throughput and accuracy. Additionally, they feature a large off-chip memory which in combination with latency hiding techniques enables high-throughput inference for large models.

Conclusion
We presented an overview of the vast literature of the highly active research area concerned with resource efficiency of DNNs. We have identified three major directions of research, namely (i) network quantization, (ii) network pruning, and (iii) approaches that target efficiency at the structural level. Many of the presented works are orthogonal and can in principle be used in combination to potentially further improve the results reported in the respective papers.
We have discovered several patterns in the individual strategies for enhancing resource efficiency. For quantization approaches, a common pattern in the most successful approaches is to combine real-valued representations, that help in maintaining the expressiveness of DNNs, with quantization to enhance the computationally intensive operations. More recently, mixed-precision quantization, where the bit widths are determined during training, is an upcoming topic. For pruning methods, we observed that the trend is moving towards structured pruning approaches that obtain smaller models whose data structures are compatible with highly optimized dense tensor operations. On the structural level of DNNs, a lot of progress has been made in the development of specific architectures that maintain a high expressiveness of the DNN while at the same time reducing the computational overhead substantially. The newly emerging NAS approaches are promising candidates to automate the design of application-specific architectures with little user interaction. However, it appears unlikely that current NAS approaches will discover new fundamental design principles as the resulting architectures highly depend on a-priori knowledge encoded in the architecture search space.
In experiments, we demonstrated the difficulty of finding a good trade-off among computational complexity, embedded hardware, and predictive performance on two benchmark datasets. We demonstrated on three embedded hardware platforms that massive parallelism is required for inference efficiency and that quantization as well as structured pruning map well onto these accelerators.