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Evaluation of the Scalability of Round Robin Arbiters for NoC Routers on FPGA

Network-on-Chip (NoC) performance is directly influenced by latency of routers and throughput obtained in some specific topologies. The arbitration inside routers plays an important role in the whole system performance. The size of the arbiters is affected by the node degree and number of virtual channels of the routers. In the literature most of arbiter designs were targeting VLSI, but the mapping of these architectures to the programmable logic and interconnect of an FPGA is not explored. In this paper, we re-evaluate the most famous Round Robin Arbiter (RRA) architectures on FPGA to fulfill this gap. We compare RRA implementations with respect to speed and area. This work will allow NoC designers to scrupulously choose the suitable design of RRA trading-off performance and area.