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A digital calibration technique for multi-bit-per-stage pipelined ADC

In this paper, a digital calibration algorithm, based on original radix 2 off-line algorithm, is employed to calibrate a 4 stages, 12 bits pipelined Analog-to-Digital Converter(ADC). The detail implementation process of this algorithm, from algorithm design to circuit structure, is presented. The simulation results show that the calibrated ADC achieves SNR of 73.9 dB, SNDR of 73.3 dB, SFDR of 84.2 dB, DNL of 0.47 LSB and INL of 0.84 LSB.