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Thermal management solutions for a lightweight 3L GaN inverter

This paper presents a comparative study of different approaches and solutions to the cooling of new type highly compact flat packages for gallium nitride (GaN) transistors. The focus here is on an inverter intended for hybrid and full-electric transport applications, where optimization of the gravimetric power density is paramount. As a case-study, a 3-level active neutral point clamped (aNPC) bi-directional inverter-rectifier topology is considered. The outcomes of the investigation are manifold: optimum design of thermal vias is considered; it is highlighted that the use of a graphene layer just underneath the chip can help reduce the temperature gradient between chip and PCB and can also improve heat-conduction in subsequent layers of the assembly, by enabling a better exploitation of lateral heat-flow possibilities, too; the benefit of using a soldered DCB substrate to assist heat removal from the vias towards the heat-sink is quantified for different materials of the insulating layer (ceramic).