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A CAM-based VLSI architecture for shared buffer ATM switch with fuzzy controlled buffer management

This paper proposes a CAM-based shared buffer ATM switch-on-a-chip architecture that takes network-element internal congestion control into consideration. This internal congestion control includes selective cell discard, priority service scheduling, and fuzzy controlled buffer management. To provide "fair" access to the network resources for all users, the SMXQ buffer control scheme is adopted. The SMXQ scheme assumes a queue length threshold is chosen for the logical queue pertaining to each output port, and if the queue length exceeds the threshold the arriving cells are discarded. Selective cell discard is performed per port basis when the shared buffer is full or the queue length of a particular output port exceeds its threshold. For each output port, {CLP=1} cells will be discarded before any {CLP=0} cell is discarded. The set of chosen queue length thresholds are computed directly by an on-chip fuzzy congestion controller (FCC) in sub microsecond intervals.