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Performance and Hardware Complexity Trade-offs for Digital Transparent Processors in 5G Satcoms

In the emerging global framework for fifth generation (5G) wireless technologies, transparent satellites may be considered as an appealing solution to provide backhaul connectivity to the on-ground Relay Nodes. Nevertheless, along the last decade semi-transparent transponder architectures have received major attention. This kind of architectures has appeared as a viable alternative to provide broadband connectivity in modern network topologies with large users' populations and a variety of requirements in terms of bandwidths and Quality of Service (QoS), while maintaining the payload complexity affordable. In this frame, significant on-board digital processing is involved, which calls for careful system modeling and accurate digital hardware design to achieve feasible trade-offs between hardware efficiency and overall link-budget performance. In these regard, an equivalent noise model for the analog-digital hybrid receiving chain that composes the satellite transparent transponder has been proposed in our recent works. In the present paper the theoretical framework is extended in order to take into account the actual hardware resource utilization and the related power consumption for a given Field Programmable Gate Array (FPGA) technology.