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A stabilized multi-channel CMOS time-to-digital converter based on a low frequency reference

The aim of this work was to improve the performance and usability of a digital time-to-digital converter (TDC) in CMOS technology. The characteristics of the TDC were improved especially for the needs of pulsed laser time-of-flight (TOF) distance measurement, where picosecond-level precision with a long μs-level measurement range is needed in order to approach mm-level measurement accuracy. Stability in the face of process, voltage and temperature variations, multiple measurement channels, alternative measurement modes, a high integration level, standard interfaces and simple usage were the main features for development. The measurement architecture is based on counter and timing signal interpolation on two levels. The counter counts the full reference clock cycles between the timing signals, while a new recycling delay line developed in this thesis interpolates within the reference clock cycle. This technique utilizes a short delay line several times per reference clock cycle, which minimizes the interpolation nonlinearity. The same structure also makes the use of a low, MHz-level reference frequency possible, and thus only a crystal is needed as an external oscillator component. The parallel load capacitor-scaled delay line structure acts as the second, sub-gate-delay interpolation level. The INL does not accumulate in elements connected in parallel, and the load capacitance differences enable high, ps-level resolution to be achieved. Four TDC circuits in 0.35 μm CMOS technology were designed and tested in the course of this work, of which the latest, a 7-channel TDC, is able to measure the time intervals between the start pulse and three separate stop pulses in one measurement and to resolve the pulse widths or rise times at the same time. In laser TOF distance measurement this functionality can be used when several echoes arrive at the receiver, and also to compensate for the detection threshold problem known as timing walk error. The TDC achieves 8.9 ps interpolation resolution within the cycle time of a 20 MHz reference clock using only 8 delay elements on the first interpolation level and 14 delay elements on the second. A measurement precision better than 9 ps was achieved without using result post-processing or look-up tables. This work shows that versatile, high performance TDCs can be created in standard CMOS technology.