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Efficient architecture for hierarchical bidirectional motion estimation in frame rate up-conversion applications

Bidirectional motion estimation is an efficient algorithm which can solve the problem of holed and overlapped regions for motion compensated frame interpolation in frame rate up-conversion applications. This paper proposed an efficient VLSI architecture for this algorithm using multi-resolution frames to reduce the hardware resource. The initial motion vectors (MVs) in bidirectional motion estimation are obtained by full-search motion estimation algorithm at the lowest resolution frames. Then, the MVs are refined in small local search in the upper-resolution frames. The buffer is implemented to store the search data of two down-sampled levels. The proposed architecture is synthesized with about 25K gates and 1440 bytes internal memory for the search range of [-16, 16].