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Dynamic in-chip current distribution simulation technology for power device layout design

This paper reports an in-chip current distribution verification technology for power devices that takes into account the effect of layout parasitics. The proposed method enables verification of dynamic current distribution in a chip considering the influence of layout parasitics from the initial stage of device development by brushing up each element technology of TCAD, Spice model, and layout parasitic extraction technology for power devices and linking them seamlessly. We report that this method was applied to the layout optimization of our 8th generation IGBTs, and the in-chip current variation could be reduced by about 50% compared to the conventional layout structure.