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Design methodology of single-flux-quantum flip-flops composed of both 0- and π-shifted Josephson junctions

A methodology for designing single-flux-quantum (SFQ) flip-flops composed of both conventional (0-) and π-shifted Josephson junctions is investigated. We investigated the implementation of a storage loop, which can store flux quantum and is indispensable to express binary logic states in superconductor logic circuits. As all SFQ flip-flops have storage loops, the investigated design methodology can be applied to their design. We designed several SFQ flip-flops composed of 0- and π-shifted Josephson junctions using the investigated design methodology. The performances of the designed SFQ flip-flops were quantitatively evaluated by using an analog circuit simulator which we developed. We confirmed the correct operation of various SFQ flip-flops composed of 0- and π-shifted Josephson junctions with wide operating margins. Moreover, we observed that the investigated design methodology is suitable for SFQ flip-flops with complementary outputs because a storage loop composed of both 0- and π-shifted Josephson junctions has a symmetric structure and the complementary output function can be realized by using the storage loop. Our investigation indicates that the number of Josephson junctions and static power consumption of a non-destructive read-out flip-flop with complementary outputs (NDROC) can be reduced to less than half of those of the conventional NDROC, which has two storage loops composed of 0-Josephson junctions, to realize the complementary output function. The investigated design methodology is expected to be applied to not only SFQ circuits but also other superconducting logic circuits and novel reconfigurable logic devices using programmable 0-π Josephson junctions.


Introduction
As the end of Moore's law approaches, beyond-CMOS (complementary metal-oxide-semiconductor) devices have been attracting attention [1,2]. Such devices can overcome the physical limitations of semiconductor CMOS devices.
Superconducting logic devices are one of these candidates, owing to their high operation speed and extremely high energy efficiency [3][4][5][6].
A conventional Josephson junction (0-JJ herein) [7,8], where the flowing superconducting current is related to the phase difference between two superconducting electrodes comprising the 0-JJ, is the most fundamental element of superconducting circuits such as a single-flux-quantum (SFQ) circuit [9,10], quantum flux parametron [11,12], and reciprocal quantum logic circuit [13]. To improve the performances of superconducting circuits, the introduction of πshifted JJs (π-JJs) into superconducting circuits has been investigated [14,15]. The current-phase relationship of a π-JJ is expressed as where I is the current, I C is the critical current of the π-JJ, and θ is the gauge-invariant superconducting phase difference between the two superconducting electrodes of the π-JJ. Superconducting loops that contain 0-JJs are used to express the binary logic states of a superconducting circuit. In the case of conventional SFQ flip-flops, the existence and absence of flux quantum in the superconducting loop, called a storage loop, represents the internal logic states of the flipflops. The bias current is asymmetrically injected into the storage loop to realize the bistable energy potential of the storage loop, which is indispensable to the implementation of SFQ flip-flops [16].
In contrast, bistable energy potential can be realized using a superconducting loop containing a π-JJ without applying bias current to the loop [16]. Consequently, the static power consumption of the SFQ circuit can be reduced by introducing π-JJs into the circuits [15][16][17][18]. Furthermore, we can implement dense superconducting circuits by using π-JJs because the large inductance required by the storage loop can be replaced with a π-JJ, which has an intrinsic π phase shift [17,19]. A superconducting quantum interference device composed of π-JJs can also be utilized as a superconducting flux quantum bit that does not require magnetic flux bias [20][21][22].
Among various superconducting SFQ flip-flops, only a toggle flip-flop (TFF) has been investigated and implemented by using π-JJs so far [15,16,18]. This is because a TFF has a simple circuit structure and is suitable for circuit implementation and demonstration. However, the method of designing SFQ flip-flops using π-JJs and the question of whether the performance of flip-flops can be improved by introducing π-JJs are not clear.
In this study, we investigated a circuit design methodology for designing SFQ flip-flops by considering the implementation method of a storage loop, which can store flux quantum and is indispensable for the implementation of SFQ flip-flops, by using π-JJs. We designed several SFQ flipflops composed of 0-and π-JJs based on the investigated design methodology. To simulate and quantitatively evaluate the designed SFQ flop-flops, we developed an analog circuit simulator that can simulate the operation of superconducting circuits composed of both 0-JJs and π-JJs. The performances of the designed SFQ flip-flops composed of 0-JJs and π-JJs were quantitatively evaluated by using the developed analog circuit simulator. The circuit performances of the designed flip-flops were compared with those of the conventional SFQ flip-flops.

Analysis of storage loop containing π-JJs
We investigated the implementation method of a storage loop composed of 0-JJs and π-JJs to design SFQ flip-flops using π-JJs. Figure 1 shows the simplified equivalent circuits of a storage loop in the conventional SFQ flip-flop composed of two 0-JJs. To simplify the discussion, the critical currents of the two JJs in the storage loop are assumed to be the same, i.e., I C . The inductance of the storage loop L S is large so that the loop can store the flux quantum. The bias current I b is asymmetrically supplied to realize the bistable energy potential of the storage loop [16]. I 1 and I 2 are the currents flowing through J 1 and J 2 , respectively, when the internal state of the storage loop is '1' where one flux quantum is stored in the storage loop. According to Kirchhoff's law, the following relationship is satisfied: In the '1' state, as one flux quantum is stored in the storage loop, the phase difference across the path C shown in figure 1(a) is 2π. Therefore, the following equation should be satisfied: 2 , where θ 1 , θ L , and θ 2 are the phase differences across J 1 , L S , and J 2 , respectively. The phase difference across each device is expressed as where Φ 0 is the flux quantum. It should be noted that this discussion is valid only for the steady state analysis because junctions' capacitances are not considered. By substituting equations (4), (5) and (6) into (3), the relationship between the inductance of the storage loop L S and the current flowing through the storage loop can be obtained as where I=I 2 /I C and i=I b / I C . To store the flux quantum in the storage loop, I should be less than 1. Equation (7) expresses the relationship between the inductance required to implement the storage loop and the current flowing through J 2 when the internal state of the storage loop is '1'. Figure 2 shows the simplified equivalent circuits of a storage loop composed of a π-JJ, P 1 , and a 0-JJ, J 2 (π-storage loop). P 1 and J 2 have the same critical current I C . In the πstorage loop, the binary states are represented by the direction of half-flux quantum (0.5Φ 0 ) threading the π-storage loop. The bias injection is removed because the bistable potential can be achieved without the current bias [16]. Therefore, the current flowing through both P 1 and J 2 has the same value I 2 .
Owing to the intrinsic π-phase shift in π-JJ P 1 , the phase difference along the π-storage loop in its '1' state is expressed as where , 1 L q q ¢ ¢ , and 2 q ¢ are the phase differences across P 1 , L S , and J 2 , respectively. As the current flowing through both P 1 and J 2 is the same, is satisfied. The phase differences across P 1 and J 2 are expressed as respectively. By substituting equations (9), (10) and (11) into (8), we obtain the following relationship: where I=I 2 /I C . '0' and '1' sates of the π-storage loop correspond to states where the normalized circulating current ±I is flowing in the loop. Equation (12) shows the relationship between the inductance required for the implementation of the π-storage loop and the current flowing through J 2 when one flux quantum is stored in the storage loop. By using equations (7) and (12) we can derive the inductance required to implement the storage loop and πstorage loop as a function of I. In order to hold one flux quantum in the storage loop, I should be less than 1. Figure 3 shows the dependence of the required storage loop inductance on the current flowing through J 2 for both the conventional SFQ circuit implementation (assuming i=0.5) and the π-JJ implementation. As shown in figure 3, the inductance of the π-storage loop is approximately half that of the conventional storage loop. Therefore, the circuit area required for implementing the storage loop is expected to be reduced by introducing π-JJs. As the π-storage loop does not require the injection of bias current, it consumes no static power.
However, assuming that the π-storage loop is directly connected to the conventional SFQ circuit, the intrinsic phase  shift of the π-JJ affects the operation of the SFQ circuit. To connect the SFQ circuit and π-storage loop without modifying the former, we devised the insertion of an additional π-JJ between them. Figure 4 shows the devised interface part between the SFQ circuit and the π-storage loop. An additional π-JJ P 2 is inserted to cancel the phase shift by P 1 , and thus, the SFQ circuit can be directly connected to the π-storage loop. P 2 can also be used as an escape junction that cancels the successive data input. By using the devised interface, we can build SFQ flip-flops by replacing the storage loop with the π-storage loop, inserting the π-JJ, and removing the bias current injected to the storage loop.
As superconducting circuits other than the SFQ circuit require superconducting loops to store flux quantum, the investigated π-storage loop and its interface with the conventional superconducting circuit are expected to be applied to other superconducting circuits.

Development of simulator for circuits containing π-JJs
To evaluate the characteristics of the superconducting circuits composed of 0-JJs and π-JJs, we developed an analog circuit simulator by modifying JSIM [31], which was developed in 1989 and has been widely used [32]. The JSIM employs the modified nodal analysis (MNA) method to represent the circuit equation including characteristics of 0-JJs in matrix form [31]. We added a new function that builds the matrix (called MNA stamp) in the circuit equation of the π-JJ, the characteristic of which obeys the current-phase relationship represented by equation (1). The matrix size of the MNA stamp of the π-JJ is 3×3, which is the same as that of the 0-JJ. Therefore, the calculation time and the computation resources required for the simulation of the π-JJ are the same as those of the 0-JJ. The MNA stamp of the circuit under simulation, the connection and circuit parameters of which are described in the netlist, is updated by the functions corresponding to each circuit component including the π-JJ. Calculation results are obtained by numerically solving the differential equations of the MNA and are output every calculation step. We added and modified functions for netlist input, updating the MNA stamp, and calculation result output. In total, we added 10 functions and modified 21 functions. The developed circuit simulator can also perform a transient analysis taking thermal noises at the finite temperature into account by employing the noise model implementation by Satchell [33].
In order to confirm validity of the simulation results by the developed analog circuit simulator, we calculated the maximum current characteristic of a dc-SQUID composed of a 0-JJ and a π-JJ (π-dc-SQUID) and compared it to that of a dc-SQUID composed of two 0-JJs. Figure 5 shows the equivalent circuit of the π-dc-SQUID and an example of the corresponding netlist. As shown in figure 5(b), if the case that the initial character of the device name is 'P' or 'p', the simulator recognizes the corresponding device as the π-JJ. In this simulation, the junction characteristics of both the 0-JJ and the π-JJ, which are described in the netlist, are assumed to be the same as that of the junction fabricated by the National Institute of Advanced Industrial Science and Technology (AIST) 2.5 kA cm −2 Nb standard process 2 (AIST-STP2) [34,35]. In the simulation, the ramped current I b with the rise rate of 100 μA ns −1 was applied to the π-dc-SQUID. The maximum current was obtained by measuring the applied current value when the π-dc-SQUID switches to the finite voltage state. The magnetic flux was applied to the π-dc-SQUID by applying the dc-current to the inductors L 1 and L 2 shown in figure 5. Figure 6 shows the calculated dependence   circuit and (b) an example of the netlist of a dc-SQUID composed of a 0-JJ and a π-JJ. The circuit symbol of P 1 corresponds to the π-JJ [36]. J 1 and P 1 are device names of the 0-JJ and the π-JJ, respectively. The critical current of J 1 and P 1 is 100 μA. 'fcheck' is needed to describe inductors in the netlist [37]. of the maximum current on the externally applied magnetic flux. The threshold characteristic of the dc-SQUID, composed of two 0-JJs, is also shown in figure 6. The threshold characteristic of the π-dc-SQUID shows the periodicity shifted by half a period compared to that of the dc-SQUID. This result indicates that the characteristic of the superconducting circuit containing π-JJ can be precisely simulated by the analog circuit simulator we developed.
The developed analog circuit simulator, which we call PJSIM, is advantageous to design and analyze large-scale superconducting circuit composed of both 0-JJs and π-JJs compared to the conventional simulation method that uses an equivalent circuit model, which is composed of an inductance and a current source, and can imitate π-phase shift in the superconducting circuit [38]. We used the analog circuit PJSIM to quantitatively evaluate the characteristics of the superconducting circuits composed of both 0-JJs and π-JJs mentioned in the following section. We are planning to make PJSIM available for the public in the near future.

SFQ flip-flops containing π-JJs
We designed several SFQ flip-flops based on the design methodology discussed in section 2. Figure 7 shows the equivalent circuit of a delay flip-flop with an escape junction (DFFE) implemented by using a π-storage loop (π-DFFE). The π-DFFE was designed by modifying the DFFE cell in the CONNECT cell library [39]. The storage loop of the DFFE cell with an asymmetric bias supply is replaced by the π-storage loop and the escape junction for data input (din) is replaced by P 7 . At the standard bias voltage of 2.5 mV, the static power consumption of the π-DFFE is 1.50 μW, whereas the original DFFE cell from the CONNECT cell library has a static power consumption of 1.72 μW. The inductance in the π-storage loop (L 3 ) is 5.500 pH, which is much smaller than the typical inductance of a conventional storage loop.
As the conventional SFQ circuits can be directly connected to the π-storage loop owing to P 7 , the π-DFFE is compatible with any cells in the CONNECT cell library. We simulated the π-DFFE by connecting three Josephson transmission line cells in the CONNECT cell library in front of and behind the π-DFFE. Figure 8 shows an example of the result of simulated transient analysis of the π-DFFE by using the PJSIM discussed in section 3. In this simulation, the junction characteristics of both the 0-JJ and the π-JJ, critical current density, normal and sub-gap resistances, and junction capacitance are assumed to be the same as those of the 0-JJ fabricated by the AIST-STP2 [34,35]. Because the current flowing in P 7 is larger than that in P 3 when the π-DFFE is in '1' state, P 7 acts as the escape junction for data input (din), and thus, the successive 'din' input is canceled. The simulated dc bias margin of the π-DFFE is −31.6% to 45.2%. Although the circuit parameters of the π-DFFE were not optimized well, a wide bias margin of±30% could be obtained. We also evaluated the circuit parameter margin of all circuit elements of π-DFFE using PJSIM. The critical device, which has the narrowest parameter margin, is J 1 and the margin is −23.0% to 23.5%. Similarly, we designed the AND gate and the nondestructive read-out flip-flop (NDRO) and confirmed the correct operation of the circuits with dc bias margins of more than±25%.
The π-storage loop has a symmetric circuit structure and logic representation according to the direction of half-flux quantum. By using the symmetry of the π-storage loop, SFQ flip-flops with complementary outputs, such as the NDRO with complementary output (NDROC), can be designed efficiently. The NDROC is widely used in a binary decoder [40][41][42], dual-rail SFQ circuits [43][44][45][46], etc. However, the NDROC with a complex complementary function is one of the largest SFQ flip-flops and the delay of the NDROC is larger than that of other flip-flops. In the conventional NDROC, two storage loops are used to realize the complementary output function. The number of 0-JJs of the NDROC cell in the CONNECT cell library is 33. Figure 9 shows the equivalent circuit of the NDROC implemented by using π-JJs (π-NDROC). The loop composed of P 8 , L 9 , L 12 , L 10 , and J 9 in figure 9 is the π-storage loop. The π-NDROC is designed using only one π-storage loop and has a symmetric circuit structure with an axis of Figure 7. Equivalent circuit of the π-DFFE. 'din', 'clk', and 'dout' correspond to data input, clock, data output ports, respectively. The critical current values of the 0-JJs and π-JJs are as follows: J 1 =230 μA, J 2 =216 μA, P 3 =140 μA, J 4 =150 μA, J 5 =216 μA, J 6 =228 μA, and P 7 =170 μA. L 1 =2.457 pH, L 2 =2.500 pH, L 3 =5.500 pH, L 4 =4.690 pH, L 5 =2.457 pH, L 6 =3.400 pH, L 7 =2.421 pH, and R 1 =R 2 =8.34 Ω. The bias voltage V b is 2.5 mV. symmetry expressed by the horizontal dashed line in figure 9. This π-storage loop is not only structurally but also logically symmetric because P 6 and P 8 are π-JJs whereas J 7 and J 9 are 0-JJ. When the clock (clk) signal is supplied to the π-storage loop, the output is obtained from either 'dout' or 'doutc' ports according to the direction of the half-flux quantum in the π-storage loop. As the internal logic state of the π-storage loop, which corresponds to the direction of half-flux quantum in the π-storage loop, can be changed by applying 'din' and 'reset' signals, the function of NDROC can be obtained. The number of JJs, including π-JJ, used in the π-NDROC is 15. The static power consumption of the π-NDROC is 2.25 μW, whereas that of the NDROC cell in the CONNECT cell library is 8.56 μW. Figure 10 shows the simulation result of the π-NDROC. The correct complementary output signals are obtained from the 'dout' and 'douc' ports. The simulated dc bias margin of the π-NDROC is −18.4% to 42.4%. The critical devices are J 4 and J 5 and the parameter margin is −20.5% to 21.5%. The latency of the π-NDROC is also reduced compared with that of the NDROC cell.

Conclusion
We investigated a design methodology of SFQ flip-flops composed of both 0-JJs and π-shifted JJs. The investigated design method enables us to design SFQ flip-flops by using a storage loop containing π-JJs. Moreover, the design methodology is suitable for implementing SFQ logic gates with complementary outputs owing to the symmetric circuit structure and logic state representation. We could drastically reduce the number of JJs and the power consumption of the flip-flops with complementary outputs by introducing π-JJs. We developed an analog circuit simulator for the superconducting circuits containing π-JJs. We confirmed the correct operation of SFQ flip-flops composed of 0-JJs and π-JJs with wide operation margins. The developed design methodology and analog circuit simulators are helpful for designing future large-scale superconducting circuits containing π-JJs and reconfigurable logic circuits composed of programmable 0-π JJs. Figure 9. Equivalent circuit of the π-NDROC. The critical current values of the 0-JJs and π-JJs are as follows: J 1 =J 2 =J 3 =215 μA, J 4 =J 5 =205 μA, P 6 =J 7 =230 μA, P 8 =J 9 =140 μA, P 10 = J 11 =120 μA, J 12 =J 13 =100 μA, and J 14 =J 15 =203 μA. L 1 =L 2 =L 3 =2.457 pH. L 4 =1.500 pH, L 5 =5.500 pH, L 6 = L 11 =L 13 =0.500 pH, L 7 L 8 =L 9 =L 10 =0.500 pH, L 14 =L 15 = 5.486 pH. R 1 =R 2 =R 3 =8.34 Ω. The bias voltage V b is 2.5 mV.