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Hardware architectures for real time processing of High Definition video sequences

Actually, application fields, such as medicine, space exploration, surveillance, authentication, HDTV, and automated industry inspection, require capturing, storing and processing continuous streams of video data. Consequently, different process techniques (video enhancement, segmentation, object detection, or video compression, as examples) are involved in these applications. Such techniques often require a significant number of operations depending on the algorithm complexity and the video resolution, which make impossible a time efficient software implementation.
The actual demand, driven by the consumer electronics market, of lightweight and high performance portable systems capable of processing high definition (HD) video sequences in real-time is therefore mainly targeted through the use of integrated digital electronic systems.
Very high performance can be obtained by using full custom ASIC implementations. However, the complexity and the cost associated with ASIC design is significant. Moreover, ASIC implementations are not reconfigurable and require a long design time. For these reasons, Field Programmable Gate Array (FPGA) devices are more and more being chosen as target technology for the hardware acceleration.
In this dissertation, several hardware architectures for real-time video processing of HD video sequences are proposed.
The circuits are designed by using Hardware Description Languages (HDL) and the target technologies for the implementation are mainly FPGA devices. Area utilization, maximum working frequency, and power dissipation are also computed and analyzed for all the described architectures and several experiments are carried out to test the circuits characteristics.
The comparison with previously proposed works shows that circuits performance overcome the state-of-the-art architectures, highlighting the effectiveness of the proposed solutions.