{'fraction_non_alphanumeric': 0.019693654266958426, 'fraction_numerical': 0.0, 'mean_word_length': 5.1891891891891895, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
The design and simulation of the PACE prototype architecture

We present a case study of the use of a Unix/C/Verilog production environment to aid the design, from concept to physical prototype, of the PACE parallel graph rewriting architecture. The entire architecture has been modelled, so that simulated runs of complete programs are possible. The architecture's model is currently being refined towards a component by component detailed hardware design.