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Design and implementation of offset system for video image based on FPGA technology

In this dissertation, the imbedded system of video capture, storage, processing and offset output system. The data collected by the camera first goes through A/D chip and realize the configuration of video decoding chip-ADV7181B through 12C bus protocol. It then decode the video data stream, extract Y gray component in the valid video and use the ping-pang cache technology to realize seamless buffering of the data through ram. After de-interlacing, the processed video data is output line by line and stored in sram. Finally it goes into VGA control module after the change of address and realizes the offset output of image on the screen. This system has been realized on EP3C25 in Cyclone III series of Altera Company, which has proved to be steady, easily-extensible and low-cost.