{'fraction_non_alphanumeric': 0.019622093023255814, 'fraction_numerical': 0.002180232558139535, 'mean_word_length': 5.287671232876712, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Rethinking Last-Level Cache Management for Multicores Operating at Near-Threshold Voltages

Near-threshold voltage computing promises an order of magnitude improvement in energy efficiency, enabling future processors to integrate 100s of cores running concurrently. However, such low voltage operation accompanies extreme parametric variations, resulting in unreliable operation of the processor. The memory bit-cells in on-chip caches are most vulnerable to failure due to their tight functionality margins. In this paper we focus on the NTV challenges with the last-level cache (LLC) management for future multicores. The state-of-the-art mechanisms enable a hybrid of disabling faulty cache lines and error correction capabilities to maximize the usable cache capacity in the LLC. We postulate that future technologies will suffer from extreme fault rates and some portions of the LLC need to be disabled. This will put unprecedented stress on the LLC capacity impacting the existing management schemes for placement, movement and replication of data. We focus our attention on evaluating the state-of-the-art LLC data management schemes and observe that a scheme optimized for nominal voltage operation may not necessarily perform optimally at NTV. We show that LLC data management schemes must be rethought and redesigned for the emerging energy efficient NTV multicores.