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Defect detection methodology on the back-end process: a case study

The manufacturing yield improvement comes mainly from back end process defects which unfortunately are difficult to detect: the topography on back end layers shows significant differences in height between the upper and lower levels, and even when planarization techniques are used the difference in thickness on dielectric layers leads to difficult optical detection. The W selective process step is an attractive way to make the vertical interconnections for integrated circuit fabrication. For the most advanced processes more than five metal levels separated by insulated layers are connected by vias buried in the silicon dioxide and filled with metal. The W selective process is an alternative to the W etched back process. This method seems to be economic as the removal of the metal layer is avoided. However, the chemical process of the selective W deposition between the silicon oxide and metal is very sensitive to any chemical perturbation or physical modification on the surface. Moreover, the deposition of the metal on the metal layer can be blocked. For all these reasons, studies on the cleanliness and physical properties (scratches on the dielectric for example . . .) are important for understanding the phenomena and thus correcting the process. The defects resulting from the tungsten selective deposition are little spheres which must be detected from 0.15 micrometer to cope with 0.4 micrometer design rules. The number and size of these particles, named nuclei, must be measured to qualify this process. The dark-field pixel-to-pixel optical inspection tool has been chosen to detect these nuclei. The electrical yield prediction based on the nuclei size distribution completes the study and saves time by avoiding final electrical test results.