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Statistical Modeling and Simulation for DAC Design

A Monte-Carlo approach has been applied to the estimation of yield of CMOS Digital-to-Analog Converter circuits as a design optimization tool. Parasitic circuit elements are included. A components of variance model is used to describe the multilevel variability of the resistors. The dependence of yield on the nominal values and the variances of circuit parameters has been examined. Test structures have been fabricated to investigate further the statistical distributions of DAC circuit elements.