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A multicasting ATM switch architecture

An architecture for Asynchronous Transfer Mode (ATM) switching with an aggregate capacity approaching 10 Gb/s and 160 Gb/s for the entire switching fabric is described in this paper. The architecture provides a minimum delay variation for each packet in a multicast stream. The entire system is designed from the ground up to allow for a growable network with an emphasis on simplicity and modularity. The switching nodes have 16 inputs and 16 outputs and, to facilitate the scalability of the switching fabric, the nodes both utilize and generate backpressure flow-control information for switching element neighbors. Full ATM line speed is retained at 622 Mb/s.