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Temperature-dependent hysteresis in black phosphorus FETs

Black phosphorus, also known as phosphorene in the few layer limit, is an almost unexplored “beyond graphene” material which is now considered a promising candidate for next-generation 2D FETs with good Ion/Ioff ratios [1-4]. One issue that has not been explored in detail yet is the hysteresis in the Id-Vg characteristics, which can severely limit the usability of these devices. Here we examine the hysteresis of back-gated black phosphorus FETs with SiO2 gate insulator and Al2O3 encapsulation [4]. We measure the Id-Vg characteristics of our devices using different sweep rates S = Vstep/tstep at different temperatures and monitor variations of the hysteresis width ∆V which is proportional to the charged trap density shift ∆NT. As shown in Fig. 1, the Id-Vg curves contain electron and hole conduction regions with the Dirac point in between. Each of these regions exhibits some hysteresis, which becomes more pronounced at higher temperatures and for lower sweep rates. Fig. 2(left) shows the dependence of ∆V vs. S extracted closely to Vth at four different temperatures. Clearly, slower traps are frozen out at -193 o C and become dominant at 165 o C. This means that charge trapping at the black phosphorus/SiO2 interface is thermally activated, similarly to Si technologies [5]. As shown in Fig. 2(right), at higher temperature the number of charged traps increases within the whole range of gate voltages. Since the typical ∆NT values in black phosphorus FETs are considerably larger than in their Si counterparts, we conclude that further efforts are needed to make this technology competitive.