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A Gate Level Analysis of Transient Faults Effects on Dual-Core Chip-Multi Processors

With continuous scaling in CMOS technology the number of transistors grows more and more in a single chip and it makes modern processors prone to the risk of transient fault. In this work the effects of transient faults in MIPS-based Chip-Multi Processors (CMPs) are investigated in two phases. In the first phase a low level fault injection is performed and sensitive components is determined. In the next phase, in order to improve the reliability term in CMPs, two simple low overhead fault tolerant techniques are employed on the most vulnerable components in the MIPS-based dual-core processor. Hsiao code was used which is an optimal minimum odd-weight-column single error correction and double error detection SEC-DED code to protect MPI and program counters. TMR (Triple Modular Redundancy) technique is used to improve reliability of the Arbiter. Using fault injection improves 12.8% in error recovery and 16.6% reduction of failure rate with negligible performance overhead.