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Latchup in CMOS

Latchup is a failure mode in CMOS circuits that results in either soft failures with a loss of data or logic state, or in extreme cases, a destructive hard failure and permanent loss of the circuit. As isolation widths shrink, device structures become ever more susceptible to both failure modes, unless steps are taken to improve latchup robustness. The rapid proliferation of multiple power supply voltages and system-on-chip designs also exacerbate the problem. Prevention of both transient and destructive failures is of utmost importance in advanced CMOS designs. CMOS technologies have largely converged on p-bulk substrates. Reducing the CMOS power supply voltage is a potential solution for hard latchup failures, but not soft ones. This paper presents characterizations of latchup obtained by process and device modeling. Introducing a low resistance shunt layer by ion implantation is shown to be the most effective method for preventing all types of latchup failures.