{'fraction_non_alphanumeric': 0.020928116469517744, 'fraction_numerical': 0.0009099181073703367, 'mean_word_length': 5.111111111111111, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 1, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Accurate TDDB Lifetime Prediction Based on Intrinsic CiDSR Effect Model with Regarding Extrinsic Failures

The Charging-induced Dynamic Stress Relaxation (CiDSR) effect model has been expanded to be affordable of explaining (i) the situation both intrinsic and extrinsic failure modes coexist and (ii) the thinner region of gate dielectrics. This is because the CiDSR effect model was originally proposed to explain anomalous Weibull distortion and various anomalous TDDB statistics of intrinsic mode observed in thick gate dielectrics (> ~4 nm). The dynamic carrier charging to initial and generated traps does occur and affects the TDDB reliability to some extent also in relatively thin film region, but no clear distortion of Weibull of TBD is observed, resulting in less attention to the charging. The study on the TDDB lifetimes and statistics of samples with various STI and gate electrode edge perimeters in this work has demonstrated the validity of the CiDSR effect and revealed the key for above (i) and (ii). Thus, the CiDSR effect must be more taken into account in thinner film region.