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Power optimization and stage op-amp linearity relaxation in pipeline ADCs with digital comparator offset calibration

This paper presents a power optimization technique for Pipeline ADCs using digital background calibration of comparator offsets as an extra design variable. Thanks to calibration, comparator offset errors above half the stage least-significant bit (LSB) margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax the power consumption of stage amplifiers within the Pipeline queue, since output swing and driving capability are significantly lower. The proposal was validated using realistic hardware-behavioral models and transistor-level simulations. A 1.8V 15-bit 74dB-SNDR 100Msps Pipeline ADC was used as a demonstrator. Thanks to comparator calibration, the total power of stage subADCs was reduced by 75%, while a factor of 19% was found in stage amplifiers.