{'fraction_non_alphanumeric': 0.03294573643410853, 'fraction_numerical': 0.022286821705426358, 'mean_word_length': 4.644808743169399, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Ultra-low-power front-end CMOS true logarithmic amplifier for biopotential signal acquisition applications

An ultra-low-power logarithmic amplifier is presented in order to use in the front-end of preconditioning stages of bio-potential and neural recording microsystems. In such applications, low-power and low-noise performance is very challenging and important. The proposed true logarithmic amplifier, designed by making use of the piece-wise linear approximation and based on the parallel summation topology, includes five low-power limiting amplifiers. In this amplifier, the DC offset removal mechanism applies a low-pass filter in the feedback loop to reject the input offset. This amplifier has been simulated in a 0.18 μm CMOS technology. The simulation results demonstrate a CMRR of 134.7 dB at 50/60 Hz and an input referred noise of 2.53 μVrms in a bandwidth of 0.1-10 kHz. To reduce the power consumption, all transistors are biased in sub-threshold region. The power consumption is 3.72 μW from a 1.2 V power supply.