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Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits

VLSI circuits are becoming increasingly susceptible to radiation-induced "single event upset (SEU)". This paper focuses on one type of SEU caused by particle strikes inside the combinational logics, called "single event transient (SET)". We study various factors affecting SET effects in CMOS digital circuits and present a static method of analyzing the circuit's SET tolerance. We also propose a heuristic cell resizing process to effectively improve the circuit SET tolerance with limited design overhead. Experimental results have shown that our analysis can accurately evaluate SET effects and the cell resizing process is able to significantly reduce the probability of SETs becoming stable errors with no timing cost and negligible area penalty