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Slow Current-Drift Mechanism in n-Channel Inversion Type InP-MISFET

The current drift mechanism inherent in n-channel inversion type InP-MISFET's were investigated. From comparison of drift behavior of InP-MISFET with that of Si-MISFET (fabricated in the same manner as that of InP-MISFET) and measurement of its temperature dependence, it was found that the drift originated from electron trappings, and the trapping centers located in the CVD-Al2O3 gate insulator and in the InP native oxide surface layer. Because of higher concentration of trapping centers (one order of magnitude higher than that of Al2O3 insulator), the InP native oxide served as the main cause of the observed current drift. The trap level and concentration in the native oxide were estimated to be ∼38 meV above Fermi level and 1.5×1017/cm3, respectively.