{'fraction_non_alphanumeric': 0.01889763779527559, 'fraction_numerical': 0.0, 'mean_word_length': 5.838709677419355, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design and Performance Evaluation of a NoC-Based Router Architecture for MPSoC

NOC is an approach in designing communication subsystems between intelligent property (IP) cores in SOC with greater efficiency. Packet switched network are being proposed as global communication architecture for future soc designs and implementation. For effective global on-chip communication, on-chip routers provide expected routing functionality with low complexity and better performance. This paper provides Analytical Design and implementation of on-chip router architecture for MPSOC, which is the concept of high efficiency architectural design.