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Design of conventional three-stage CMOS comparator in 90-nm CMOS technology and comparative analysis with its counterparts

Comparators, as the name suggests, compare an analog signal with a reference signal, and outputs the signal in form of a binary signal. Dynamic comparators are widely employed, for their high speed. A comparator plays crucial role in the conversion of the analog signals to digital. This paper puts forth the design of the conventional three-stage comparator in 90-nm CMOS technology. The paper also provides a comparative analysis of the conventional comparator with the latch-based and hysteresis-based comparators. The circuit design and analysis has been done using Cadence.