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Design for computational storage simulation platform

Data movement between storage and compute resources represents a bottleneck in data-driven applications. This performance bottleneck can be mitigated by leveraging inherent parallelism in the user application and offloading component tasks, called compute kernels, for execution at the storage layer instead of on the host CPU. Performing computation on the storage device instead of moving the data through the memory hierarchy to the CPU cache provides opportunities for increased throughput and reduced energy consumption by exploiting data independence present in the application. Previous work in this domain requires either specialized hardware for each type of application, a restrictive set of operations executable on the storage device, or significant engineering effort to program the compute kernel offloaded to the device. While prior work has proposed accelerating certain compute tasks (e.g. encryption/decryption, compression/decompression) the application space has been very limited, because applications need to fulfill certain properties to be a good candidate. Currently there exists no way to figure this out. To extend the applicability of computational storage we propose a new simulator platform that enables large design space explorations for storage accelerators and applications. By reducing the cost of offload we can leverage more fine-grained compute kernels, increasing the applicability of computational storage. Researchers can use our simulator design to explore different approaches for accelerating applications, including different mechanisms for offloading compute tasks to the device and consuming results, different methods of interfacing between user applications and the device, and different device characteristics and capabilities. This system enables us to evaluate the scalability of compute offloading techniques without significant investment in hardware or engineering effort.