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Massive parallelization of SPICE device model evaluation on GPU-based SIMD architectures

Device model evaluation is one of the most time-consuming tasks in analog simulators such as SPICE. Graphics Processing Unit (GPU) architectures allow massive utilization of vector data on SIMD architectures. In this paper, the formulation of double precision device model equations into a form compatible with stream computing is presented. We show data on isolating typical bottlenecks, especially the communication and kernel call overheads. Our results indicate speedup of up to 20X when counting overheads, and up to 50X when using techniques to overcome these overheads. In particular, we show that our techniques are valid for small device counts, which is typically a well known problem for accelerated parallel computing with communications overheads.