{'fraction_non_alphanumeric': 0.045714285714285714, 'fraction_numerical': 0.040952380952380955, 'mean_word_length': 4.650537634408602, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A 1.25mW 0.8–28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS

This paper presents a wide-operating range analog phase locked loop (PLL) constructed from all-digital integrated circuit (IC) process components. Specifically, this work introduces 2 cutting-edge, scalable analog circuit designs for a charge pump (CP) and a voltage controlled oscillator (VCO). The ultra-low power and highly accurate CP circuit uses 6 minimum-sized transistors, a small metal interconnect capacitor, and, unlike the state-of-the-art, no current mirrors. The ring VCO has a reconfigurable, expandable structure and is capacitively tunable allowing for an exceptionally large frequency operating range of 0.8 to 28.2GHz making it suitable for variety of wireless and wireline applications. The PLL has been fabricated in a TSMC 40nm all-digital CMOS process and physically tested with a 0.5-1.2V supply. The fabricated PLL has an area of 0.0048mm2, consumes a maximum of 1.25mW, and has a 0.82 ±0.0275ps RMS jitter over the entire operating range.