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A decoupled access-execute architecture for reconfigurable accelerators

Mapping computational intensive applications on reconfigurable technology for acceleration requires two main implementation parts: (a) the data plane, i.e., efficient interconnected units that accelerate processing, and (b) the access-plane, i.e., efficient ways to access data and transfer them to/from the accelerator. Data plane construction is well understood and mature tools -such as High Level Synthesis (HLS)- that produce efficient reconfigurable architectures exist. The access plane, however, is more challenging: data fetching for big-data and high-performance computing applications is even more complex and time consuming than processing. Towards this end, we present DAER, a Decoupled Access-Execute architecture and framework for Reconfigurable accelerators. Our approach maps the code to be accelerated in two separate parts: (a) the fetch unit, responsible for fetching data to the accelerator and storing results back in memory, and (b) the processing unit, which processes the fetched data in a streaming way. This approach offers the user a structured and well-defined way of mapping applications on an FPGA. Additionally, it bodes well with other hardware-based optimization techniques, e.g. pipelining, custom processing and data prefetching, which hide the memory data access latency. We use the DAER framework and HLS mapping tools on five applications and show the proposed DAER framework achieves an order of magnitude performance speed-up compared to unmodified applications, and as much as 2x performance improvement compared to their optimized HLS versions. We, also, map the DAER-based architectures on HPC platforms showing the performance advantages of our approach on real world platforms.