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Modeling and implementation of CPPLL

Based on the model of SMIC 0.13 mixed-signal process and its supply voltage is 3.3 V, a Charge Pump Phase-Locked Loop is designed in this paper. The Verilog-A language is applied to build the behavioral modeling for the Charge Pump Phase-Locked Loop, in the bias circuit of Charge Pump a voltage regulation NMOS is added to reduce the charging and discharging current mismatch to less than 0.073%, and the design parameters of the Loop Low-Pass Filter is given in this paper. The Cadence simulation results show that the frequency of the input of the Charge Pump Phase-Locked Loop is 3~160MHz, and the output frequency is 3~400MHz; the maximum division number is 32 and the lock time is less than 22us.