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Design of a compact fault tolerant adder/subtractor circuits using parity preserving reversible gates

Reversible logic has drawn great attention in recent years due to its emerging propagation in diverse range of areas. In this paper, we present a novel approach to unite addition and subtraction operations; circuits that perform addition/subtraction operations using fault tolerant reversible gates with fault detection capability. Adder and subtractor are basic building blocks of any Arithmetic Logic Unit; in this manner we first present the concept of merging those two circuits into one logical block. Then we introduce all possible approaches to construct fault tolerant united addition-subtraction circuit for not only reducing the number of gate but also minimizing quantum cost and garbages of circuit at a meaningful level. We demonstrate three types of half-adder/subtractor circuits and four types of full-adder/subtractor circuits. Again, we depict an algorithm based on our novel concept and we also present simulations on our proposed circuits. Besides, the comparative analysis of our proposed compact method shows our proposed circuit outperform than existing circuit as highest improvements of proposed circuits are 33.33% for garbage output, 26.66% for quantum cost and 50% for gate count. Finally, overall significance of our proposed designs is presented in conclusion.