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Efficient FPGA implementation of multiplier-adder-quotient-remainder approach

Fast multiply-and-add is essential in signal processing, and DSPs usually feature this operation. The CPU+software implementation is, however, sometimes not sufficient, because increasingly more complex operations are required. Though a hardware solution can improve the situation, large circuit and/or long logic-synthesis time pose alternate problems. The authors propose a circuit configuration to enable the rapid development of a multiplier-adder with constant coefficients using FPGAs (field-programmable gate arrays). The quotient-remainder scheme based on the bit width division reduces the design time down to 1/5 or less.