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Improving the energy efficiency of coarse-grained reconfigurable arrays

Coarse-grained reconfigurable arrays (CCRAs) are a class of spatial accelerators that combine advantages from both FPGAs and VLIW processors to efficiently exploit the computationally-intensive inner loops of an application. This thesis systematically explores a region of the design space for CGRAs and identifies architectural features that can improve the architecture's overall energy efficiency, without sacrificing performance. Using the results from this exploration we developed the Mosaic CGRA, which is an energy-optimized architecture that can meet the industry's demand for dramatic improvements in energy-efficient computing, by boasting a 10× reduction in its area-delay-energy product versus a baseline architecture. 
We accomplish this improvement in energy efficiency by systematically isolating the impact of each architectural feature on both the architecture's physical characteristics and its runtime performance, rather than performing an ad-hoc exploration of the design space. As a result, the architect is able to compare the relative advantages of each feature and compose them more easily than has been traditionally possible with past architectural explorations. Not only does this evaluation provide the foundation of the Mosaic CGRA, but provides an infrastructure, and a reference design for future architecture development.