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Full-Chip Leakage Verification for Manufacturing Considering Process Variations

A novel compact model for subthreshold leakage (Isub) including its extraction scheme has been developed in this paper. Both quantum and stress effects have been covered in this model, and it accurately fits experiment data for both nMOSFETs and pMOSFETs. A study of subthreshold leakage variations (SLVs) for the 65 nm technology has been reported for the first time. Gate length (L) roughness and variations in Vth are found to account for most of the SLVs. With the proposed model, a statistical methodology has been developed to address the growing issue of full-chip leakage verification for actual- fabrication circuits.