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A robust SVM technique to minimize the effects of unbalanced voltage disturbances

Space vector modulation (SVM) is one of the most popular PWM techniques in the control methods of multilevel inverters. The assignment of the reference vector location is very important to obtain the exact switching times and to determine the correct space vectors in this techniques. The location of the reference vector is determined by utilizing the phase angle of the system. It can be obtained from Clarke Transformation for SVM technique or phase-locked loop (PLL) for other methods. The unbalanced disturbances occurred in the three-phase systems affect the switching times obtained by utilizing the phase angle. The output waveform of the multilevel inverters is affected as well. In this study, the effect of disturbances such as line to line faults, unbalanced voltage sags/swells are investigated on conventional SVM technique. In order to minimize these affects, a new technique based on Clarke Transformation is proposed and applied to the two-level inverter. PSCAD/EMTDC simulation program is used to apply the case studies and to take the simulation results.