{'fraction_non_alphanumeric': 0.013812154696132596, 'fraction_numerical': 0.0, 'mean_word_length': 5.470238095238095, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Scaling down channel dimensions in organic and polymer thin-film transistors: charge transport and device design considerations

Scaling down channel dimensions of organic and polymer semiconductor based thin-film transistors to submicron and nanoscale dimensions presents several challenges. Successful scaling will enable vastly improved device performance and hence the prospects are certainly very enticing. One of the biggest challenges is in making suitably good doped source and drain regions to facilitate relatively low-resistance contacts. A more thorough understanding of velocity saturation mechanisms and charge transport at high electric fields is also necessary. We describe charge transport in oxide and polymer TFTs with an emphasis on scaling. We show that for some TFTs, scaling of the channel width facilitates scaling down of channel length and a nanostripe or nanogroove array channel geometry has advantages. Finally, we describe hybrid TFTs – with multiple materials that are better suited to scaling down. The future prospects of scaled down TFTs are discussed.