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Comparative Analysis of Low Power 4-bit Multipliers Using 120 nm CMOS Technology

In the recent years growth of the portable electronics is forcing the designers to optimize the existing design for better performance. Multiplication is the most commonly used arithmetic operation in various applications like, DSP processor, math processor and in various scientific applications. Overall performance of these devices is strongly depends on the arithmetic circuits like multiplier. This paper presented detailed analysis of low power CMOS multiplier which is very important for today’s scientific application. Simulation results are presented at 120nm technology.