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Active devices and wiring under chip bond pads: stress simulations and modeling methodology

In the semiconductor industry, cost competitiveness can be significantly improved by maximizing the use of chip real estate. For wire-bonded chips, vacant space under the bond pads can be populated with active devices and wiring known as structures under pads (SUPs). Although this layout strategy can improve productivity, reliability issues concerning stresses from the wire-bonding loads must be resolved before population can occur. The necessary qualification work, including designing, building, and stressing test sites, can become very costly if it attempts to cover all possible SUP layouts. Mechanical simulations using finite element analysis (FEA) software can play a critical role in reducing the cycle time and qualification cost by predicting the wire-bonding stresses for different SUP layouts. Knowledge gained from FEA models can be used throughout the qualification process: early on to design the test site and later on to interpret the test results and bridge them to other technologies or die configurations. To achieve these time and cost savings, a set of simulations must be properly defined and interpreted. This paper discusses mechanical modeling performed in conjunction with an SUP qualification effort at IBM. We describe the modeling methodology as well as the effects of different layout variables on the stress distribution.