{'fraction_non_alphanumeric': 0.019801980198019802, 'fraction_numerical': 0.0039603960396039604, 'mean_word_length': 4.952941176470588, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A time-multiplexed FPGA architecture for logic emulation

This paper presents an architecture for a FPGA oriented towards logic emulation, to achieve maximum usable logic density per unit silicon area, and fast mapping. Logic circuits are translated into a program that is executed sequentially by a network of processor elements. Overall, a sevenfold increase in raw logic blocks, and a 25-fold increase in usable logic blocks compared to a FPGA-based logic emulator is expected for a given silicon area.