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Advanced bus-clamping PWM techniques based on space vector approach

Conventional space vector pulsewidth modulation (CSVPWM) employs conventional switching sequence, which divides the zero vector time equally between the two zero states in every subcycle. Existing bus-clamping PWM (BCPWM) techniques employ clamping sequences, which use only one zero state in a subcycle. This paper deals with a special type of switching sequences, termed here as “double-switching clamping sequences,” which use only one zero state and apply an active vector twice in a subcycle. The present work brings out a class of bus-clamping PWM techniques, which employ such sequences. It is shown analytically as well as experimentally that the proposed BCPWM techniques result in reduced harmonic distortion in the line currents over CSVPWM as well as existing BCPWM techniques at high modulation indices for a given average switching frequency of FSW. At high modulation indices, the dominant harmonic components in the line voltages are around 2 FSW with the proposed BCPWM techniques, while the dominant components are around FSW and 1.5 FSW, respectively, with CSVPWM and existing BCPWM techniques. The proposed techniques also reduce the inverter switching losses at high power factors over CSVPWM and existing BCPWM techniques.