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A Transient-Enhanced Digital Low-Dropout Regulator with Bisection Method Tuning

This paper presents a digital low-dropout regulator (DLDO) with bisection method (BM) tuning for fast transient response. Different from conventional DLDOs, the proposed DLDO employs adders instead of shift registers to tune binary distributed PMOS power switches. When a load-transient is detected, the BM tunes power switches within constant steps to stabilize the output voltage in a short setting time. To improve the voltage undershoot induced by fluctuating load, an additional analog assistant (AA) technology is adopted. The proposed DLDO is designed and simulated in 180nm CMOS process. A maximum setting time of 3.3us with only 9μA quiescent current and the voltage undershoot/overshoot of 187/43mV is obtained with an 18mA/1ns load step and a total capacitor of 100pF. The resulting figure of merit is 0.42ps.