{'fraction_non_alphanumeric': 0.0152, 'fraction_numerical': 0.0, 'mean_word_length': 5.689839572192513, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Signal Processor Architecture Performance Assessment For Very High Speed Integrated Circuits (VHSIC)

This paper discusses the problem of digital signal processor architecture performance evaluation. This aspect of signal processor technology, while not totally ignored in the past, has not received the explicit consideration which it deserves. If effective use of available resources is to be achieved, future implementation of complex VHSIC/VLSI-based systems probably will require increased consideration of the architecture performance assessment problem. Three broad approaches to this problem are discussed and a brief example of each is presented. Of the approaches considered, it appears at present that techniques based upon computer-aided simulation and/or analyses of signal processor models represent the most promising approach to this problem. Quantitative figures of merit for use in evaluating/comparing signal processor performance are presented and briefly discussed. These are typically defined in terms of a limited number of selected system parameters which might be of concern in a given application. Several techniques that are of interest to the architecture performance assessment problem are briefly reviewed and discussed.