{'fraction_non_alphanumeric': 0.031413612565445025, 'fraction_numerical': 0.005235602094240838, 'mean_word_length': 4.632352941176471, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Josephson Latch-Decoder

This paper proposes a Josephson decoder named a latch-decoder. It is constructed from two-input AND gates operated in the latching mode. Main features of this decoder are high speed operation and simple circuit construction. Discussions are focused on the principle and design of the latch-decoder. An experimental 3-to-8-bit decoder is also demonstrated.