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Multi-branch inductance extraction procedure for multi-chip power modules

This paper describes a procedure for estimating the parasitic impedances associated with multi-chip power module (MCPM) interconnections and packaging at finer granularity than has been previously demonstrated. The methodology introduced here makes it possible to determine an estimate for the loop inductance at each individual semiconductor die position within the module geometry based on frequency-domain characterization of a single, specially-configured MCPM test subject. The impedance estimates produced by this procedure are shown to be in good agreement with values obtained through finite element analysis (FEA) using COMSOL.