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Parallel test generation using circuit partitioning and spectral techniques

The problem of testing digital circuits is becoming much more difficult as these circuits increase in size and complexity. Thus, the development of parallel procedures for test pattern generation is currently a field of important research activity. A new parallel procedure to determine the set of patterns to test a circuit is presented. It stems from a circuit partitioning scheme based on a mixed simulated annealing and tabu search technique which allows the load to be distributed among the processors in such a way that similar sized parts of the circuit are assigned to each processor while communications between processors are minimised. The method applied by each processor to obtain the test pattern uses an algorithm based on the Reed-Muller spectrum to determine the equation, thus being different from other procedures previously reported. The experimental results obtained by applying the procedure to the usual benchmark circuits in this field (ISCAS set) show good efficiencies which are maintained when the number of processors increases.