{'fraction_non_alphanumeric': 0.023421588594704685, 'fraction_numerical': 0.02240325865580448, 'mean_word_length': 4.371584699453552, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A low power switching method with variable comparator reference voltage and split capacitor array for SAR ADC

A low power switching method for SAR ADC is proposed in this paper. With this switching method the comparator first compares the sampled input voltage with Vref/2 to generate the MSB and determine whether to use Vref/2 or Vref as the comparator reference voltage in the following conversation steps, and the DAC with a split capacitor array uses Vref/2 as the reference voltage to generate the remaining bits. In MATLAB simulation, with the proposed switching method, the average switching energy of the DAC is reduced to 7.8% of the conventional one. An 8-bit SAR ADC employing this low power switching method is designed and simulated in 0.18μm CMOS technology. Simulation results show that at the 1.2 V supply and a reference voltage of 1.2V with a sampling rate of 1 MS/s, the ADC consumes 8.14μW and reaches an ENOB of 7.69 bits and an FOM of 39fJ/conversation-step.