{'fraction_non_alphanumeric': 0.03783783783783784, 'fraction_numerical': 0.013513513513513514, 'mean_word_length': 5.226890756302521, 'pattern_counts': {'":': 0, '<': 1, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Scaling Limits of Capacitorless Double Gate DRAM Cell

In this paper, we consider the scaling of capacitor-less single transistor (1T-OC) DRAM by classical (CL) and quantized-ballistic (QB) methods to establish that (1) it may be difficult to scale 1T-OC cell below 30 nm channel length even with ultrathin (<3 nm) body because of the quantum confinement effects, (2) cumulative drain disturb time must be limited to ensure reasonable retention times, (3) the surround gate structures such as silicon nanowires (as 1T-OC cells) are expected to have more significant confinement effects, and (4) practical considerations such as the process variations in cell geometry and single events upsets are likely to remain important scaling concerns