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High density Cu-Cu interconnect bonding for 3-D integration

The demand for more complex and multifunctional microsystems with enhanced performance characteristics is driving the electronics industry toward the use of best-of-breed materials and device technologies. Three-dimensional (3-D) integration enables building such high performance microsystems through bonding and interconnection of individually optimized device layers. Bonding of device layers can be achieved through polymer bonding or metal-metal interconnect bonding with a number of metal-metal systems (e.g. Cu-Cu, Cu/Sn-Cu, etc.) currently under development. RTI has been investigating and characterizing Cu-Cu and Cu/Sn-Cu interconnect processes for high density area array applications, demonstrating bonding between pads less than 15 microns in diameter for large area array configurations. Cu and Cu/Sn bump fabrication processes were developed that provide well-controlled surface topography necessary for the formation of low resistance, high yielding, and reliable interconnects. In this paper, the effects of Cu interconnect bonding parameters (pressure and temperature) and thermal reliability testing (thermal cycling and aging) on electrical connectivity and mechanical strength are presented and compared to Cu/Sn-Cu interconnect bonding with an eye toward small pitch scaling and ease of assembly. The conditions for producing Cu-Cu bond strengths ≫ 110 MPa and electrical connectivity as high as 99.999% are described.