{'fraction_non_alphanumeric': 0.03251533742331288, 'fraction_numerical': 0.0, 'mean_word_length': 5.550200803212851, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
An Algorithm - Architecture Co-Designed System for Dynamic Execution-Driven Pre-Silicon Verification

In EDA industry, functional verification of a design-under-test (DUT) has been pre-dominantly performed through software based simulation. However, the never-ending growth of DUT size rapidly degrades their execution speed which, in turn, escalates the verification effort. This manifests the requirement for random dynamic simulation, using which only the typical behaviors, and not all possible behaviors of a chip can be verified in a time-bound simulation run. To overcome this bottleneck, the EDA industry is increasingly adopting “hardware-accelerated simulation platforms”, which are classified as simulation-accelerators, emulators and FPGA prototypes. These platforms still do not address the state-space problem effectively, as they work in cycle-driven or event-driven mode. They also require huge design porting effort to the native development environment. Hence, the need of the hour is a simulator that needs to be design-aware enough to partition and map huge dataflow-graphs (DFGs) of scientific applications, at each abstraction level of verification and schedule it for simulation. In this paper, we present a novel approach for dynamic pre-silicon verification, called EX-DRIVE (execution-driven functional verification methodology). It addresses the state-space explosion problem in verification by hosting a variety of partitioning and mapping algorithms. We show that the proposed functional-verification flow achieves significant improvement in verification performance over industry standard simulators.