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A 3.2 mW 0.13 μm high sensitivity frequency-domain CMOS capacitance interface

A frequency domain capacitance interface system is proposed for a femto-farad capacitance measurement. In this technique, a ring oscillator circuit is used to generate a change in time period, due to a change in the sensor capacitance. The time-period difference of two such oscillators is compared and is read-out using a phase frequency detector and a charge pump. The output voltage of the system, is proportional to the change in the input sensor capacitance. The capacitance sensor interface system was designed and a prototype was implemented in a 0.13 μm standard CMOS technology. Experimental and simulation results are presented. It exhibits a maximum sensitivity of 8.1 mV/fF, which is significant improvement over the state-of-the-art while consuming 3.2 mW from a 1.2 V supply.