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Towards Fine and Medium Grain Dynamic Functional Extraction for HW/SW Acceleration

In this paper, an acceleration method for hardware platforms for embedded systems is presented. The target system is a Xilinx Virtex II Protrade with an embedded PowerPCtrade. The PowerPCtrade operates as a general purpose processor, while the reconfigurable FPGA fabric is used as a reconfigurable co-processor. A comparison experiment of HW acceleration using different grain levels is done, and results are shown using an MPEG audio decoding algorithm example. A HW/SW interface to communicate the processor with a custom hardware which is synthesized in the reconfigurable fabric is shown. Algorithm analysis is done by profiling and a partitioning decision is based on a fine-medium grain philosophy, which allows more hardware reusability, and simpler and faster reconfiguration. Repetitive functional blocks in the algorithm were detected and implemented in the FPGA logic, and corresponding generic software functionally for writing/reading data in the co-processor unit was developed.