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Hardware reduction methodology for 2-dimensional kurtotic fastica based on algorithmic analysis and architectural symmetry

In this paper we propose a hardware reduction methodology through detailed algorithmic analysis and exploiting datapath symmetry for 2-D Kurtotic Fast ICA. The relationship of the hardware saving with respect to input data frame-length and maximum iteration for convergence is also explored. An example architecture following the developed hardware reduction methodology consumes 3:55 mm2 silicon area and 27:1 µW @1 MHz at 1:2 V supply using 0:13 µm standard cell CMOS technology showing the effectiveness of the proposed methodology.