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Loading effects in deep silicon etching

Feature scale pattern dependencies and chip and wafer level loading effects complicate the use of deep silicon etching in MEMS applications. They have major effect on uniformity and etch rate on the wafer scale and on a feature scale. The aim of this study was to find the limitations that these phenomenon set on deep silicon etching. Wafer scale, chip scale and feature scale structures were etched in pulsed ICP. Etched depths were 10-500 micrometers , and aspect ratios up to 20:1. Strong dependence of etch rate on loading was observed. On the wafer scale average etch rate was greatly reduced, from 5.4 micrometers /min to 1.7 micrometers /min. At same time uniformity deteriorated from excellent 2 percent to 35 percent which is too high value to practical applications. Chip pattern density did not affect etch rate on an isolated small chips but for 10 by 10 mm2 chip 10 percent etch rate reduction was seen at high chip scale load. In this case wafer scale etchable area was 6 percent. We show that feature scale and wafer scale pattern dependencies in ICP etching are strongly coupled.