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Transformation-based peak power reduction for test sequences

This paper describes a new algorithm for transforming an existing test sequence for sequential circuits into a cheaper one from the point of view of peak power consumption. The algorithm exploits both symbolic techniques (to identify sub-sequences performing a given state transition) and heuristic methods. Preliminary experimental results show that the algorithm is able to reduce the peak power consumption of ATPG-generated sequences by up to 54%, while the reduction of the fault coverage is limited to at most 1%.