{'fraction_non_alphanumeric': 0.018820577164366373, 'fraction_numerical': 0.0, 'mean_word_length': 5.487804878048781, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Behavioral fault modeling and simulation of phase-locked loops using a VHDL-A like language

A new methodology called induced behavioral fault modeling is presented for fault simulation and testing of analog and mixed-signal circuits, and demonstrated using voltage controlled oscillators and phase-locked loops. The key of this methodology is to use actual layout and process defect information to derive a set of realistic faults at the transistor level, and to generate a small set of behavioral fault models-in a mixed-signal hardware description language-that abstracts the derived transistor-level faults. While ensuring the same fault coverage as transistor-level fault modeling, induced behavioral fault modeling offers significant advantage in simulation efficiency and modeling capacity.