{'fraction_non_alphanumeric': 0.023191094619666047, 'fraction_numerical': 0.0018552875695732839, 'mean_word_length': 5.096045197740113, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 1, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Implementation of Six-Layer Automatic Elevator Controller Based on FPGA

This paper introduces the design of FPGA-based elevator controller. Through structural analysis of the system, we use the modular design method. A new FPGA-based elevator controller is designed in order to overcome the defects of traditional single-chip microcomputer-based elevator controller, such as the complexity of peripheral circuit and the instability of the performance. The FPGA chip is used as the core of the controller, and the functions of the controller are described in VHDL language. The editing, debugging and combination of the programs are performed in the integrated software environment-Quarters II 8.1. And at the same time circuit synthesis and simulation is also performed. Finally, the program codes are downloaded to the FPGA chip using specialized cable to implement its functions. This design not only simplifies the design of the circuit, improves the capability of anti-jamming, but lowers the power consumption as well. Thus, the controller has broad application prospects.