{'fraction_non_alphanumeric': 0.02220324508966695, 'fraction_numerical': 0.0, 'mean_word_length': 5.43956043956044, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Representing Bit Vectors and Arrays in Control Data Flow Graph for High Level Synthesis

High-Level Synthesis (HLS) comprises translating a behavioral specification into its corresponding Register Transfer Level (RTL) specification of the system. Structured Architecture Synthesis Tool (SAST) takes the behavioral description of an input design and outputs the synthesizable RTL Verilog code. This work involves enhancing the SAST by adding interfaces for the verifier. The first step of HLS involves deriving control and data-path information from the behavioral code into a Control Data Flow Graph (CDFG). We added array access notations to the existing CDFG representation. Using that representation we can schedule the array operations. The preprocessor converts the input CDFG into intermediate representation (IR) which consists of the precedence constraints or partial order between the operations in each basic block, along with the incoming (in) and outgoing (out) variables set for each basic block. We implemented preprocessing stage of SAST in order to handle the array operations. This generated intermediate representation is used as input to the scheduler.