{'fraction_non_alphanumeric': 0.035868005738880916, 'fraction_numerical': 0.005738880918220947, 'mean_word_length': 4.8655462184873945, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Study on scalability of hybrid junctionless FinFET and multi-stacked nanowire FET by TCAD simulation

This work studied the electrical characteristics of silicon-oninsulator (SOI) multi-stacked nanowire junctionless FET (NW-JL-FET) and SOI hybrid junctionless FinFET (H-JL-FET) using TCAD simulation. The scalability of the above two structures was investigated by simulating device performance with gate lengths from 30 nm to 5 nm. Results show that NW-JL-FET has better performance than that of H-JL-FET due to gate all around structure. However, H-JL-FET still has good performance under ultra-small gate length indicating FinFET still could be a competitor for 5 nm and beyond technique nodes.