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Dual Metal Hetero Dielectric GAAFET based Energy Efficient Digital Circuits

In this work, basic logic gates, universal logic gates, half adder (HA), and full adder (FA) have been designed using device-circuit co-design approach for low energy efficient circuits. A Verilog A model based on look up table approach has been developed for DM-HD GAAFET to perform all SPICE circuit simulations. The channel length of 28nm is chosen for device DM-HD GAAFET to create Verilog A model which further used to design logic gates, HA and FA. For DM-HD GAAFET, DIBL and leakage current found very low. Simulation results for CMOS and DM-HD GAAFET based logic gates, HA and FA are compared for power, delay, and energy consumption. For DM-HD GAAFET based logic gates 79.5% energy reduction is observed. Moreover, reduction in power dissipation and energy consumption for HA is observed as approximately 78.3% and 73.1% respectively, while for FA is approximately 78.1% and 61.9% respectively.