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Thermal performance characteristics of folded stacked packages

The trend towards miniaturization and increased functionality has pushed for packaging more than one die together, while maintaining chip scale. Multi-chip packages consist of either vertical stacking of the die to reduce package footprint and/or placing dies adjacent to each other to improve functionality. The challenge lies in continuing to reduce the size while satisfying the stringent thermal, mechanical and electrical requirements of the wireless industry. One such solution in this area is the folded stacked technology developed by Tessera Technologies. In this design, the dies are placed side-by-side onto a substrate, which is then folded appropriately to obtain a low profile multi-chip CSP package. Their design allows the flexibility of different die sizes and die pad configurations to cater to different applications. Any multi-chip solution carries along with it the concern over its capability to dissipate heat quickly and effectively to prevent overheating of the die. Thus this work focuses on studying the thermal performance characteristics of a multi-die folded stack package.