{'fraction_non_alphanumeric': 0.014234875444839857, 'fraction_numerical': 0.002372479240806643, 'mean_word_length': 5.645669291338582, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design and VLSI implementation of new hardware architectures for image filtering

Nowadays, hardware implementation of image and video processing algorithms is highly attractive. Needing to real-time processing makes hardware implementation of these algorithms inevitable. In most of image and video processing algorithms, pre-processing filters are the first and most important stage of the algorithm. In this paper, we propose new hardware architectures for the implementation of image filters including Gaussian, median and weighted median filters. The proposed architectures aim to optimize the filter implementation for speed and gate usage. The proposed architectures are implemented and synthesized in ASIC with 65 nm technology and different specification of the implementation such as maximum clock frequency and IC area are reported.