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Suitability of tile-based rendering for low-power 3d graphics accelerators

In this dissertation, we address low-power high performance 3D graphics accelerator architectures. The purpose of these accelerators is to relieve the burden of graphical computations from the main processor and also to achieve a better energy efficiency than can be achieved by executing these computations on the main processor. Since external data traffic is a major source of power consumption and because usually the rasterization stage of the 3D graphics pipeline requires the highest amount of data traffic, in this dissertation we especially focus on this stage of the graphics pipeline. Another reason for focusing on the rasterization stage is that it requires more processing power than the other stages because the operations are pixel-based. A promising technique to reduce the external data traffic in the rasterization stage of the graphics pipeline is tile-based rendering. This technique decomposes a scene into tiles and renders the tiles one by one. This allows the color components and z values of one tile to be stored in small, on-chip buffers, so that only the pixels visible in the final scene need to be stored in the external framebuffer. Tile-based accelerators, however, require large scene buffers to store the primitives to be rendered. While there have been studies related to the tile-based rendering paradigm for high performance systems, we are specifically discussing the suitability of tile-based 3D graphics accelerators for low-power devices. In order to evaluate various low-power 3D graphics architectures we first present GraalBench, a set of 3D graphics workloads representative for contemporary and emerging mobile devices. Furthermore, we propose several scene and state management algorithms for tile-based renderers. Thereafter, we analyze the performance of tile-based renderers compared to that of traditional renderers and we also determine the influence of the tile size on the amount of the data-traffic required for the rasterization stage of a tile-based renderer. In order to reduce even more the data traffic between the main memory and graphics accelerators, and to exploit the high temporal and spatial locality of texture accesses, we have also investigated several cache structures. Our results show that the proposed algorithms for tile-based renderers can effectively decrease the data traffic and computational requirements for the rasterization stage of the 3D graphics pipeline.