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Does Negative Bias Temperature Instability Affect the Soft Error Rate of SRAMs ?

Integrated circuits operating in space must withstand a harsh radiation environment [1], but, at the same time, they are subjected to the same intrinsic degradation mechanisms that are present on Earth. Aging of MOSFETs is one of the hottest topics in CMOS research. In fact, due to the ever increasing electric field, the reliability margin of modern devices is rapidly decreasing [2]. Negative Bias Temperature Instability (NBTI), in particular, is considered one of the most pressing threats nowadays [2]. As the name suggests, NBTI is active when a negative bias is applied to an MOS structure (e.g., an ON PMOSFET) at high temperature. NBTI causes PMOS parameters to change over time due to trapped charge and interface state generation. Due to ever increasing concern about wear-out, several synergetic studies have been carried out to evaluate possible interactions between radiation effects and aging, for instance in SRAMs [3] and in Flash memories [4]. In this work we study the implications of NBTI as far as Single Event Upsets (SEU) are concerned. To this purpose, we will use a combination of SPICE simulations and heavy-ion experiments.