{'fraction_non_alphanumeric': 0.022774327122153208, 'fraction_numerical': 0.005175983436853002, 'mean_word_length': 5.198717948717949, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Reliable routing schemes in 3D network on chip

3D network on chip (3D-NoC) is the replacement of traditional infrastructures and the new design paradigm for communication in future very large-scale system on chip (SoC), due to the fact that it provides flexibility, extensibility and low power consumption. One of the most important issues of a 3D-NoC design is the implementation of an efficient and reliable routing algorithm, which has a direct impact on the overall network performance. A routing algorithm aims predominantly at fulfilling three distinct objectives: deadlock freedom, congestion awareness and fault tolerance, which is a highly desired but somewhat a challenging task. In this paper, a non-exhaustive list of the most relevant routing algorithms in 3D-NoC are surveyed and classified based on their objectives, the advantages and drawbacks of each algorithm are also presented, as well as the possible enhancements to improve their reliability.