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In-Probe Ultrasound Beamformer Utilizing Switched-Current Analog RAM

A low-power high-energy-efficiency switched current (SI)-based beamformer is designed and fabricated in a 180-nm complementary metal-oxide-semiconductor technology. The beamformer is implemented using an analog RAM (ARAM) delay and sum approach. A new bias-shared SI architecture is proposed for the low-power ARAM implementation. The highlight of the proposed architecture is that the number of memory cells in the ARAM can be increased without a proportional increase in power consumption. This feature allows the beamformer to have a longer memory depth and higher flexibility for wave shaping during the beam formation. As proof of concept, 16 channels have been implemented for the beamformer, each containing 16 memory cells. The current consumption of a single memory cell is 27 μA. The maximum input signal frequency is 10 MHz, and the sampling frequency is 25 MHz. The measurement results for the beamformer show a 60-dB signal-to-noise ratio after summation. The total current consumption of the chip, including the beamformer along with the bias generation and a digital controller, is 7 mA, and it occupies an active area of 1.3 mm2.