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Lattice-Traversing Design Space Exploration for High Level Synthesis

This paper describes a design space exploration methodology for High Level Synthesis (HLS) frameworks. Inputs of HLS tools are a description (usually in C/C++) of the functionality of an intended hardware, and a set of optimisation directives that specify its implementation, hence allowing the generation of many design variants with widely varying performance and required resources. The relationship between directives and performance/cost is nonetheless not straightforward, and highly influenced by application-specific characteristics. A major challenge facing designers is then to define effective values for the directives while avoiding time-consuming – and often infeasible – exhaustive explorations. We herein address it by proposing a novel HLS exploration approach which employs a lattice representation of the design space, and a methodology for its navigation. We base our strategy on the observation that Pareto-implementations share a low variance among their configurations. We therefore guide the selection of HLS directives minimising the variance of new candidate solutions, with respect to the best performing ones that have already been visited. By only requiring local searches in the lattice space, our methodology gracefully scales to complex designs. It results in close approximations of the real Pareto frontier, while requiring a lower workload and fewer synthesis runs with respect to existing approaches.