{'fraction_non_alphanumeric': 0.01564537157757497, 'fraction_numerical': 0.0, 'mean_word_length': 5.095238095238095, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A circuit reduction technique for finding the steady-state solution of nonlinear circuits

Computing the steady-state response of large nonlinear circuits is becoming a key simulation requirement due to the rapid market growth of RF silicon integrated circuits. In this paper, we describe a nonlinear circuit reduction algorithm for finding the steady-state response. The proposed algorithm uses a congruent transformation-based technique to reduce the harmonic-balance equations into a much smaller set of equations. The main feature of the reduced circuit is that it shares with the original one a certain number of the derivatives with respect to the RF input power, steady-state analysis is then carried out on the reduced circuit instead of the original circuit.