{'fraction_non_alphanumeric': 0.0345821325648415, 'fraction_numerical': 0.018731988472622477, 'mean_word_length': 5.0964912280701755, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Background calibration of bit weights in pipeline ADCs using a counteracting dither technique

A counteracting dither technique is proposed to remedy the bit-weight error issue in pipeline analogue-to-digital converters (ADCs). A capacitor is added to the traditional comparator dither scheme. By switching the added capacitor, the residue swing increment due to comparator dither is counteracted, thereby greatly relaxing the design requirement of the residue amplifier. Behaviour-level simulation results show that the spurious-free-dynamic-range and the signal-to-noise-and-distortion-ratio are improved from 59 and 52.8 dB to 102.7 and 85 dB after calibration in a 14-bit ADC, respectively.