{'fraction_non_alphanumeric': 0.020966802562609202, 'fraction_numerical': 0.0064065230052417, 'mean_word_length': 5.684824902723736, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Stress inspection for overlay characterization

The understanding and control of stresses accumulated during device fabrication is becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for the management of overlay and depth of focus during lithography. This paper describes the use of a comprehensive stress inspection technology, the Coherent Gradient Sensing (CGS) interferometer, for the characterization of stress-induced overlay errors. Using CGS, stresses and wafer distortions induced by any upstream process (or series of processes) can be measured, and the relative contribution of stress-induced overlay associated with individual processes can be evaluated. The CGS technology has two key features that enable the application of stress metrology to lithographic overlay: 1) whole-wafer stress measurement with approximately 800,000 points on a 300mm wafer, 2) patterned wafer stress measurement that is highly insensitive to variations in device structures or materials, such that any location within a die or wafer can be characterized without the need for traditional test structures. Fundamentally, thin-plate theory relates the in-plane stresses in a thin film structure to in-plane strains and displacements. The in-plane displacements in the film due to stress are related to the lithographic overlay. The approach presented here demonstrates the relationship between stress gradients are related to in-plane displacements. Data from case-studies are presented that further shows the correlation between in-plane displacements, measured from wafer distortion and traditional measurement of overlay targets.