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Architectures of Stack Soft-CPUs in FPGA

The article discusses options for the architecture of stack processors, implemented on the basis of configurable FPGA resources. The capabilities of programmable logic chips with FPGA architecture are determined mainly by specialized resources operating in parallel - digital signal processing units and IP-cores synthesized on the basis of logical cells and memory blocks. The purpose of processor cores added to FPGA-based projects is shifting towards the task of managing core computing resources. Thus, the processor in FPGA-based projects is no longer the most productive computing node, so its characteristics such as code density and ease of connecting peripheral devices are beginning to play a more important role. The stack machine provides the ability to minimize the width of the processor control word, since it does not require the transfer of operands in the instruction, therefore, the choice of a processor with a stack architecture allows you to reduce the amount of memory required for its operation, which is important for FPGAs with limited on-chip memory resources. The varieties of stack processors considered in the article are mainly focused on FPGAs of small and medium integration levels.