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Novel circuit technique for high-speed ECL gates

We present a novel circuit technique for high-speed emitter-coupled logic (ECL) gates. SPICE simulation indicated the novel ECL circuit technique could boost the operating speed by about 10% above that of a conventional gate without increasing power consumption. In addition, we analyzed the propagation-delay times of conventional and novel ECL gates using SPICE sensitivity analysis, which revealed that our circuit could be operated at high speed because the delay time constants of RLCjC and RbCjC were reduced. In addition, we devised a novel toggle flip-flop (T-FF) circuit using our ECL gates. The simulations demonstrated that the maximum operating frequency of our T-FF was about 10% faster than that of the conventional circuit. Our circuit technique is thus attractive for fabricating ultra-high-speed integrated circuits (ICs) with data rates beyond 50 Gbit/s using Si-based technology.