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A superconducting-nanowire 3-terminal electronic device

In existing superconducting electronic systems, Josephson junctions play a central role in processing and transmitting small-amplitude electrical signals. However, Josephson-junction-based devices have a number of limitations including: (1) sensitivity to magnetic fields, (2) limited gain, (3) inability to drive large impedances, and (4) difficulty in controlling the junction critical current (which depends sensitively on sub-Angstrom-scale thickness variation of the tunneling barrier). Here we present a nanowire-based superconducting electronic device, which we call the nanocryotron (nTron), that does not rely on Josephson junctions and can be patterned from a single thin film of superconducting material with conventional electron-beam lithography. The nTron is a 3-terminal, T-shaped planar device with a gain of ~20 that is capable of driving impedances of more than 100 k{\Omega}, and operates in typical ambient magnetic fields at temperatures of 4.2K. The device uses a localized, Joule-heated hotspot formed in the gate to modulate current flow in a perpendicular superconducting channel. We have characterized the nTron, matched it to a theoretical framework, and applied it both as a digital logic element in a half-adder circuit, and as a digital amplifier for superconducting nanowire single-photon detectors pulses. The nTron has immediate applications in classical and quantum communications, photon sensing and astronomy, and its performance characteristics make it compatible with existing superconducting technologies. Furthermore, because the hotspot effect occurs in all known superconductors, we expect the design to be extensible to other materials, providing a path to digital logic, switching, and amplification in high-temperature superconductors.

astronomy, and its performance characteristics make it compatible with existing superconducting technologies. Furthermore, because the hotspot effect occurs in all known superconductors 7,8 , we expect the design to be extensible to other materials, providing a path to digital logic, switching, and amplification in high-temperature superconductors.
The nanocryotron (nTron) is a two-dimensional superconducting device with a gate, a drain, and a source terminal, depicted in . Bias currents ≳ 0.9 I c0 resulted in undesired behavior such as photon-and noise-induced hotspot generation, while operating the devices at lower bias currents improved their robustness to source noise and typical ambient magnetic noise.
Despite the difference in underlying physical phenomena, the nTron is functionally analogous to a transistor. Fig. 1d 9 . In the case of thin-film NbN, out-diffusion of hot electrons is the primary means of thermal energy transfer from the hotspot to the surrounding material 10,11 ; the characteristic diffusion coefficient for non-equilibrium electrons has been measured 12 to be 45 nm 2 /ps.
To corroborate our measurement results and facilitate future designs, we simulated the nTron device geometry using an established theoretical framework, the two-temperature model 13 , which uses an effective electron temperature T e to represent the temperature of populations of quasiparticles and Cooper pairs. The simulation used no free parameters-we instead employed measurements from the device as well as empirical parameters for thin-film NbN found in the literature 11,12 . The simulation results showed that when a hotspot was formed in the choke of the nTron, the effective electron temperature T e of the surrounding ~100 nm was increased. This temperature increase corresponds to a decrease in J c over the same radius, effectively reducing the total channel critical current. As a result of the hotspot formation, the I c0 was reduced by 28% of its original value, closely matching the measured value of 30.5%. Additionally, just above I c gate the resistance of the simulated gate hotspot was 823 Ω, which was comparable to the measured resistance of 832 Ω.
The nTron consists of a single layer of thin-film superconducting material, so its 2D geometry defines its operation. The layout of the device has several essential design elements, resulting in a large design parameter space in which future implementations may be optimized.
The most critical design element is the size and location of the choke region, which is the point of highest current density for the gate input current and is where the hotspot first forms .
To demonstrate the suitability of the nTron for digital applications, we used it to build AND/OR/NOT/COPY gates (Fig. 2a), and from those constructed a half-adder (Fig. 2b). We operated the half-adder in a pipelined fashion, where valid inputs were translated into valid outputs for the next stage only upon the enabling of the gate bias current. After the computation was completed and the final outputs were recorded, all the input and bias currents were shut off to unlatch the gates and reset the computation. For the purposes of this demonstration, operating in the latching regime enabled us to tolerate potentially large fabrication defects in these first devices. In the latching regime, variations between the OFF-state input impedances of the gates did not matter because each stage was able to drive arbitrarily large input impedances in the next stages-to operate in a non-latching regime, output impedances must be more carefully controlled 14 . No electrical or magnetic shielding was necessary.
We performed a number of additional characterization experiments to demonstrate RF operation, sensitivity, and robustness of the nTron. To characterize the device at higher frequencies, we input a 10 MHz square wave into the device to generate an eye diagram. With a 1.46 kΩ output load, the nTron was able to convert a 3.10 ± 0.02 μA input square wave into a 62 We tested the nTron's ability to amplify pulses as well as established an upper bound to its jitter by integrating it with a superconducting nanowire single-photon detector 15 (SNSPD).
When detecting a photon, SNSPDs produce millivolt-scale microwave pulses with sub-100 ps rising edges. The integrated device used these pulses as input into the gate of a nTron amplifier.
We monolithically fabricated the SNSPD and nTron on the same film within a 100 μm 2 area, connecting the SNSPD output to the gate of the nTron. Our circuit design (Supplementary

Methods Summary
All the nTron devices used in this paper were fabricated from a contiguous ~10 nm film of niobium nitride (NbN) deposited on a single 2" R-plane sapphire wafer. For the simulation, parameters extracted from the device and the film from which it was fabricated included (1)     For the NOT gate, when a logical LOW was input, I c channel was greater than the bias current, allowing all the current to pass through it without switching. However, I c pulldown was designed to be smaller than the full channel bias current, which caused the pulldown constriction to switch and diverted the excess current into the output, producing a logical HIGH out. In the case of a HIGH input, the suppressed I c channel (I gate ) was less than the bias current. As a result, the nTron transitioned to the ON state, and current was diverted to ground through the shunt resistor. The pulldown constriction served to tie the output to ground, even in the presence of the unavoidable small current leaking through the resistive channel.

Experimental details: Half-adder
The half-adder experiment consisted of fabricating several individual gates on a single chip, connecting them via wirebond, and biasing them in a pipelined manner to perform the summing computation. We built a custom 16-channel combined ADC Using the experimental setup shown in Fig. S1a, we generated a 10 MHz eye diagram for the nTron digital amplifier. We accomplished this by sending one current square wave into the device channel, and one current square wave into the gate port (delayed by approximately 10 ns relative to the channel square wave). The channel square wave primed the nTron to switch from the ON to the OFF state, such that when the rising edge of the gate square wave arrived, the nTron switched, generating an output current which was read out by the scope. We tested the nTron as a comparator to characterize the current sensitivity of the gate input. As shown in Fig. S2, the experimental setup was the same as that of the 10 MHz eye diagram characterization, only differing in the current bias and readout scheme. First, we applied a 52.8 μA bias current to the channel in order to prime it for transition from the ON to OFF state when I gate exceeded I c gate . We then ramped the gate current from 0 to 15 μA at a rate of 16.7 nA/μs, recording the output current through the load resistor R L on a 1 GHz oscilloscope.
We repeated this experiment 11,000 times, plotting the results as a histogram (Fig. S2b). From the histogram, we found a mode switching value of 2.91 μA with a 1-σ grey zone of 66 nA. Pulses generated from the device and output to the coax in (a) arrived at the other end of the coax, shown in (b), where they were amplified with 3× 20-3000 MHz amplifiers before being input to the scope.

SNSPD + nTron amplifier circuit design/schematic and experimental details
As shown in the Fig. S3, the SNSPD and nTron pulse amplifier were integrated as single circuit.
Current biasing was accomplished through the use of inductive splitting, where the inductance was provided by the kinetic inductance of the nanowires. The SNSPD nanowires had a width of 60 nm, and the inductor nanowires had widths of 200 nm. The entire circuit occupied an area of approximately 100 μm 2 .The 50 Ω lines were high-frequency coaxial cable running between the sample and room-temperature electronics. During operation, we biased the SNSPD at 35 μA and