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A new flip-flop based on multiple leakage reduction techniques

In present CMOS circuits, the scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to both leakage dissipations and total power consumptions. This paper proposes a new flip-flop, which uses P-type CMOS technique, power-gating and dual threshold technique to reduce both sub-threshold and gate leakage circuits. Simulation results show that the proposed MLRT (multiple leakage reduction technique) flip-flop saves 60–70% leakage power dissipations and 40–50% total power consumptions compared with the single-threshold transmission gate one.