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Highly Parallel Lattice QCD Wilson Dirac Operator with FPGAs

In this paper, we discuss a highly parallel implementation of the lattice QCD Wilson Dirac operator on FPGAs. The operator is described as a data-flow graph using OpenSPL and acts on a four-dimensional lattice collecting all next neighbour terms. The so implemented kernel fits on an Altera Stratix V FPGA using fixed-point arithmetic. This allows us to compute all arithmetic operations simultaneously. In addition, the OpenSPL language shows also an implicit optimized locality expressed by the offset operator which is studied on the presented implementation. The lattice is held in DDR3 memory on the FPGA accelerator card and streamed into the FPGA over six memory channels where we use the MAX4 card and the software framework from Maxeler. The operator is memory bound and has an equivalent arithmetic intensity of 0.92 FLOPs/Byte. With a clock frequency of 133 MHz, we get an equivalent theoretical peak performance of 176 GFLOP/s. Therefore, we also address the memory interface and memory access pattern.