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Variability Immune FinFET-Based Full Adder Design in Subthreshold Region

Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. To improve switching performance, energy/switching, and also the robustness of the subthreshold logic for the implementation of 1-bit static full adder, we propose the use of sub-FinFET (sub-threshold voltage FinFET) transistors. The power, speed and energy evaluation has been carried out using extensive simulation on HSPICE circuit simulator. The simulation results are based on 32 nm CMOS Berkeley Predictive Technology Model (BPTM).