{'fraction_non_alphanumeric': 0.04081632653061224, 'fraction_numerical': 0.0397422126745435, 'mean_word_length': 4.4186046511627906, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS

This paper presents a 9-bit 222 MS/s low-power asynchronous single-bit/cycle successive approximation register (SAR) ADC. The SAR ADC combines techniques such as asynchronous clocking, binary-weighted custom-designed capacitive DAC with small unit capacitors, splitting monotonic capacitor switching, and dynamic SAR memory to optimize both power consumption and SAR loop delay using a single comparator. Measurement results show that the 9-bit SAR ADC achieves 47.6 dB SNDR and 29.6 fJ/conversion-step figure-of-merit (FoM) near Nyquist frequency at 222 MS/s, consuming 1.07 mA from a 1.2 V supply. The ADC does not consume static power and the current consumption scales down linearly with the sampling rate, keeping the low FoM value constant over a very wide sampling frequency range. The design occupies an active area of 92 μm × 180 μm (0.017 mm2) in 65 nm CMOS.