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Realization of a self-testing bus arbiter

This paper discusses a realization of a self-testing distributed arbiter for bus-connected systems. One of the traditional schemes for arbitration is that each of the connected modules acknowledges when the arbitration is completed. However, there is a problem in that a dedicated software as well as a complex hardware are required, which increases the cost and affects the through-put of the system. 
 
 
 
The method proposed in this paper assigns a certain code as the module number for verification of arbitration, and detects failure by a retrial using its complement. In other words, the method aims at secure arbitration using time-space redundancy, i.e., redundancy in time and redundancy in code space, and at realization by as simple a circuit as possible, with the self-testing function. 
 
 
 
It is verified from the results of simulation that all single stuck-at faults can be detected for the case of 3 bits, under the assumption that all possible inputs are given before the next failure is produced. Even if not all of the inputs are given, there was no observed extraordinary operation where an incorrect module is selected. Thus, the self-testing arbiter with a high speed and a simple hardware configuration can be realized.