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Investigating a four-issue deterministic VLIW architecture for real-time systems

The correct functioning of real-time systems depends not only on the logically correct response, but also the time when it is given. This type of application is increasingly present today and the processing demand is such that complex processors are needed. Unfortunately general purpose processors are not well suitable for hard real-time applications due to their non-deterministic behavior caused by the use of cache memories, branch prediction, speculative execution and out-of-order pipelines. The goal of this work is to investigate pipeline performance of VLIW (Very Long Instruction Word) architectures for real-time systems with an in-order pipeline, a direct mapped instruction cache and a scratchpad memory to accelerate data memory. The prototype was implemented in VHDL considering the HP VLIW ST231 ISA. We present quantification of WCET and average-case performance and discuss some of the performance loss on using only pure deterministic design.