{'fraction_non_alphanumeric': 0.013415892672858616, 'fraction_numerical': 0.008771929824561403, 'mean_word_length': 5.078369905956113, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Embedded Tutorial: Silicon Technology Impact on ESD Qualification

With the continued scaling of technologies the ESD qualification has become a major challenge. This is mainly due to the demand for higher speed circuits, mostly implemented in large high pin count packages, increased SoC applications, along with the newer features of the transistors such as FinFETs. This review paper will present the current perception about ESD and the industry wide thrust to change the ESD qualification requirements towards more realistic levels. Speaker Biography Charvaka Duvvury is a TI Fellow and an IEEE Fellow, working in the Technology Design and Integration Group. He is also a member of the Board of Directors for the ESD Association since 1997. He received his Ph.D. in Engineering Science from the University of Toledo. Since joining TI he was involved in numerous areas including DRAM Circuit Design, Transistor SPICE Modeling, Hot Carrier and ESD/Latchup Reliability. His current work is on development and company wide support on ESD for the nanometer submicron CMOS technologies. Charvaka is known across TI worldwide for his development work in CMOS ESD protection methods, for training and consulting to numerous design and product groups on ESD issues. He has received numerous Best Paper awards including the Outstanding Contributions Award from the ESD Association. He is also a recipient of the Outstanding Mentor Award from the Semiconductor Research Center during 1994 and 2012. He has published over 140 papers in technical journals and conferences and holds more than 70 patents. Charvaka is a cofounder and co-chair of the Industry Council on ESD Target Levels whose mission is to establish safe and realistic component ESD target levels while meeting the silicon technology challenges. Charvaka is an active participant of JEDEC activities and has been representing the Industry Council at both JEDEC and JEITA meetings.