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Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle

A radiation-hardness-by-design (RHBD) method for flip-flop single-event upsets (SEUs) mitigation is studied in this paper. This method applies a certain radiation hardened structure, e.g., the dual-interlocked storage cell (DICE), to implement one stage latch of a flip-flop while the SEUs protection for the other stage is realized by adjusting the clock duty cycle to shorten its hold state duration. Since the radiation hardening technique is used for only one stage latch, the overall area and power costs can be lowered. This technique is compatible with the automatic digital design flow and was implemented for an asynchronous first-in-first-out (FIFO) circuit as a case study in this paper.