{'fraction_non_alphanumeric': 0.032520325203252036, 'fraction_numerical': 0.008130081300813009, 'mean_word_length': 5.1826484018264845, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A self-timed dual-rail processor core implementation for microcontrollers

In recent years, microcontrollers are largely used in varieties of different systems, especially on small embedded systems, small device controllers, and e-devices. Different from general systems, processors inside these systems may not need very powerful computing capability; however, reliability, robustness, low EMI, and low power are the most important criteria. It is a well-known fact that asynchronous circuit can achieve these goals via removing the global clock in the synchronous circuit. However, it's very difficult to implement systems with asynchronous circuits. In 2009, we revealed an asynchronous microcontroller called NCTUAC18 which is compatible with Microchip's PIC18 ISA. It is a quasi-delay-insensitive (QDI) implementation. However, because of the DI /QDI nature, it is inflexible and thus it makes the circuit design even more difficult. In order to meet the DI/QDI constraints, it causes some limitations. To overcome these limitations, we propose a new pipeline model in this paper. Instead of original FPGA implementation, we synthesized the design with TSMC 0.13µm technology. The area and worst case delay are also shown in this paper. With our work, we demonstrate a possible implementation model of processor core with dual-rail Muller pipeline.