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A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation

In this paper, a third order continuous-time (CT) delta-sigma (ΔΣ) modulator in TSMC 65nm CMOS technology is presented. The digital excess loop delay (DELD) compensation for half a clock cycle which can be operated quite fast. Instead of using compensation in analog domain, the compensation is performed by means of using a high speed digital subtraction block which will result in low power dissipation. The modulator achieves 78.5dB SNDR and a 15 MHz bandwidth (BW) under 600MHz clock frequency. The power consumption equals 7.81mW drawn from a 1.2V supply voltage, which yields a state-of-the-art Walden figure of merit FOM of 39 fJ/conv-step.