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Idle time reduction in TDMP implementation of LDPC decoder

This article concerns the hardware iterative decoder for a subclass of LDPC (Low-Density Parity-Check) codes that are implementation oriented. They are known as Architecture Aware LDPC (AA-LDPC). The decoder has been implemented in a form of parameterizable VHDL description. To achieve high clock frequency of the decoder hardware implementation, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a heuristic algorithm for parity check matrix optimization to minimize the total number of required idle cycles and hence maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties, however the decoder throughput can be significantly increased.