{'fraction_non_alphanumeric': 0.023952095808383235, 'fraction_numerical': 0.0, 'mean_word_length': 5.972222222222222, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
An improved quad Itoh-Tsujii algorithm for FPGAs

In this paper, we propose an improved quad Itoh-Tsujii algorithm to compute multiplicative inverse efficiently on Fieldprogrammable gate-arrays (FPGA) platforms for binary fields generated by irreducible trinomials. Efficiency is obtained by eliminating the precomputation steps required in conventional quad-ITA (QITA) scheme. Experimental results show that the proposed architecture improves the performance on FPGAs compared to existing techniques.