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Performance analysis of asynchronous dual mode logic using leakage power reduction techniques

In VLSI circuit power reduction is of major concern. Considerable research is carried out in literature to develop techniques to reduce both dynamic power and leakage power. However attempts are still in progress to reduce the power without degrading the performance of the circuit in terms of speed and accuracy. In this paper a novel DML approach is adopted in the design of a low power asynchronous circuit and the power consumed is measured. It is found that the adopted technique resulted in 40% reduction of the wasted power.