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Automatic visual inspection of integrated circuits using a SEM

In this thesis, we investigate the complex problem of designing an integrated circuit inspection system that will be used in controlling an automated semiconductor manufacturing facility. Such a system will have to be accurate, fast and be able to inspect integrated circuits with submicron features. To satisfy the accuracy requirements, we propose a system that integrates information supplied by multiple intelligent (virtual) sensors. Most of our work concentrates on the design of two, scanning electron microscope (SEM) based, intelligent sensors. One of them extracts 3D IC surface topography information using computer stereo vision techniques and the other identifies shape defects in IC patterns using the IC design file as the reference. Both of these problems are viewed as constrained contour matching problems. In stereo matching, we match feature contours extracted from the left and right stereo images where as in pattern shape inspection we match pattern boundary contours extracted from the image and the IC design file. We present an optimization technique for solving the matching problem that results in both cases. This general approach simplifies the task of transforming the specifications of a physical problem into a computational form and results in a modular system. Based on several experiments, we achieve stereo matching error rates of less than 5%. To meet the speed requirements of the inspection system, we discuss the parallel implementation of our algorithms on readily available, multiple instruction multiple data (MIMD) processors. We show how these processors can efficiently solve not only low level vision problems but also higher level problems (formulated as global optimization problems.)