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High order correction and sampling strategy for 45nm immersion lithography overlay control

As advanced semiconductor companies move forward to the 45nm technology node, traditional overlay sampling and linear correction used in dry lithography become less feasible to bring overlay control into the desired budget. New overlay control methodologies need to be established to meet the needs of much tighter overlay budgets in the immersion lithography process. Overlay source of variance (SOV) was first investigated to understand the major contributor of overlay error sources. The SOVis broken down into wafer, field, and random components in order to utilize the SOV information to prioritize overlay improvement decisions. High order wafer level or field level error components are commonly observed as a significant contributor and requires attention to bring the overlay residual into the desired limit. Optimal sample is determined in considering sample plan robustness and throughput impact while increasing sampling becomes a necessity in 45nm technology node.