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A novel leakage power reduction technique for nano-scaled CMOS digital integrated circuits

In this paper, we present a method to improve the efficacy of a famous leakage reduction technique known as gate length biasing. In proposed method, gate length biasing is combined with progressive sizing. The method greatly reduces both the leakage power consumption and its spread without a significant delay overhead. In addition, it does not increase the complexity of the design. To assess the efficacy of this method, leakage power consumptions of several benchmark circuits optimized by our method and conventional gate length biasing techniques are compared. The circuits are implemented in a 65nm standard CMOS technology. The simulation results reveal that the proposed method reduces the nominal standby leakage power consumption and its spread by 20% and 18%, respectively, with 2–6% delay increase on average.