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Extended tensor description to design non-uniform heat-removal in interlayer cooled chip stacks

Interlayer cooling is a heat removal concept that scales with the number of stacked tiers. Uniform fluid cavities result only in moderate heat removal performance. A substantial improvement could be expected for nonuniform, hot-spot-aware fluid cavities. Hence, we propose an extension of our multi-scale modeling framework to support nonuniform fluid cavity designs. The chip stack with its cavities and the silicon dies are represented by field-coupled porous and solid domains, respectively. Detailed sub-domain modeling using two pairs of periodic boundary conditions for fully and half populated pin-fin arrays with 100 μm height and pitch was performed. Permeability and convective thermal resistance values with respect to arbitrary flow directions were extracted. These values are used in the chip stack model to predict the mass and the energy transport within the fluid cavity and between the domains, respectively. Three mathematical permeability descriptions are benchmarked against each other and are experimentaly validated. The extended tensor description predicts the mass flow and maximum junction temperature best at an accuracy of better than 20%. We could also demonstrate the extension of interlayer cooling to TSV pitches of 50 μm with hot-spot heat fluxes of up to 250W/cm2 by pin-fin-density modulation and four-port fluid delivery.