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Transition analysis on FPGA for multiplier-block based FIR filter structures

This paper presents a study on the power consumption analysis of several multiplier-block based FIR filter structures. Transitions have been counted for the filter structures that were implemented on an FPGA device. The algorithms employed to generate the multiplier-blocks are compared with respect to their power performance. A new term, Glitch Path count, has been proposed and tested for use as an indicator of power consumption. This measure has been shown to be more correlated with the transition counts than the adder-count and logic depth approaches.