{'fraction_non_alphanumeric': 0.020319303338171262, 'fraction_numerical': 0.0, 'mean_word_length': 5.216216216216216, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Multi-Layer Perceptron Hardware Accelerator on RISC-V Processor

The need for domain-specific hardware architectures of neural network models is increasing with the rapid development of autonomous cars, robotics and IOT. For these data-driven systems, new fast and efficient hardware methodologies are introduced recently. In this study, a comparison between general purpose RISC-V processor and customized version of it will be presented. Customized version consists of local memory structure, special float computing unit and an interface to communicate with core. It is aimed to show by using the strong sides of these two hardware more efficient and fast architectures can be achieved.