{'fraction_non_alphanumeric': 0.0367170626349892, 'fraction_numerical': 0.023758099352051837, 'mean_word_length': 4.867088607594937, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad standard

This paper presents an area-efficient multi-Gbps multi-mode LDPC decoder architecture for 60GHz wireless gigabit communications. A novel, low-complexity local switch is proposed to implement the multi-mode dynamic column-shifting scheme. Furthermore, the usage of a one's-complement instead of a two's-complement number system is explored. Moreover, an efficient quantization method is also presented to reduce the memory and area requirement of the decoder. The synthesis and layout is performed using TSMC 65-nm CMOS technology. Post layout results show that the proposed decoder requires only 0.575 mm2 of area to achieve a throughput of 9.25 Gb/s for all code rates defined under IEEE 802.11ad. The proposed architecture shows much better throughput, as well as better area- and energy-efficiency, compared to other multi-mode LDPC architectures.