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A Method to Reuse RTL Verification Tests to Validate Cycle Accurate Model

Testing C/C++ based high abstracted software simulation models for complex functional and timing accuracy has always been a tedious process. Typically test cases development itself takes very high amount of time as it involves in-depth study of design and manual validation of stimulus. Writing similar tests in hardware description language is easier as design itself is low abstracted and language supports required timing constructs. In software modeling world, a model is mostly at transaction level while the timing details available from documents always talk in terms of pins and signals. Mapping those to a different abstraction level demands huge efforts and requires rigorous validations. What if there is a way to do this mapping automatically? If we can convert RTL tests into a format which is understood and usable by models, that would solve this daunting problem of writing and validating test cases. This paper talks about such an approach where we leverage highly verified RTL tests written at low abstraction level, for functional and timing testing of C++ models written at much higher abstraction level. The traffic of RTL test is recorded during test run and processed to create transactions for model. This methodology provides readymade high-fidelity non-trivial stimulus for models thus utilizing the efforts spent by RTL verification teams and saving time of model tester in creating similar tests, at the same time ensuring quality delivery and promising lesser bugs reporting from end users.