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Parallel implementation of genetic algorithm on FPGA using Vivado high level synthesis

Genetic algorithm (GA) is one of most popular evolutionary search algorithms that simulates natural selection of genetic evolution for searching solution to arbitrary engineering problems. However, it is computationally intensive and will become a limiting factor for evolving solution to most of the real life problems as it involves large number of parameters that needs to be determined. Fortunately, there are some parallel platforms such as field programmable gate array (FPGA) that can be adopted to overcome this constrains by improving its latency. So, efficient parallel implementation of GA was proposed where each step of GA was exploited to improve its computational task. Moreover, many optimization and parallelisation techniques were adopted and applied to achieve high speed up. The results show that 43 speed up is achieved compared with the typical one. Moreover, higher speed up can be achieved with larger input size.