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Memory-Aware Warp Scheduling

1. ABSTRACT A modern Graphics Processing Unit (GPU) is characterized by numerous programmable computational cores and thousands of simultaneously active fine-grained threads. These threads are grouped into thread blocks, also known as cooperative thread arrays (CTAs). All the threads within a CTA are scheduled on the same core at the granularity of warps. In spite of having numerous resident threads and theoretically high thread-level parallelism (TLP), GPU cores still suffer from high periods of idle times, resulting in under-utilization of hardware resources. These idle times are primarily a result of the inability of the commonly-employed warp scheduling policies in facilitating a GPU core to completely tolerate the long memory fetch latencies, which are primarily attributed to: (1) contention in caches caused by multiple concurrent threads, (2) DRAM contention caused by various concurrent threads from multiple GPU cores, and (3) limited offchip DRAM bandwidth available in GPUs. The commonlyemployed warp scheduling policies, for example, round-robin (RR) scheduler is shown to be ineffective in alleviating all these three sources of long memory fetch latencies [3–5]. Although the recently-proposed two-level warp scheduler [5] performs better than the RR scheduler on all three aspects, it is far from optimal [2–4]. The cache-conscious warp scheduler [6], developed concurrently with our ASPLOS 2013 paper, was shown to outperform both the two-level and RR schedulers, but it addresses contention in only caches, not in DRAM. In this paper, we propose a comprehensive c(O)operative