{'fraction_non_alphanumeric': 0.024242424242424242, 'fraction_numerical': 0.0015151515151515152, 'mean_word_length': 5.031963470319635, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Gate Capacitance Modeling and Diameter-Dependent Performance of Nanowire MOSFETs

We investigated the diameter-dependent performance of Si and InAs nanowire metal-oxide-semiconductor field-effect transistors (NW MOSFETs) by developing a gate capacitance model. A nonparabolic effective-mass approximation and a semiclassical ballistic transport model were used. The capacitance model helped interpret the different contributions of the capacitances, which were due to the inversion-layer centroid and density of states. As a result, the inversion-layer centroid was close to the surface with a shrinking diameter. In Si NWs, this effect increased the gate capacitance in a small diameter. On the other hand, in InAs NWs, the density of states could decrease the gate capacitance in a small diameter. In both NWs, the on-current drastically increased in diameter smaller than 5 nm mainly due to the increase in the gate capacitance. The diameter-dependent injection velocity reached a peak around 5 nm in both NWs. Our results could imply that the peak in the diameter-dependent injection velocity is a universal feature of NW MOSFETs. With respect to intrinsic gate delay, the highest injection velocity led to the best performance of Si NWs; however, this case was not accompanied with the best performance of InAs NWs.