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An Early Stage Design Flow for Switching Noise Attenuation

In the design of highly complex integrated circuits (ICs), switching noise is a raising problem. To handle this, current shaping techniques are applied to reduce current peaks causing ground bounce and voltage drops. Such techniques distribute the switching activity by adding phases and/or jitter to the clock of different domains. However, they are usually performed at later phases of the design process, i.e., in the chip layout. In this phase, the timing margins of the logic paths are typically fixed, which limit the clock phases that can be introduced between the domains. In this paper, we present a novel design preconditioning flow, which addresses the optimization of power noise characteristics of a design already at the frontend level. This allows early RTL-level design modifications, e.g., clock inversion or pipeline stage insertion, which potentially facilitate noise mitigation or enhance clock skewing in later design stages.