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Matrix multiplications on the memory based processor array

A memory based processor array (MPA) for matrix multiplications is designed as an effective array architecture. Also a mapping algorithm to implement matrix multiplication on the MPA system is proposed. One outstanding feature of the MPA system is that it can be easily integrated into any host system via memory interface. Specifically, the MPA system provides an efficient mechanism for its local memory accesses allowed by the row basis and the column basis using the hybrid row and column decoding, which is suitable for matrix multiplications. An important factor to improve performance in the processor array is to reduce the communication time among processing units and this can be achieved through efficient memory structure. The proposed architecture and its corresponding algorithm are turned out to be better than others by performance evaluation. And the MPA system also provides a new platform for computing a variety of linear algebra applications.