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Study of Full-Duplex Communication with Excellent Security by 3-Level Communication Method

Currently, the industry is using the MODBUS communication method, utilizing RS485 for the distributed equipment and network construction. This method has a rather good transmission and reception distance but has a disadvantage in that it is a half-duplex communication method that cannot simultaneously transmit and receive. Therefore, there is a great need for a full-duplex communication system that can simultaneously transmit and receive two-wire communications. Therefore, in this paper, we propose new communication hardware equipment that can implement a full-duplex communication method by communication signal level in order to overcome the disadvantage of communication speed when using a full-duplex communication method by time division method. The proposed communication hardware is a structure that can transmit and receive at the same time in such a way that two pieces of equipment communicating by two-wire communication can apply the outgoing signal to the same communication line and detect the received signal at the same time. Therefore, the receiving side can analyze the received signal based on the information on the current transmission signal. This signal can only be analyzed by the two communicating devices, indicating that communication security is very good.

communication line is long. Thus, it is urgently necessary to investigate a full-duplex communication method that can transmit and receive in a two-wire communication [8][9][10]. Thus, this study proposes new hardware equipment for communication which can implement a full-duplex communication method in the level of the communication signal to overcome the disadvantage in communication speed in using a full-duplex communication method by a time-sharing system. The proposed communications hardware is a structure that can transmit and receive simultaneously in a way that can detect the received signal, while at the same time, two pieces of equipment (which communicate with the two-wire communication) authorize a transmission signal to the communication line [11][12][13]. The characteristics of this communications hardware involve a 2-level signal for data transmission that is generated in the transmission equipment, while in the receiver, a 3-level electrical signal is generated according to the status of the transmission data generated in it. This signal is characterized by its simultaneous inclusion of the data transmission signal of the transmission equipment and the data transmission signal of the receiver [14,15]. Therefore, the reception equipment can analyze the received signal through information about the present transmission signal. Since the signal can only be analyzed by the two devices that communicate, it is notably very excellent in terms of communication security.

Comparison of the Characteristics of the Existing Asynchronous Communication Method
In industrial settings, the 1:1 connection for communication to share information between devices, the full-duplex method and the RS232C communication method, which can simultaneously transmit and receive in a 3-wire communication, is employed, as shown in Figure 1(a). However, if several devices are connected together, RS485/422 communication is often employed. In this case, several units can be connected to the communication line with a single port due to the cost increases, since the RS232C communication method requires multiple communication ports [16,17].  Table 1 compares the characteristics of the representative asynchronous communication methods of RS232 communication with those of RS485 communication. In the RS485 method, the maximum output voltage is lower than that in the RS232 method, but due to the differential input, the maximum distance range and the highest communication speed are excellent; however, it has the disadvantage of being a half-duplex communication method, which cannot simultaneously transmit and receive in communication [18][19][20][21]. Unlike this, the RS232 method has the advantage of being a full-duplex method, which can transmit and receive at the same time; however, it has the disadvantage of being a three-wire method, in which there is a wire for transmission and a wire for reception.  Table 1 compares the characteristics of the representative asynchronous communication methods of RS232 communication with those of RS485 communication. In the RS485 method, the maximum output voltage is lower than that in the RS232 method, but due to the differential input, the maximum distance range and the highest communication speed are excellent; however, it has the disadvantage of being a half-duplex communication method, which cannot simultaneously transmit and receive in communication [18][19][20][21]. Unlike this, the RS232 method has the advantage of being a full-duplex method, which can transmit and receive at the same time; however, it has the disadvantage of being a three-wire method, in which there is a wire for transmission and a wire for reception.
The RS232 communication method and the RS485 communication method have the disadvantage of being very vulnerable in terms of communication security since it is easy to leak the communications protocol by installing an analyzer of communication data on the communication line. In other words, if both Q 1 and Q 2 are off, the output is the high impedance status, which cannot make the transmission function in the communication line. If Q 1 is on, and Q 2 is off, the binary value '1' of serial communication is transmitted, V s becomes V dc , and if Q 1 is off, and Q 2 is on, the binary value '2' of serial communication is transmitted, V s becomes 0. However, V L voltage appears to be 3-level by the output level of the other party due to the output impedance resistance [22][23][24][25].  In other words, if both Q1 and Q2 are off, the output is the high impedance status, which cannot make the transmission function in the communication line. If Q1 is on, and Q2 is off, the binary value '1' of serial communication is transmitted, Vs becomes Vdc, and if Q1 is off, and Q2 is on, the binary value '2' of serial communication is transmitted, Vs becomes 0. However, VL voltage appears to be 3-level by the output level of the other party due to the output impedance resistance [22][23][24][25].  It is presumed that, since in the proposed topology, the output impedance is larger than that on the communication line, the impedance on the communication line is ignored. VS1 and VS2, reception voltages on Side A and Side B are not determined by the voltage on the transmission side or reception side, but determined by both the voltage on the transmission side and the reception side. In other words, if the voltage on both transmission sides is the same, the transmission voltage is detected, and if it is different, the whole transmission voltage is detected. By this logic structure, the output voltage on the receiving end becomes 3-level according to the transmission information on the transmission side and the reception side. Therefore, the reception information can be obtained by combining the reception information and the transmission information in which the 3-level voltage has been formed according to the transmission status on the transmission side and the reception side.  It is presumed that, since in the proposed topology, the output impedance is larger than that on the communication line, the impedance on the communication line is ignored. V S1 and V S2 , reception voltages on Side A and Side B are not determined by the voltage on the transmission side or reception side, but determined by both the voltage on the transmission side and the reception side. In other words, if the voltage on both transmission sides is the same, the transmission voltage is detected, and if it is different, the whole transmission voltage is detected. By this logic structure, the output voltage on the receiving end becomes 3-level according to the transmission information on the transmission side and the reception side. Therefore, the reception information can be obtained by combining the reception information and the transmission information in which the 3-level voltage has been formed according to the transmission status on the transmission side and the reception side.    Figure 5 shows the waveform of operation in the general 485 mode, in which Side B generates transmission information while Side A only receives it. This is a 2-level communication mode in which the voltage on the transmission side and that on the reception side appear to be the same. As seen in Figure 5, the output voltage on Side B, VS2 and the reception voltage on Side A, VL1 become the same form, and the inclusive-OR of the outputs of the two comparators, DH1 and DL1 always become 0. In addition, the exclusive-OR of voltage LL1 and the reception signal, which is always 0 appears as the reception signal.      Figure 5 shows the waveform of operation in the general 485 mode, in which Side B generates transmission information while Side A only receives it. This is a 2-level communication mode in which the voltage on the transmission side and that on the reception side appear to be the same. As seen in Figure 5, the output voltage on Side B, VS2 and the reception voltage on Side A, VL1 become the same form, and the inclusive-OR of the outputs of the two comparators, DH1 and DL1 always become 0. In addition, the exclusive-OR of voltage LL1 and the reception signal, which is always 0 appears as the reception signal.  Figure 5 shows the waveform of operation in the general 485 mode, in which Side B generates transmission information while Side A only receives it. This is a 2-level communication mode in which the voltage on the transmission side and that on the reception side appear to be the same. As seen in Figure 5, the output voltage on Side B, V S2 and the reception voltage on Side A, V L1 become the same form, and the inclusive-OR of the outputs of the two comparators, D H1 and D L1 always become 0. In addition, the exclusive-OR of voltage L L1 and the reception signal, which is always 0 appears as the reception signal.   Figure 6 shows the waveform if it is operated in the simultaneous full-duplex communication mode, in which Side B generates transmission data while Side B also generates a transmission signal. To interpret it clearly, the two transmission signals, VS1 and VS2 were defined as those having a 90-degree phase contrast like the figure. In this case, the voltage on the transmission side and that on the reception side appears at different levels with the other party's information on the transmission side. As seen in Figure 6, the voltage received on Side A, VL1 is formed like the figure by the voltage transmitted on Side A, VS1 and the voltage transmitted on Side B, VS2, and the inclusive-OR of the outputs of two comparators, DH1 and DL1 appears two times in the transmission frequency. Thus, the exclusive-OR of voltage LL1 and reception signal VL1 is the same as the transmission voltage on Side B, VS2. Thus, you can output the desired reception signal from the 3-level reception signals.  Figure 6 shows the waveform if it is operated in the simultaneous full-duplex communication mode, in which Side B generates transmission data while Side B also generates a transmission signal. To interpret it clearly, the two transmission signals, V S1 and V S2 were defined as those having a 90-degree phase contrast like the figure. In this case, the voltage on the transmission side and that on the reception side appears at different levels with the other party's information on the transmission side. As seen in Figure 6, the voltage received on Side A, V L1 is formed like the figure by the voltage transmitted on Side A, V S1 and the voltage transmitted on Side B, V S2 , and the inclusive-OR of the outputs of two comparators, D H1 and D L1 appears two times in the transmission frequency. Thus, the exclusive-OR of voltage L L1 and reception signal V L1 is the same as the transmission voltage on Side B, V S2 . Thus, you can output the desired reception signal from the 3-level reception signals.   Figure 6 shows the waveform if it is operated in the simultaneous full-duplex communication mode, in which Side B generates transmission data while Side B also generates a transmission signal. To interpret it clearly, the two transmission signals, VS1 and VS2 were defined as those having a 90-degree phase contrast like the figure. In this case, the voltage on the transmission side and that on the reception side appears at different levels with the other party's information on the transmission side. As seen in Figure 6, the voltage received on Side A, VL1 is formed like the figure by the voltage transmitted on Side A, VS1 and the voltage transmitted on Side B, VS2, and the  Figure 7 is a simulation circuit diagram to test the validity of the communication method proposed in this study. The simulation circuit consists broadly of a half-bridge inverter to generate a communication signal, a comparator to detect 3-level, a logical circuit diagram, and the DLL part to generate a series transmission signal by Visual C language.    Figure 6, that is, the two transmission signals on Side A and Side B have a 90-degree phase contrast. In this case, the voltage on the transmission side and that on the reception side appear at different levels; however, a waveform the same as that in Figure 6 appears, and it was noted that Side A perfectly receives the signal transmitted on Side B.   Figure 6, that is, the two transmission signals on Side A and Side B have a 90-degree phase contrast. In this case, the voltage on the transmission side and that on the reception side appear at different levels; however, a waveform the same as that in Figure 6 appears, and it was noted that Side A perfectly receives the signal transmitted on Side B. Figure 9 is  Figure 9 is the result of a simulation to check asynchronous serial communication, in which Side A transmitted the character, 'U' by ASCII Code and Side B transmitted the character, 'U' by ASCII Code, setting 9600bps, 8-bit data, 1 stop bitter and no-parity.

Result of Simulation
As seen in the figure, as a VS1 series signal on Side A, ASCII Code character 'U' is generated,    Figure 10 is a new communication prototype in the 3-level method, which can transmit and receive simultaneously in two-wire communication. This prototype consists broadly of the SMPS part with 9-36 V input range, gate amp part, half-bridge equipment to generate a communication signal, and the comparison equipment and the logic equipment, which receive 3-level input and convert it to 2-level reception information.  Figure 11 is the result of an experiment in which Side B generates ASCII Code 'C' communication data while Side A only receives them, which is the general communication method. As seen in the resulting waveform of Figure 11, this communication method is compatible with the existing communication method.  Figure 12 is the result of an experiment of communication in the same status as the simulation condition of Figure 9. As shown in the resulting waveform of Figure 12, the two transmitters transmit the same data, but the asynchronous communication method is different, so the three-level  Figure 11 is the result of an experiment in which Side B generates ASCII Code 'C' communication data while Side A only receives them, which is the general communication method. As seen in the resulting waveform of Figure 11, this communication method is compatible with the existing communication method.  Figure 10 is a new communication prototype in the 3-level method, which can transmit and receive simultaneously in two-wire communication. This prototype consists broadly of the SMPS part with 9-36 V input range, gate amp part, half-bridge equipment to generate a communication signal, and the comparison equipment and the logic equipment, which receive 3-level input and convert it to 2-level reception information.    Figure 12 is the result of an experiment of communication in the same status as the simulation condition of Figure 9. As shown in the resulting waveform of Figure 12, the two transmitters transmit the same data, but the asynchronous communication method is different, so the three-level  Figure 12 is the result of an experiment of communication in the same status as the simulation condition of Figure 9. As shown in the resulting waveform of Figure 12, the two transmitters transmit the same data, but the asynchronous communication method is different, so the three-level voltage appearing on the communication line is different. However, it was found that the received data correctly received the transmitted data.

Result of Exiperiment
voltage appearing on the communication line is different. However, it was found that the received data correctly received the transmitted data.

Conclusions
In this paper, we propose new communication hardware equipment capable of implementing a full-duplex communication method at the same time, apart from the full-duplex communication method by the time division method.