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Design of linear ramp generator for ADC

In recent years, the electronic systems become more complex due to high integration of multi-system functionalities with deep submicron technologies. Also, the insistent requirements of analog and mixed-signal circuits like precision output and observability of logic functions are limited due to the high integration density and limited availability of input-output pins. And it makes the testing of analog and mixed signal circuit as complex and expensive. This work presents an efficient on-chip ramp generator is to correlate the placement of built-in-self-test techniques for ADC static linearity testing. The significant contributions of this work are design of a ramp generator, integration of ramp generator with ADC for testing using tanner.