{'fraction_non_alphanumeric': 0.023291925465838508, 'fraction_numerical': 0.0, 'mean_word_length': 5.649484536082475, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
The implementation of digital protection in power system using FPGA

This paper presents the Application Specific Integrated Circuit (ASIC) implementation of the digital protective relays in power distribution system. It was achieved using Electric Design Automation (EDA) techniques. This design was simulated and then implemented into two Field Programmable Gate Arrays (FPGAs). The complete protective relay including the data acquisition, data processing, protections group, communication part and task scheduler part. This is a typical system on chip design. The experimental results show that the proposed scheme gives a good performance.