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Die matching algorithm for enhancing parametric yield of 3D ICs

This paper addresses the problem of selecting (i.e., matching) dies to be bonded together in 3D IC design to improve parametric yield, producing 3D chips that are highly tolerant to the on-package induced timing variation. For two-layered 3D ICs, the corresponding two-dimensional die-to-die matching problem can be formulated into the maximum bipartite matching problem which is solvable optimally in polynomial time. However, for 3D ICs with K(>; 2) layers, the corresponding K-dimensional die-to-die matching problem is known intractable. The previous approach applies the optimal two-dimensional matching algorithm repeatedly to find a solution of the K-dimensional die matching problem. The inherent limitation of the previous approach is that each of the optimal two-dimensional matchings applied in the iteration process is completely isolated and localized, resulting in globally unoptimized K-dimensional matching solutions. This work overcomes this limitation. Precisely, we propose a new enhanced two-dimensional die matching formulation based on finding a maximum flow of minimum cost in a network, which can be solved optimally in polynomial time while facilitating finding globally improved K-dimensional matching solutions when it is iteratively applied. From experimental results with benchmark circuits, we confirm that our proposed algorithm is able to find solutions that produce 5%, 8%, and 12% improved parametric yield for 3-layered, 4-layered, and 5-layered 3D ICs compared to the results of previous work, respectively.