{'fraction_non_alphanumeric': 0.01440922190201729, 'fraction_numerical': 0.0, 'mean_word_length': 5.261261261261262, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
An access pattern based energy management strategy for instruction caches

Increasing leakage energy consumption is an important problem for SOC-based platforms as such platforms rely on large on-chip SRAMs. While most of the previous techniques focus on hardware based leakage optimization, in this paper, we present an application access pattern oriented strategy for reducing instruction cache leakage energy. This strategy keeps track of the dynamic transitions between the procedures of a given application, and tries to keep the cache lines not used by the current procedure in a power-down state as much as possible. Our simulation results indicate significant savings in leakage energy.