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High performance MAC unit for DSP and cryptographic applications

Multiplication and addition are the basic arithmetic operation used in Digital Signal Processing (DSP) for coefficient multiplication, scalar point multiplication in Elliptic Curve Cryptography (ECC) and in other fields. Multiplications are basically a shift and add operation. However, there are many different variations on how to do it. Some are more suitable to implement on FPGA than others. However time complexities and hardware complexities are the major issues in designing a multiplier unit. There are different multiplication algorithms in current technology. Hardware complexities in some design are more than time complexities whereas in some other design time complexities are more. However there must be a tradeoff between these two types of methodology. This paper will discuss a brief idea how a tradeoff can be achieved. Experimental results that have discussed here and the architecture based on the proposed algorithm shows it's novelty. Applications of the proposed algorithm on DSP and ECC have been dealt here clearly.