{'fraction_non_alphanumeric': 0.017488076311605722, 'fraction_numerical': 0.006359300476947536, 'mean_word_length': 5.052884615384615, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Scheme for variable-frequency digital circuit with data compression based on block-match process

In order to find a way to solve the contradiction among storage space, transmission capacity and the data volume in the embedded systems, a data compression scheme based on block matching with an identifier is presented by using the technology of digital integrated circuit. The scheme can achieve lossless real-time data compression and reduce the volume of the data. Through statistical analysis on the data source, the authors can obtain that such a scheme has many advantages in real-time performance, a complication of implement, efficiency and practicability. So the digital circuit is considered as a method which can present the encoding process. With the help of QUARTUS II, they combine Verilog and schematic to finish the design hierarchically and code the decompression program by using C language for comparison. The accuracy and efficiency of the circuit are verified with simulation and relevant experiments. The average compression rate is 52.3% with 12 MHz clock frequency and the compression speed on average is 352% faster than the one by using block-match software algorithm. The scheme would have good performance in many embedded systems.