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Design for Ultrahigh-Density Vertical Phase Change Memory: Proposal and Numerical Investigation

The integration level is a significant index that can be used to characterize the performance of non-volatile memory devices. This paper proposes innovative design schemes for high-density integrated phase change memory (PCM). In these schemes, diploid and four-fold memory units, which are composed of nano-strip film GST-based memory cells, are employed to replace the memory unit of a conventional vertical PCM array. As the phase transformation process of the phase change material involves the coupling of electrical and thermal processes, an in-house electrothermal coupling simulator is developed to analyze the performance of the proposed memory cells and arrays. In the simulator, a proven mathematical model is used to describe the phase change mechanism, with a finite element approach implemented for numerical calculations. The characteristics of the GST-strip-based memory cell are simulated first and compared with a conventional vertical cell, with a decrease of 32% in the reset current amplitude achieved. Next, the influences of geometric parameters on the characteristics of memory cell are investigated systematically. After this, the electrothermal characteristics of the proposed vertical PCM arrays are simulated and the results indicate that they possess both excellent performance and scalability. At last, the integration densities of the proposed design schemes are compared with the reference array, with a maximum time of 5.94 achieved.