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A Delay-Aware Implementation Scheme for Cost-Effective Implication-Based Concurrent Error Detection

Implications have been shown to be beneficial for both concurrent error detection and diagnosis. To reduce the incurred hardware cost, one critical issue is selection of a minimum number of appropriate implications. Although the previous work developed several implication selection algorithms, the critical path delay may still be high. This is because the factors related to the critical path delay have not been well studied and considered during implication selection. In this paper, we investigate these factors and develop a new delay-aware implication selection algorithm. A buffer insertion algorithm is also developed such that the minimum number of buffers are inserted to further reduce the delay. This algorithm is integrated with the implication selection algorithm as a delay-aware implementation scheme. Experimental results on 18 ISCAS'85 and ITC'99 benchmark circuits show that 29.02% delay overhead reduction is achieved on average with only additional 0.34% implications selected.