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Circuit Design for Bias Compatibility Investigation of Bulk FinFET Based Floating Body RAM

Single transistor Floating Body Random Access Memories (FB-RAMs) are foreseen to bring size and speed benefits and have the potential to replace existing DRAMs. However, the implementation in matrix is complex because the voltages applied to access one cell can disturb the state of other cells. We propose an approach at circuit level to provide compatible bias conditions and to explore further on the optimization of the biasing voltages for improved write and read operations and improved retention. To do so we use synchronized bitline and wordline drivers providing different voltages to selected and unselected lines during the different operations. In addition, a robust sensing scheme is described that can be implemented in the same process technology as the array. The full circuit has been validated by simulations based on the experimental data of fabricated bulk FinFETs floating body cells and the design has been taped out.