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Towards Ideal Arbiter PUF Design on Xilinx FPGA: A Practitioner's Perspective

Despite the perceived lightweight and structural regularity of Arbiter PUF (APUF), high quality (bias-free) large APUF implementation on FPGA has traditionally proved to be challenging. Currently, the most widely accepted design approach for FPGA-based APUF implementation is the Programmable Delay Line (PDL) based APUF. In this work, we describe a scalable design methodology to implement close-to-ideal APUF on Xilinx FPGA using the standard Xilinx CAD tool flow. The main insight is to exploit the Hard Macro feature of the Xilinx design flow to design bias-free symmetric delay paths. We have demonstrated the effectiveness and superiority of our design to previously proposed PDL-based PUFs through implementation and characterization results.