{'fraction_non_alphanumeric': 0.02067539627842867, 'fraction_numerical': 0.011026878015161957, 'mean_word_length': 5.178723404255319, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
VHDL implementation of wavelet packet transforms using SIMULINK tools

The wavelet transform is currently being used in many engineering fields. The real-time implementation of the Discrete Wavelet Transform (DWT) is a current area of research as it is one of the most time consuming steps in the JPEG2000 standard. The standard implements two different wavelet transforms: irreversible and reversible Daubechies. The former is a lossy transform, whereas the latter is a lossless transform. Many current JPEG2000 implementations are software-based and not efficient enough to meet real-time deadlines. Field Programmable Gate Arrays (FPGAs) are revolutionizing image and signal processing. Many major FPGA vendors like Altera and Xilinx have recently developed SIMULINK tools to support their FPGAs. These tools are intended to provide a seamless path from system-level algorithm design to FPGA implementation. In this paper, we investigate FPGA implementation of 2-D lifting-based Daubechies 9/7 and Daubechies 5/3 transforms using a Matlab/Simulink tool that generates synthesizable VHSIC Hardware Description Language (VHDL) code. The goal is to study the feasibility of this approach for real time image processing by comparing the performance of the high-level toolbox with a handwritten VHDL implementation. The hardware platform used is an Altera DE2 board with a 50MHz Cyclone II FPGA chip and the Simulink tool chosen is DSPBuilder by Altera.