{'fraction_non_alphanumeric': 0.04477611940298507, 'fraction_numerical': 0.012629161882893225, 'mean_word_length': 5.0137931034482754, 'pattern_counts': {'":': 0, '<': 1, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A novel sub-10 ps resolution TDC for CMOS SPAD array

In this work, we present a novel Time-to-Digital Converter (TDC) for single-chip integration in Single-Photon Avalanche-Diode (SPAD) array and digital Silicon Photomultiplier (SiPM). Such novel detector-timing electronics combination will be suitable for Time-Correlated Single-Photon Counting (TCSPC) applications and direct Time-Of-Flight (TOF) measurements. The proposed TDC is based on a 200 MHz 4-bit counter that guarantees a Full-Scale Range of 80 ns. Two interpolators exploit the sliding scale technique to reduce the Differential Non-Linearity (DNL). Besides the coarse interpolation, the multi-stage interpolators have a novel dual-fine interpolation that guarantees a resolution as good as 7 ps, with a conversion time (< 50 ns) much shorter compared to typical architectures based on Vernier delay lines.