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Excellence of Gate Oxide Integrity in Metal-Oxide-Semiconductor Large-Scale-Integrated Circuits Based on P-/P- Thin-Film Epitaxial Silicon Wafers

The substitution of Czochralski (CZ)-silicon (Si) wafers into p-(n-)/p-(n-) ( p- or n- layer on p- or n- Si substrate: resistivity of approximately 100 m Ω m) thin-film epitaxial Si wafers used as starting materials has been investigated with respect to application to metal-oxide-semiconductor (MOS) large-scale-integrated circuits (LSIs). The optimum epitaxial layer ( p-/p- structure) thickness for MOS-LSIs was determined to be approximately 1 µ m from the viewpoints of gate oxide integrity (GOI) improvement and cost effectiveness. With increasing epitaxial layer thickness from 0.1 to 0.3 µ m, the oxide defect density was greatly reduced and leveled off at approximately 1/30 that of a CZ-Si layer if the layer thickness is above 0.3 µ m. This is because microdefects in CZ-Si represented by crystal originated particles (COP) which cause weak spots in the gate oxide layer are covered by an excellent Si epitaxial layer on the CZ-Si surface. The p-/p- thin epitaxial structure results in very controlled resistivity for electrically active regions in the device, resulting in a lower cost of growth.