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Contact resistance extraction of graphene FET technologies based on individual device characterization

Straightforward contact resistance extraction methods based on electrical device characteristics are described and applied here to graphene field-effect transistors from different technologies. The methods are an educated adaptation of extraction procedures originally developed for conventional transistors by exploiting the drift-diffusion-like transport in graphene devices under certain bias conditions. In contrast to other available approaches for contact resistance extraction of graphene transistors, the practical methods used here do not require either the fabrication of dedicated test structures or internal device phenomena characterization. The methodologies are evaluated with simulation-based data and applied to fabricated devices. The extracted values are close to the ones obtained with other more intricate methodologies. Bias-dependent contact and channel resistances studies, bias-dependent high-frequency performance studies and contact engineering studies are enhanced and evaluated by the extracted contact resistance values.


Introduction
Graphene (G) field-effect transistors (FETs) have been demonstrated to be suitable candidates for low-power high-frequency (HF) applications in both rigid and flexible substrates [1]. Despite the early stage of this technology, extrinsic cutoff and maximum oscillation frequencies of tens of GHz have already been reported in fabricated GFETs [2]- [6]. In addition to other technological issues to be overcome, the metal-graphene interface in GFETs needs to be further optimized towards exploiting the graphene intrinsic properties, e.g., high velocity saturation and high mobility, at a device level, towards improving static and dynamic device characteristics [7]- [9] In general, the contact resistance in GFETs is a representation of the physical mechanisms preventing the current flow at the interface between the metal contacts and the graphene channel. A correct and efficient characterization of this parameter is a critical point for the development of this emerging technology. A sophisticated physical description of the metal-graphene interface is preferred for the understanding of the carrier injection processes [9,10], however, this might be unsuitable for an immediate device characterization since internal device quantities are required in this approach. As an alternative, analytical and compact device models are able to describe specific GFETs by using certain fitting parameters, including the contact resistance [11]- [18]. However, these are technology-specific approaches which rely on the physical basis of the models and on the calibration procedure.
Test-structure-based characterization methods are of more practical use in laboratories than the modeling approaches for contact resistance assessment. Some of them such as the two-point/four-point-measurement (2P/4P) technique [2], [19], the cross bridge Kelvin method [19], [20] and the widely used transfer length method (TLM) [3,9,14,21,22] have been used in GFETs. However, they involve the fabrication of additional devices and/or special measurement setups and hence, they represent a higher-cost solution in fabrication terms and a less straightforward option for immediate characterization purposes. Furthermore, the reliability of some of these methodologies for graphene FETs is still an open discussion at this early stage of the technology [7,22,23].
Practical and efficient extraction methods in which contact resistance values can be obtained from individual transistor characteristics are required in order to ease device and technology evaluation. In this work, two I − Vbased methodologies, enabled by a drift-difussion description of the transport in GFETs, are presented and applied to simulation and experimental data.

GFET contact resistances
The device total resistance R tot (= V DS /I D ) of a GFET embraces the channel resistance R ch due to scattering processes and/or defects in the graphene layer(s) and the resistances associated to the source and drain contact regions, R C,S and R C,D , respectively. The latter can be lumped into a total contact resistance R C (= R C,S + R C,D ), i.e., In general, two transport processes occur in a metal-graphene interface: from the metal contact to the coatedgraphene region and from the coated-graphene region to the uncoated-graphene region [9], [10], [24]. The contact material [10], [21], the contact geometry and dimensions [19], [21], [24] as well as possible additional layers between metal and graphene [8] have an impact on the resistance originated by the first process. A bias-dependent potential barrier induced by a difference in the electronic properties of the coated and the uncoated graphene portions [9], [10] is the main cause of the resistance associated to the second process. By considering a practical point of view, these resistances are embraced in this work by the contact resistance corresponding to the drain or source contact in a GFET. Notice that, from a modeling point of view, the impact of the potential barrier at the metal-graphene interface on the performance of Schottky-type devices, such as GFETs, can be considered either into the channel resistance or into a bias-dependent contact resistance. R C extracted at a single bias point in the device linear operation regime is generally provided for technology evaluation [8], [18], [21], however, a bias-dependent R C reveals more information on internal physical phenomena at the metal-graphene interface.

Y-function-based contact resistance extraction methods for GFETs
Graphene transistors of different channel and gate lengths have been successfully described by a drift-diffusion (DD) approach [25]- [29] due to unavoidable scattering centers deviating the carrier transport within the channel from ideal ballistic conditions. Furthermore, mobility models inspired by conventional Si theory have described GFET experimental results [28], [29]. Extraction methods for contact resistance of GFETs, based on drift-diffusion theory, are presented next.
The Y-function [30] describes a relation of a DD drain current I D equation at the linear region and its corresponding transconductance g m (= ∂I D /∂V GS ) such as Y = I D / √ g m , where the impact of mobility reduction effects has been removed [30]. Straightforward Y-function-based methodologies (YFMs) have been adapted [31], [32] and applied [33] for device parameters extraction, including R C , of emerging transistor technologies. In order to consider YFM for GFETs, the underlying transport equation needs to embrace the physical phenomena associated to graphene devices, e.g., Dirac-cone bandstructure [25]- [27].
By assuming that the electron carrier transport in GFETs can be described by the DD-approach at the linear unipolar (ohmic) operation regime, and assuming that the carrier concentration can be computed as the average between the charge at the source side C ox (V GS − V Dirac ) and the charge at the drain side C ox (V GD − V Dirac ), I D is given by [31], [32] where V GS/DS is the extrinsic gate-to-source/drain-to-source voltage, V Dirac = V GS | min(I Dirac ) ∼ V GS0 + V DS /2 is the Dirac voltage with V GS0 as the flat-band voltage [26], β = µ 0 C ox w g /L g with a low-field mobility µ 0 , the oxide capacitance C ox , the gate width w g and length L g , and θ is the extrinsic mobility attenuation factor θ = θ 0 + R C β [30], [34] with the instrinsic attenuation factor due to vertical fields θ 0 . By considering Eq. (1), the corresponding Y-function yields from where β can be obtained at the maximum point of its derivative Y with respect to V GS for each V DS . The maximum derivative has been choosen in order to guarantee a linear operation limit. Similarly, a function X = 1/ √ g m is given by the derivative of which yields a value for θ at the maximum point of its derivative X with respect to V GS for each V DS . A V GS -independent contact resistance value R C,1 is extracted from the slope of the relation of θ with respect to β, once these terms have been obtained as described above, i.e., R C,1 = ∂θ/∂β. Alternatively, in order to obtain a V GS -dependent contact resistance R C,2 , an expression can be obtained by applying the definition of θ in Eq. (1) and using Eqs. (2) and (3) for rearranging terms. R C,2 is hence given by [32] According to the methods' features, the transfer characteristics at different V DS , rather than the output characteristics of the device are required for the R C extraction. The methods can be also applied to hole transport by properly adapting Eq. (1) to a hole drain current model and following a similar approach as described above. In contrast to the widely used TLM, no assumption of uniform sheet resistance along the channel and the region under the contacts [48] is required in YFM. In order to obtain reliable reproducible values, the impact of unavoidable traps is recommended to be reduced in experimental data, e.g., by pulsed measurements [35], [36]. The extracted contact resistance values are useful for practical applications since they correspond to the bias region where GFETs are expected to work in HF circuits. In contrast to a previous study where R C of GFETs has been extracted with a different YFM [37], the DD curent model here involves minimum simplifications which has been proven to yield more accurate results in carbon-based devices [31]. Furthermore, a practical difference with the method in [37] is that for the extraction of R C here, the characterization of C ox is not required.

Simulated devices
Scattering-affected DC transfer characteristics of top-gate GFETs with identical device architecture but with different gate lengths have been generated with numerical device simulations consisting on a self-consistent solution of the Poisson's equation and the current-continuity equation [26]. This set of different L g devices enables to imitate a TLM structure. The simulated devices consist of an hexagonal boron nitride (h-BN) encapsulated graphene channel with top and bottom h-BN layers thicknesses of 30 nm each and relative permittivity of 3 and a 285 nm SiO 2 substrate layer. The mobility is assumed to decrease with the vertical field. Further details on the considerations made for device geometry and carrier mobility can be found in [26]. A reference constant contact resistivity of 400 Ω · µm associated to interface layers has been set. The devices gate lengths are of 30 nm, 56 nm, 100 nm, 178 nm and 300 nm. The corresponding TLM curves obtained at different bias are shown in Fig. 1(a).
The contact resistivity R C · w g , extracted with Eq. (4), for the 100 nm-long simulated device 1 is in good agreement with results of the same parameter obtained via TLM within the same bias region as shown in Fig. 1(b). The V GSdependence and the larger value of extracted R C · w g (> 400 Ω · µm) in comparison to the reference value indicate that both extraction methods embrace not only the impact of interfacial layers but also phenomena associated to the internal bias-dependence potential barrier (see Section 2).
The extraction methods have also been applied to data from a physics-based model (Landauer transport theory) [45] of a graphene-based transistor-like device (see Fig. 10 in [45]) with a reference contact resistance in the model   4)). [45] embraces a resistance associated to a potential barrier R C,PB,ref of 250 kΩ and a resistance associated to other interfacial layers R C,IL (value not reported). Notice that a metal/oxide/graphene/semiconductor stack is considered within the contact region and that the oxide is isotropic and isometric along the whole device in the direction of the carrier transport including the gated-graphene region under the top-gate [45]. R C,1 has been extracted for devices in [45] with identical architectures but different oxide thickness t ox,MG at the metal-graphene interface: a 10 nm t ox,MG for the simulated device under study (SDUT) A and a 100 nm t ox,MG for SDUT-B. A smaller oxide improves the gate control over the graphene channel and hence the potential barrier is reduced [45]. The latter is the same tendency observed from the extracted smaller R C,1 of 342 kΩ for SDUT-A in contrast to the 351 kΩ extracted for SDUT-B. From R C,1 (= R C,PB,ref + R C,IL,ext ) on this study, the increase of the interfacelayers resistance R C,IL,ext due to a larger t ox,MG can be also observed since a 101 kΩ for SDUT-B has been extracted in contrast to the 92 kΩ obtained for SDUT-A. Furthermore, the larger increase of the extracted channel resistance R ch,ext (= R tot − R C,1 ), associated to a higher number of scattering events in the thicker device (76 kΩ for SDUT-A, 397 kΩ for SDUT-B), in contrast to the almost similar R C,1 in both cases, indicate that the channel phenomena have no impact on the extraction method.

Fabricated GFET technologies
Contact resistance values have been extracted with the methods discussed above for a wide variety of GFET technologies [2,3], [8], [14]- [18], [38]- [44], i.e., devices with different footprints, architectures and fabrication processes have been considered. The extractions have been performed here considering the dominant branch of the transfer characteristic in each device. Eq. (1) has been calculated with the extracted parameters, including R C,1 or R C,2 -depending on the selected method-, for each device under study and the results have been compared to the corresponding experimental data. A good match between such curves validates the parameters within the bias range selected for the extraction. This validation procedure has been applied for all devices. As an example, Fig. 2 shows the good match between experimental data of devices with different gate lengths (60 nm [17] and 1 µm [38]) and Eq. (1) using the corresponding extracted parameters, including the contact resistance. Additional curves for different GFET technologies ( [3], [43]), i.e., different geometries, have been presented elsewhere [33] with similar results. Notice that the I − V-based verification procedure presented here has not been performed for the contact resistance values extracted with other methods in the corresponding reference.
In order to further demonstrate the validity of the extraction methods presented above, the experimental transfer characteristics of the different GFET technologies and their corresponding description with Eq. (1) using the extracted parameters, including R C,1 and R C,2 are shown in Fig. 3 where |V GS,0 | is the lowest gate-to-source voltage in which the methods have been applied. Results are shown at the lowest reported |V DS | in all studies in order to ease the discussion, however, similar accurate descriptions have been also obtained at different |V DS | in all cases (not shown here).
Eq. (1) correctly describes the experimental data of all technologies under study using the extracted values, including R C,1 and R C,2 , from both methodologies. The extraction methods have been applied here within a bias region (|V GS − V GS,0 |) of interest for HF circuit applications, such as the strong linear regime, i.e., the bias corresponding to the Dirac point has not been considered. Due to noisy data and diverse technology-related effects, the bias range in which Eq. (1) is valid differs from device to device and thus, the extraction methods have been applied accordingly.  Eq. (1) w/R C,2 (b) Figure 3: Transfer characteristics within the bias range where the extraction methods have been applied of devices with different gate lengths: 60 nm [17], 150 nm [15], 150 nm [16], 250 nm [2], 300 nm [40] and 2000 nm [8]. Symbols represent experimental data and lines represent Eq. (1) using the extracted (a) R C,1 and (b) R C,2 .
The contact resistivity values, extracted using R C,1 , of the different evaluated technologies [2,3], [8], [14]- [18], [38]- [44] are listed in Table 1. R C · w g values of the same devices reported with test-structured based methods (TLM and 2P) and analytical model (AM) or compact model (CM) calibration are included as well in Table 1 for comparison along with some device geometry parameters of the studied technologies. R C,1 has been extracted at a similar bias point at which the reference contact resistance R C,ref value has been reported in the corresponding study. Despite the universality of the methods described above, a scaling study is not feasible here since the studied devices are from different technologies.
The extracted values are close to the reference ones obtained by other more intricate and technology-specific methods. The mean relative deviation of R C,1 and reference values, excluding the 150 nm-long device [15], is between 6% and 27%. However, not all the reference values are validated in contrast to the procedure included here (see Fig.  3). The difference between the extracted and reference data of the 150 nm-long device [15] can be explained by a strong impact of the Schottky barrier in the device performance which is not considered in the reference parameter in contrast to R C,1 (and R C,2 ) here which embraces the Schottky barrier contribution.
In contrast to contact resistance values obtained by fitting certain CMs or AMs, the Y-function based methods presented here work for different technologies without adjusting further parameters. While physics-based models are more accurate to describe the device performance, they result impractical from the characterization point of view since they require information regarding intrinsic physical device values, e.g., charge carrier density [8], [14]. Therefore, the methods discussed here are an alternative for immediate contact resistance extraction.
The same value of R C,1 extracted for scattering-affected transistors with identical architecture and materials but different L g [2], [3], where R ch is expected to differ, indicates that channel phenomena have no impact on the extraction. The latter can be exploited in devices with more sophisticated channel morphology, such as graphene nanoribbons FETs [46], in which channel and contact improvements can be evaluated independently. E.g., the R C,1 of 36 MΩ of such device [46], extracted with Eq. (1), should decrease after a contact engineering but remain the same under Table 1: Contact resistivity extracted at a single bias point R C,1 · w g , reported values of contact resistivity R C,ref · w g obtained with other methods and device dimensions of fabricated GFETs. only channel pattern treatment. Furthermore, the impact on the contacts quality of an electrostatic doping applied to the 1 µm-long device [38] can be observed in the reduction from 3.4 kΩ · µm, obtained with R C,1 , of the undoped device, to 1.7 kΩ · µm of the doped device. The methods presented here are also an effective and immediate tool to evaluate contact engineering techniques in a technology such as the R C improvement in fabricated GFETs [47] due to an optical litography treatment (R C,1 = 215 Ω) in contrast to non-treated contacts (R C,1 = 450 Ω). R C,2 can indicate such improvement over bias (not shown here) in contrast to the techniques in [47]. The V GS -dependent contact resistivity, obtained from Eq. (4), of HF GFETs is presented in Fig. 4(a). Considerations for the bias region in which R C,2 has been extracted remain the same as above (see discussion of Fig. 3).  (b) Figure 4: (a) Extracted V GS -dependent contact resistivity (using Eq. (4)) of fabricated GFETs designed for HF applications [2,3,8,15,16,17,40]. (b) Ratio between channel resistance and extracted contact resistance R C,2 for the HF devices. All curves correspond to the lowest reported V DS .
A monotonic decrease of R C,2 ·w g is observed for an increasing |V GS −V GS,0 |. This is an expected result in the linear operation regime due to the lowering of the potential barrier between metal and graphene. Low values of R C,2 · w g as well as a linear constant response over certain bias, can indicate a suitable contact transparency for the intended low-power HF applications of carbon-based devices [49], [50]. The device linearity is recommended to be confirmed with trap-free data [35], [36]. The bias-dependent contact resistivity of the other devices under study can be found elsewhere [33].
The channel to contact resistance ratio shown in Fig. 4(b) indicates the impact of these parameters on the device behavior. The high steepness of the curves is due to the V GS -dependence of R ch rather than that of R C,2 . The contact resistance is extremely dominant for most of the devices [2,3,15,16,40]. The non-linear response of the curves corresponding to the 150 nm-long device [16] and the 2 µm-long device [8] suggest non-trivial internal mechanisms, e.g., transport through higher sub-bands, trap-induced current variations, etc., the discussion of which is out of the scope of this work. A ratio close to unity indicates that both channel and contact resistances are relevant for the 2 µm-long device [8] as well as for the 60 nm-long GFET [17]. The latter reveals a non-intuitive scattering-affected behaviour of short devices.

R C -based high-frequency performance projection
GFETs HF performance projection studies over bias are enabled by the R C,2 and by a oftenly used small-signal model approximation [1]- [3], [26] where the extrinsic cutoff frequency f t,e and the extrinsic maximum oscillation frequency f max,e are given by respectively, where f t,i ≈ g m,i / 2π C gs,i + C gd,i is the intrinsic cutoff frequency, g m,i the intrinsic transconductance, g d,i the intrinsic output conductance, C gs,i/gd,i the intrinsic gate-to-source/gate-to-drain capacitance, R g the gate resistance and R C the contact resistance, corresponding here to R C,2 . For the calculation of g m,i and g d,i , the intrinsic gate-to-source voltage V GS,i ≈ V GS − I D R C /2 and the intrinsic drain-to-source voltage V DS,i ≈ V DS − I D R C have been considered.
The HF figures of merit defined in Eqs. (5) and (6) have been obtained for a 60 nm-long device [17], a 100 nmlong device [3] and a 250 nm-long device [2] from different technologies, using R C,2 and the corresponding C gs,i/gd,i and R g reported in the corresponding reference. g m,i and g d,i vary also with the bias point according to the reference data. Results are shown in Fig. 5. Notice that f t,e and f max,e of the best HF device reported in each work can not be reproduced here due to the lack of information required for the applied YFM, e.g., transfer characteristic not reported or reported at different bias. The impact of R C can be observed in the difference between intrinsic and extrinsic cutoff frequency: the highest the R C,2 values (associated to the device in [3]), the most degraded f t,e with respect to f t,i . In addition to electrostatic effects and in contrast to mature technologies, f max,e in HF GFETs is strongly affected not only by R C,2 but also by R g . The latter one can be optimized by T-type gate architectures [2], [17] while the former requires further optimization which can be evaluated with the extraction methods presented here.

Conclusion
Efficient and immediate contact resistance extraction methods, developed within the context of drift-diffusion theory, have been described and applied to graphene FETs from different technologies. In contrast to other technologyspecific and more intricate approaches, e.g., AMs, TLM, the extraction methodologies presented here are based on individual and practical transistor static characteristics, i.e., no additional test structures nor a description of internal physical phenomena are required. V GS -independent and V GS -dependent contact resistance values, R C,1 and R C,2 , respectively, can be extracted according to the applied methodology. A drift-diffusion drain current model including the extracted parameters describes the transfer characteristics of the studied devices from different technologies. Extracted values are in good agreement with reference values of different simulation frameworks. Furthermore, the extracted R C s of fabricated GFET technologies are close to the reference values obtained by other less straightforward methods. Immediate evaluation of contacts is enabled by the methods. R C,2 enables the evaluation of the contact transparency as well as high-frequency performance projections considering the bias-dependent potential barrier at the metal-channel interface. The methods are expected to be applied to any 2D transistor technology within the bias range in which the carrier transport can be described by a drift-diffusion approach.