{'fraction_non_alphanumeric': 0.04465334900117509, 'fraction_numerical': 0.012925969447708578, 'mean_word_length': 5.0, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 1, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A Novel Insight on Interface Traps Density (Dit) Extraction in GaN-on-Si MOS-c HEMTs

This paper aims to investigate the interface traps density (Dit) extraction on MOS gate stacks processed on GaN-on-Si substrates. CGV (Capacitance-Conductance) measurements under different frequencies (f = 1kHz-1MHz) and temperatures (T = 20K-500K) on various Al2O3/UID-GaN MOS capacitors were carried out. Thorough analysis under dark and UV light compared to TCAD/analytical modeling reveal a strong distributed series resistance under the gate related to the high resistivity of UID-GaN layer. This effect leads to an overestimation of the actual Dit value extracted at high frequencies (> 10kHz). Choosing an adequate doping under the gate (n-type) cancels the series resistance effect and unlocks a reliable extraction through {T/f} dependent CGV measurements.