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Accelerating the construction of BRIEF descriptors using an FPGA-based architecture

BRIEF emerged as a novel alternative to conventional floating-point-based descriptors such as SIFT or SURF. In contrast to these descriptors, BRIEF is a descriptor represented by a binary number offering two main advantages: low memory footprint and fast descriptor comparison. These qualities make it a suitable descriptor to be implemented on a hardware architecture, where the comparison operation can be implemented efficiently via a parallel scheme. However, the construction of BRIEF involves a sequential operation in the form of a set of pairwise tests on the image intensities, and as consequence, sequential memory access is necessary. In this paper, we propose a novel way to construct the BRIEF descriptor by arranging the pairwise tests such that data retrieval from memory is exploited, thus accelerating the descriptor construction up to 4 times when compared to the sequential way.