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Design and Implementation for Quadruple Precision Floating-Point Multiplier Based on FPGA with Lower Resource Occupancy

Although numerical range and precision are greatly improved for quadruple precision floating-point number in IEEE 754(2008) standard, the complexity of operation and cost of hardware resource for the quadruple precision floating-point has been significantly increased, especially for 113×113 mantissa arithmetic in floating-point multiplication operation. This paper presents a new quadruple precision floating-point multiplication algorithm. Finally, we prototype the quadruple precision floating-point multiplier unit into FPGA chip. The experimental results show that the FPGA hardware resource occupancy can be effectively reduced when using this algorithm.