{'fraction_non_alphanumeric': 0.028599605522682446, 'fraction_numerical': 0.008875739644970414, 'mean_word_length': 5.34375, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Production and propagation of single-event transients in high-speed digital logic ICs

The production and propagation of single-event transients in scaled metal oxide semiconductor (CMOS) digital logic circuits are examined. Scaling trends to the 100-nm technology node are explored using three-dimensional mixed-level simulations, including both bulk CMOS and silicon-on-insulator (SOI) technologies. Significant transients in deep submicron circuits are predicted for particle strikes with linear energy transfer as low as 2 MeV-cm/sup 2//mg, and unattenuated propagation of such transients can occur in bulk CMOS circuits at the 100-nm technology node. Transients approaching 1 ns in duration are predicted in bulk CMOS circuits. Body-tied SOI circuits produce much shorter transients than their bulk counterparts, making them more amenable to transient filtering schemes based on temporal redundancy. Body-tied SOI circuits also maintain a significant advantage in single-event transient immunity with scaling.