{'fraction_non_alphanumeric': 0.022304832713754646, 'fraction_numerical': 0.0012391573729863693, 'mean_word_length': 5.121212121212121, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
ADC and AGC requirements of a direct-sequence spread spectrum signal

In a direct-sequence spread spectrum (DSSS) digital receiver, sampling and quantization occur at a very high frequency. Since designing both a high sampling and high resolution analog-to-digital converter (ADC) is difficult, the ADC in a DSSS digital receiver must operate with the fewest bits necessary. To achieve high performance using the fewest quantization bits requires that the automatic gain controller (AGC) optimally scale the received signal. We quantify the quantization and scaling effects on the bit error rate of a DSSS signal when the additive noise is dominated by white Gaussian noise and multiple access interference. Our results suggest that a 3-bit quantizer with an effective AGC achieves near optimum performance.