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A Delay Model for SRAM-Based FPGA Interconnections

This paper proposes a delay model for SRAM-Based FPGA Interconnections. First, an equivalent resistance delay model is presented based on 50% timing delay for step input. The equivalent capacitance delay model is thereafter proposed for the ramp input The corresponding effective capacitance delay calculation method is also given. The experimental results show the efficiency and accuracy of the proposed delay model for the FPGA interconnections.