{'fraction_non_alphanumeric': 0.022222222222222223, 'fraction_numerical': 0.004678362573099415, 'mean_word_length': 5.584615384615384, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Programmable synthesis using a new "Speech microprocessor"

In the past, real-time speech synthesis has been achieved using either relatively expensive special hardware or custom integrated circuitry which implements a single synthesis algorithm. In order to fill a need for low cost, high quality synthesis with algorithm flexibility, two NMOS LSI devices which implement a programmable "speech microprocessor" have been developed. By orienting the architecture toward common features of several classes of digital vocal tract models, synthesis computations involving a large number of multiplies, adds, and other operations can be performed efficiently. For example, the processor can implement a complex cascade/parallel formant synthesizer or a lattice filter with up to fourteen poles. The LSI chip set will become commerically available in mid-1980.