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Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models

Circuit reliability is an increasingly important design consideration for modern logic circuits. To this end, our work focuses on the evaluation of circuit reliability under probabilistic gate-level fault models that can capture both soft errors, e.g., radiation-related, and spatially-uniform manufacturing defects. This basic task can, in principle, be used (i) by synthesis procedures to select more reliable circuits, and (ii) to estimate yield for electronic nanotechnologies where high defect density is expected. We propose a matrix-based formalism to compute the error probability of the whole circuit based on probabilities of specific gate errors. This formalism is surprisingly related to that of quantum circuits, but also exhibits several new features. The numerical computation of error probabilities in large circuits runs into the same scalability problems as the simulation of quantum circuits. Therefore, we hope to adapt recent advances in quantum circuit simulation to the context of this work.