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Latching on the wire and pipelining in nanoscale designs

In contrast to general-purpose programmable fabrics, such as PLAs, we develop nano-fabrics that, while also programmable and hierarchical, are more tuned towards an application domain. Our goal is to achieve denser designs with better fabric utilization and efficient cascading of circuits. We call these designs NASICs: Nanoscale Application-Specific Integrated Circuits. We believe NASICs are a more natural fit to implement microprocessors, out of semiconductor nanowires and crossed carbon nanotubes, than PLA style designs. A key challenge in nanoscale designs in general is to preserve the density advantages of the fabric once topological, interconnect, and faulttolerance constraints are considered. In this paper we demonstrate possible optimizations, within the constraints of sub-lithographic fabrication, that improve NASIC fabric utilization. We show designs that are based on dynamic evaluation approaches, rather than static ratioed logic, that can provide the scalability necessary to build larger-scale pipelined architectures. We describe NASIC dynamic circuit styles that allow pipelining and temporary storage on the wire, called nano-latches, without requiring explicit latching.