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Power optimization for clock network with clock gate cloning and flip-flop merging

Applying clock gates (CGs) and multi-bit flip-flops (MBFFs) are two of the most effective techniques for low power clock network design. Some previous works had proposed to optimize clock network with either CGs or MBFFs, but none of them simultaneously considers both CGs and MBFFs during clock network optimization. Although CGs and MBFFs can be optimized separately, the resulting dynamic power may not be optimal. This paper presents the first problem formulation in the literature for gated clock network optimization with simultaneous CG cloning and FF merging. To effectively solve the problem, a novel optimization flow consisting of MBFF-aware CG cloning, CG-based FF merging, and MBFF and CG placement optimization is introduced. Experimental results show that the proposed flow results in better dynamic power and clock wirelength compared with other flows which optimize gated clock network with CGs and MBFFs separately.