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Design of a fully pipelined single-precision floating-point unit

A fully pipelined single-precision floating-point unit is proposed in this paper. It is implemented in three pipeline stages. The core of this design is a multiply-add-fused unit. With the assistance of a lookup table and the control logic, it also implements floating-point division and square root operations, besides the basic addition, subtraction and multiply-add-fused operations. It is modeled in VerilogHDL and synthesized in 0.18 mum CMOS technology after verification. Experiment result shows that there is only 3% time penalty compared with the traditional multiply-add-fused unit.