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A New Single-Port Five-Transistor SRAM Cell Design for Signal Processing Systems

Static random access memory (SRAM) has been widely used as the typical memory for logic LSIs due to its fast operations and a little power consumed at standby mode. In this paper, a new single-port five-transistor (5T) SRAM cell integrated with assist circuitries is proposed. This design is to provide an efficient solution to the writing ‘1’ issue to improve write operations and to introduce a two-phase reading methodology to speed up reading speed and thereby avoiding unwanted power dissipation. Also, by using the standby startup circuit design, the SRAM cell can reduce leakage current in standby mode. Simulations are conducted to show the effectiveness and superiority of the proposed method.