{'fraction_non_alphanumeric': 0.023506366307541625, 'fraction_numerical': 0.010773751224289911, 'mean_word_length': 5.611650485436893, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Cryogenic Characterization of Antiferroelectric Zirconia down to 50 mK

Cryogenic operation of classical memory devices is becoming increasingly important in the context of quantum information processing1,2. In existing lab scale solid state quantum computers (QCs), quantum bits (qubits) are placed inside a dilution-refrigerator at a few mK connected to the control processor at room temperature (300 K) through control cables. However, such approach is not scalable to large number of qubits due to (1) the large thermal leakage because of the large thermal gradient across the control wires, and (2) bandwidth restrictions imposed limited number and long lengths of the wires. On the other hand, QCs require significant classical memory capacity (10–100 GB) and bandwidth to (1) store the arbitrary rotations in quantum algorithms and (2) handle error syndromes that are continuously generated and measured to compensate for the extreme noise sensitivity of the qubits. As such, the existing superconducting memory technologies (such as the Josephson-junction (JJ) based memories and hybrid JJ-CMOS memories) operating at mK cannot be used as the sole memory technology due to their limited memory density and energy efficiency. Cryogenic control architectures of QCs are being actively investigated where the processing and control systems and the memory are organized at different temperatures in a cryogenic refrigerator and the latency of room temperature classical memory is amortized by designing multi-temperature memory hierarchies constrained by the refrigerator cooling power at different temperatures and the bandwidth available from the control wires (Fig 1)1,2. Towards that end, we study the cryogenic properties of zirconia stabilized in the tetragonal phase-the work-horse material of commodity DRAM. Antiferroelectricity was recently discovered in tetragonal zirconia and its alloyed variants3,4 for which this material system can serve as a high endurance, non-volatile memory element through work function engineering.5