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Design of a matched filter for timing synchronization

This paper presents the design and evaluation of two algorithms for the implementation of a matched filter for timing synchronization in receiver architectures. The proposed solutions reduce the complexity of the matched filter by at least 40% while maintaining the performance at an acceptable level. The designs were also compared to traditional matched filter design to evaluate their relative performance at different signal-to-noise-ratio (SNR) levels. Moreover, the designs were ported on a DSP-like core to analyse and evaluate their relative metrics, such as: computation time and energy consumption. Simulation results showed an energy and a computation time reduction of 60% and 40% respectively.