{'fraction_non_alphanumeric': 0.026986506746626688, 'fraction_numerical': 0.010494752623688156, 'mean_word_length': 5.242990654205608, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 1, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Linearity enhancement in CMOS power amplifier design by using varactor-embedded output matching network

This paper presents a novel and compact linearization technique for CMOS RF power amplifier (PA) realization. To enhance linearity performance, the distortion components generated by the transistor and varactor are made to cancel each other by the proper design of the output matching network and embedded diode. For verification, a 2 GHz, 20 dBm class-AB PA was designed, fabricated and characterized. Under WCDMA excitation, an improvement of adjacent channel leakage power (ACLR) of about 10 dB and power-added efficiency of > 40% were achieved at saturation.