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An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications

Embedded DRAMs have superior features for applications that require very high memory bandwidth, such as graphics and multimedia. To achieve high memory bandwidth, various techniques such as widening input/output pins shrinking the unit array size, and performing a read operation and a write operation concurrently have been reported. However, these embedded DRAM macros incur considerable area penalty to obtain high memory bandwidth. Among the techniques for achieving high bandwidth, the concurrent read/write operation is a very effective method in performing a read-modify-write function and a double-buffer function for the graphics applications. A pseudo-two-port embedded DRAM macro that performs concurrent read/write operations at high frequency without sacrificing cell efficiency is reported in this paper. To accomplish this, a read/write cross-point switch circuit (RWCC) and distributed steering redundancy switches (DSRS) are introduced. A 32 Mb macro is characterized via a test-chip fabricated in a 65 nm embedded DRAM process.