{'fraction_non_alphanumeric': 0.012687427912341407, 'fraction_numerical': 0.002306805074971165, 'mean_word_length': 4.864864864864865, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
ARCHITECTURAL DESIGN OF 8 BIT FLOATING POINT MULTIPLICATION UNIT

In the recent high speed processor, floating point ALU (FP ALU) is one of the important units to perform the arithmetic and logical functions of the floating point number. Floating point multiplication is one of the arithmetic operations that take more computational time and when implemented in hardware, it requires more area due to the large number of component. However the advantage of implementing the floating point unit in the hardware system is to overcome the overflow and underflow conditions that occur in the logical operation. This paper presents a high speed 8 bit multiplier. To increase the speed and to reduce the power consumption due to the clock load, wave pipelining method has been used. The coding is written in VERILOG HDL and the design is analyzed in the Xilinx environment.