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A design methodology to generate dynamically self-reconfigurable SoCs for Virtex-II Pro FPGAs

Today, the technology is available for the creation of dynamically self-reconfigurable systems. However, the lack of efficient methodologies for customizing the system to the requirements of the application withholds the widespread use of this promising technique. This paper fills the existing design productivity gap concerning dynamically self-reconfigurable systems on chip by proposing a consistent framework for the toolflow that will lead, in a very cost effective way, to an RT level implementation of this type of systems. As a proof of concept we discuss a case study where a virtual instrumentation machine for DSP applications is implemented on a Virtex-II Pro component and where the reconfiguration process is controlled by an embedded processor