{'fraction_non_alphanumeric': 0.020848310567936738, 'fraction_numerical': 0.011502516175413372, 'mean_word_length': 5.15929203539823, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Dynamic and scalable runtime block-based multicast routing for networks on chips

Hardware multicast (one-to-many communication) support in Networks on Chips (NoCs) is beneficial for a wide range of applications. Multicast traffic is seen in applications using coherency protocols in distributed shared-memory systems, neural network implementations and fault-tolerant applications using redundant hardware components. In this paper, we present a dynamic and scalable runtime block-based multicast routing mechanism for mesh NoCs. In the proposed technique, a block of potential destinations is defined at runtime and a bit vector is used to give fine-grained control over destination addresses inside the target block. Since the block size is defined at runtime, dynamic mapping of bit vector index onto the nodes within the block is implemented. This provides a degree of flexibility for applications to dynamically change the block size at runtime when the number of destinations changes. Due to this concept, address overhead incurred is less especially when targeting large scale mesh based networks. For a 4×4 NoC with 6 destinations a 33% decrease in address overhead is seen and a 79% decrease is seen for 128×128 NoC when targeting 16 destinations. We implement this technique on a Virtex 7 FPGA and test it using traffic seen in fault tolerant applications implementing redundancy.