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Investigation of Trench Technology on Silicon Device Fabrication

This work was motivated by the possibility of simplifying the process steps on silicon device fabrication. This simplification could benefit other silicon detector fabrications and have the possibility of terminating the junction edges in other detector designs. This is our attempt of exploring the RIE trench technique onto silicon device process. This technique originated from the high-purified germanium (HPGe) detector fabrication. The results have shown good pixel isolations. It has also shown that the multiple guards to lower the potential from the active area are more effective for trenched guard rings than the planar-processed guard rings. Furthermore, it has shown that the inter-pixel capacitance decreases as the trench depth increases.