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A FPGA-based implementation of JPEG encoder

The research in the domain of image compression increased significantly where the requirements of transmission images have raised enormously. Image compression is very important in digital image processing. It plays a crucial role in efficient transmission and storage of images. The most widely used method of lossy compression is JPEG standard. In this paper, we will discuss the implementation of JPEG encoder for Field-Programmable Gate Array (FPGA). The target device is Virtex V ML507. The JPEG encoder was synthesized with EDK designs at the clock frequency of 125 MHz. The implementation starts with the standard JPEG algorithm that is analyzed to extract the interesting functions that can be implemented in an FPGA: quantization, Discrete Cosine Transform (D C T) and Huffman coding. Once identified, these functions are implemented in software. The design can compress from a BMP to a JPEG image with displaying the compressed one on screen.