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In-wafer variability in FD-SOI MOSFETs: detailed analysis and statistical modelling

Device level variability in a single wafer has been analysed using electrical test data from dedicated low leakage addressable array test structures. The variability has been studied in terms of the drain current. Measurement setup and data processing techniques were used to separate different types of variability. A statistical modelling approach was used to model the measured variability and a unique set of physical sources of variability has been identified and quantified for the different types of variabilities. Monte-Carlo simulations using the calibrated Leti-UTSOI compact model and the quantified sources of variability as normal random variables have been verified to reproduce the measured variances.