{'fraction_non_alphanumeric': 0.026759167492566897, 'fraction_numerical': 0.0, 'mean_word_length': 4.906432748538012, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 1, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Synthesis and simulation of phased logic systems

Phased logic is a synthesis/mapping methodology that allows a standard clocked netlist (combinational gates + DFFs) to be automatically mapped to a non-clocked netlist that uses special gates called phased logic gates. The new netlist has no clock networks and the only required global signal is a power-on reset. We demonstrate the viability of the phased logic approach via the synthesis and simulation of several designs ranging from a few hundred to a few thousand gates. Since the input to the phased logic synthesis/mapper tool is a standard clocked netlist, any standard synthesis tool can be used to produce the clocked netlist. Our methodology starts with behavioral VHDL and produces a simulateable phased logic netlist. It is shown that optimizations and architectural approaches that produce a fast clocked design results in a fast phased logic design. See http://www.erc.msstate.edu/labs/mpl/projects/phased_logic/index.html for more information.