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Design and Simulation of a High Speed CMOS Comparator

Analog-to-Digital conversion process is an electronic process in which an analog signal is changed, without changing its necessary contents, into a digital signal. Latched comparators use positive feedback mechanism (aids in the input signal) to re-generates (amplifies) the analog input signal into a Fullscale digital level output signal [2].This paper presents a CMOS comparator that reduces the overall propagation delay and hence provides higher speed. The design is simulated in 0.25μm CMOS Technology using Tanner EDA Tools. CMOS Comparator shows that the overall propagation delay of the comparator, TPD, is 1.7872e-9 seconds, with a 1.0 V supply voltage.