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A family of self-repair SRAM cores

In the present paper a family of BISR SRAM cores is proposed, characterized by a self-repair strategy performed on-line and without user intervention. Moreover, w.r.t. the BISR approaches presented so far, the proposed method is independent from the memory physical layout. In addition to the BISR architecture, to detect the faulty cells to be repaired, a complete set of test solutions is proposed ranging from an external test to an on-line concurrent BIST.