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Pipeline Optimization for Asynchronous Circuits

This thesis is consist of two parts. The first part addresses computer-aided-design techniques to automate pipeline optimization of asynchronous circuits. The general problem is defined as identifying the minimal pipelining needed in an asynchronous circuit (e.g., number/size of pipeline stages/latches required) to satisfy a given performance constraint, thereby implicitly minimizing area and power for a given performance. In our work, we have proven that this problem is NP-complete and developed an efficient branch and bound solution that can find the optimal pipeline configuration for moderate sized deterministic pipelines models. The second part introduces structural reductions of probabilistic timed Petri nets that preserve a large class of performance measurements. In particular, we proposes a class of reductions that preserve efficiently computable bounds of statistics of time-separation of events (TSEs). It identifies two specific reductions within this class. It demonstrates the utility of these reductions by reducing a detailed Petri net describing the four-phase protocol of a well-known asynchronous pipeline template into a simpler two-phase architectural-level Petri net model. The benefit of this reduced model is that the run-time of subsequent TSE analysis can be greatly improved.