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On the relationship between Rent's rule and Pareto points

The design of a VLSI chip consists of a number of steps, and is usually subject to a number of constraints. During each step estimates of the final design properties are used to steer the design tasks. If the design does not meet the constraints, part of the design must be redone. This is very time-consuming, hence the need for good prediction methods. One of the most important aspects of a design is the interconnection complexity, which is mainly determined by the Rent characteristics and the net degree distribution. A main design task is logic synthesis, which consists of both logic optimization and technology mapping. In this paper the impact of these steps on the Rent characteristics and net degree distribution of the circuit graph is analyzed. A circuit mapped to a simple technology library results in a net degree distribution with relatively more two-terminal nets, and relatively less multi-terminal nets. Also, faster circuits have a more profound Rent region II, a higher average terminal count in region I, and sometimes even a higher Rent exponent in region I.