{'fraction_non_alphanumeric': 0.024081115335868188, 'fraction_numerical': 0.0, 'mean_word_length': 4.851851851851852, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
On the Nonlinear Behavior of the Analog Phase-Locked Loop: Synchronization

The synchronization, in the presence of time delay, of the nonlinear analog phase-locked loop (PLL) with an analog multiplier as phase detector (PD) and a lag filter is investigated. A nonlinear model for the voltage-controlled oscillator (VCO) is suggested and the sum frequency component at the PD output is taken into account. Simple expressions of the hold-in range of both the main synchronization and the synchronization at the third harmonic are derived. These expressions point out the effect of the time delay and the filter time constant on the hold-in range. Some conclusions of the presented analysis are not anticipated by the PLL classic theory and allow a better understanding of the loop behavior.