{'fraction_non_alphanumeric': 0.014827018121911038, 'fraction_numerical': 0.0, 'mean_word_length': 5.333333333333333, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
VHDL Simulation of magnetic domain wall logic

The exponential growth of digital circuit complexity requires to automate their design flows. Automatic synthesis tools and hardware description language such as VHDL allow nowadays to rapidly design very complex circuits containing thousands or even millions of transistors. At each step of the design flow, comparative simulations ensure the coherency among the various views, from the most abstract to the most physical. We have applied this approach to the magnetic domain wall logic (MDWL), building on the recently demonstrated set of basics logic gates.