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Resource Efficient Architecture for Current Control Loop of Two PMSMs

This paper presents a novel closed current control loop of permanent magnet synchronous motor (PMSM). Conventional current control loops need two PI controllers per one PMSM. The paper provides a method for reduction of the resource consumption by using one PI controller for two PMSM. Combining with Black Box Blockset written by Verilog HDL based on Xilinx System Generator, one effective PI controller is designed instead of four PI controllers and simulated using Simulink. The utilization of FPGA resources is verified by Xilinx ISE 14.7 tool. The results show that the proposed method can reduce resource consumption and do not influence system performances observably.