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Some aspects of reliability in amorphous chalcogenide memory switches

It is shown that the statistical distribution of the lock-on time can predict the reliability of the set operation, which, in turn is influenced by the choice of reset parameters. Two modes of degradation of the threshold voltage are identified. One of these is impermanent and can be eliminated by the use of multiple reset pulses, while the other is permanent and is accelerated by the use of multiple reset pulses. An optimum of about 6 reset pulses is recommended. The impermanent mode is attributed to remnant crystalline debris while the permanent mode is attributed to electromigration.