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Fault Detection with Error Correction Codes for Memory Applications

The paper deals with error detection method for difference set cyclic codes with majority logic decoding. These are suitable for memory applications due to their capability to correct large number of errors. The proposed Majority Logic decoder itself detects failures which minimize area overhead and power consumption. The memory access time is also reduced when there is no error in the data read. The proposed circuit is simulated in DSCH, CadenceVirtuoso, and Xilinx. The results obtained in various tools are presented in this paper.