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Performance and productivity evaluation of hybrid-threading HLS versus HDLs

FPGA-based reconfigurable computing is finding its way into a wide range of application areas in which high performance and low power consumption are paramount. However, FPGA-application development using hardware-description languages (HDLs) faces many productivity challenges that limit its wide adoption, including a steep learning curve and lengthy compilation. High-level synthesis (HLS) languages and tools aim to overcome these challenges by providing familiar high-level languages and tools for FPGA-application development. In using HLS, however, an important consideration is the cost-benefit tradeoff for performance and productivity. Hybrid-threading (HT) is a new open-source HLS toolset from Convey Computer, Corp. that features a programming language based on C/C++ and a set of tools for efficient compilation, verification, and implementation. In this paper, we present a performance and productivity tradeoff study of HT HLS versus HDLs using three RC-amenable kernels, each chosen for their distinctive computational requirements. Our results show that for all three kernels, HT achieved over 80% performance for a fraction of development time, in comparison to corresponding optimized HDL-based designs.