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Finite state machine based arbiter for on chip communication architecture

Advanced Microcontroller Bus Architecture (AMBA) is an on-chip bus for SOC design. The role of the arbiter of AMBA system is to control which master has access to the bus. Arbiter is an authority to use the shared resource effectively, so performance also depends on arbitration techniques. This research proposes FSM (finite state machine) for bus arbiter. Proposed FSM is for time based priority arbiter. Bus arbiter ensures that only one bus master will get the grant at a time to initiate data transfers. In priority based arbiter, master has the highest priority will grant to access the bus again and again. Other masters with lower priority will never get the grant to the bus. Time based priority arbiter solves the problem of granting the signal for a bus and avoids the grant of bus to the highest priority all the time if it is always requesting. It also removes of bus starvation problem. Proposed arbiter can be used in any kind of AMBA protocol whenever the arbitration is required. Time based priority arbiter is modelled in Verilog HDL. Various simulation results of arbitration schemes are presented here and validated on Xilinx 13.4, Spartan 6 FPGA platform.