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Interconnecting a distributed processor system for avionics

This paper describes the interconnection scheme devised for an advanced Air Force system concept called Distribution Processor/Memory (DP/M) in which topologically irregular networks of small computers are used to perform avionics processing. The interconnection scheme involves the use of a combination of global and point-to-point busses to handle message traffic in predominantly homogeneous systems of from 5 to 20 computers. The major features of the scheme are the use of biphase bit-serial transmission, associatively addressed messages, and a method for reconfiguration of the point-to-point communications paths under program control. It is expected that the scheme may have general applicability to other distributed processing systems, particularly other real-time systems employing limited-capability processors.