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Circuit Techniques for Efficient Implementation of Memristor Based Reservoir Computing

Reservoir computing is a framework of computation designed with the intention of easing the training of recurrent neural networks. Physical implementation of these reservoirs plays a crucial role in enhancing this advantage by improving its processing speed and reducing hardware training costs. In this paper, we present a hardware architecture for efficient and compact implementation of memristor based reservoirs (liquid state machines specifically). The proposed system consists of a reconfigurable architecture such that any given reservoir topology can be implemented on it. It also consists of a memristor crossbar based readout layer that is trained using supervised spike-timing-dependent plasticity (STDP) techniques. The presented techniques are simple and require simple hardware for their implementation and hence reduce area overhead for training-in-hardware of physical reservoir computing systems.