{'fraction_non_alphanumeric': 0.019447287615148412, 'fraction_numerical': 0.0010235414534288639, 'mean_word_length': 4.927272727272728, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Index-based Activate Operation for High Density DRAMs

DRAMs are being used as a major device for implementing main memory. In order to meet the high performance demands of the computing environment, the size of the DRAM is getting bigger and the amount of address information to be transferred to DRAM increases. Recent DRAMs, such as LPDDR4 (Low-power DRAM) and HBM (High Bandwidth Memory), deliver addresses in a packetized manner over multiple cycles, because of the constraints of increasing the width of address bus pin. In this paper, we propose a new row addressing scheme that performs single cycle row addressing without additional address bus pins. The proposed scheme stores frequently accessed row addresses into small caches and it sends the cache index number instead of row address to DRAM. As a result, the proposed scheme reduces performance degradation due to multi-cycle row addressing and the power consumption on the memory bus due to activation commands.