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Exploiting high-performance DSP hardware for real-time CELP implementation

We describe our experience of implementing a CELP algorithm on a TMS320C44 digital signal processing board. The particular implementation we consider is the Federal Standard 1016 (FS1016) 4.8 Kbps CELP vocoder. Our main focus is on exploiting the high-performance architecture and the features of the DSP processor for possible real-time applications.