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Branch guided functional test generation at the RTL

In this paper, we propose a functional test generation method for Register Transfer Level circuits. A popular metric for measuring the effectiveness of an RTL test suite is branch coverage. The challenge in exercising a hard-to-reach branch is in the understanding of the semantics of the design. Without a good guidance, hard branches might require unnecessarily long test sequences or missed altogether. In our method, we extract such semantics from the circuit using a lightweight static analysis of the code in order to guide the search. Experimental results show that a high level of coverage can be obtained for several benchmark circuits, while reducing the test vector lengths by up to two orders of magnitude in some circuits.