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Four Parallel Channels Radix-4 FFT with Single Floating-Point Butterfly

An efficient design method of four parallel channels in-order FFT with single floating-point butterfly is proposed, to reduce the resource consumption and improve the real-time calculation ability. The radix-4 FFT is deduced to calculate the access address for four channel data parallel. The hardware architecture of the proposed FFT is presented, and the single precision floating-point adder and multiplier are also depicted. The proposed architecture of a four channels 1024 points radix-4 FFT with single butterfly is implemented in FPGA, and the performance is compared with previous literatures and some EDA corporations IP cores, which shows the correctness and effectiveness of the proposed method.