{'fraction_non_alphanumeric': 0.06072477962781587, 'fraction_numerical': 0.047992164544564155, 'mean_word_length': 4.806818181818182, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Digital-to-Time Converter with 3.93 ps Resolution Implemented on FPGA Chips

In this paper, a digital-to-time converter (DTC) based on the principle of quantified phase shift resolution (QPSR) is proposed and tested. The QPSR principle is realized by analyzing the phase relationship between two periodic signals, which distinguishes the proposed DTC from conventional DTCs. For performance evaluation, the proposed DTC is implemented on Xilinx Virtex-5 and Virtex-6 field programmable gate array (FPGA) chip, respectively. The obtained resolution of the DTC implemented on Virtex-5 FPGA is 27.1 ps, and the differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.269~+0.247 least significant bit (LSB) and −0.387~+0.171 LSB. Meanwhile, the DTC implemented on Virtex-6 FPGA can achieve a resolution of 3.93 ps, a dynamic range of 43 s, a DNL of −0.327~+0.358 LSB, and an INL of −2.6093~+2.4754 LSB. Experimental results prove that the proposed DTC features high-accuracy, low-cost, and easy implementation.