{'fraction_non_alphanumeric': 0.026094276094276093, 'fraction_numerical': 0.005892255892255892, 'mean_word_length': 5.160621761658031, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Optimization of on-chip link performance under area, power and variability constraints

A large number of repeaters are used in the global interconnects of any System-on-Chip (SoC) design for improving the delay characteristics, and these repeaters consume a significant portion of the chip area and power. In this work we emphasize that due to increasing trend of the variability, power and area optimal repeater insertion methodologies should also consider performance variability. Analytical models for area, power, performance and probability of link failure have been presented in terms of the size of the repeaters and inter-repeater segment length. It has been found that beyond a certain reduction in the size of the repeaters, the delay variability may exceed acceptable limits while still satisfying other constraints. For instance, with only 4% of performance loss due to the use of smaller repeaters, almost 30% of power and 40% of area savings can be achieved; however performance certainty is reduced by 24%. Therefore, while optimizing area, power and performance of on-chip communication links, delay (and power) variability should also be included in the figure of merit.