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Implementation of programmable delay lines on off-the-shelf FPGAs

The programmable delay line is a key component in test and measurement applications; it facilitates key functionalities such as de-skewing, timing adjustment, edge placement, and time-to-digital conversions. In this work, we investigate the implementation of programmable delay lines on off-the-shelf FPGAs (field programmable gate array). Two flavors of delay lines, coarse and fine, are realized and the corresponding step sizes are 105 and 13 ps, respectively.