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FPGA implementation of an ATM traffic classifier for quality of service management

One of the main problems in modern broadband networks is the variation of quality of service (QoS) that can occur. A very common technology used for broadband networks is ATM (asynchronous transfer mode). ATM can offer QoS guarantees for a number of different traffic classes. In an ATM switch it is possible to discard low-priority cells when the buffer is full. This can be done using logic implemented on a FPGA (field programmable gate array) chip, used because of its flexibility and easy re-configuration. This paper presents the FPGA implementation of an ATM cell priority classifier, which can be used in QoS management. The circuit directly receives a 155 Mbps ATM serial stream from a physical medium device, and performs cell delineation, serial to parallel conversion and classification according to the cell loss priority (CLP) bit. It has been implemented on a Xilinx Virtex XCV50PQ240-6 FPGA occupying 8252 equivalent gates. Simulation results show that the circuit can directly process a 155 Mbps ATM stream.