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Representation Learning of Logic Circuits

Applying deep learning (DL) techniques in the electronic design automation (EDA) field has become a trending topic in recent years. Most existing solutions apply well-developed DL models to solve specific EDA problems. While demonstrating promising results, they require careful model tuning for every problem. The fundamental question on ”How to obtain a general and effective neural representation of circuits?” has not been answered yet. In this work, we take the first step towards solving this problem. We propose DeepGate, a novel representation learning solution that effectively embeds both logic function and structural information of a circuit as vectors on each gate. Specifically, we propose transforming circuits into unified andinverter graph format for learning and using signal probabilities as the supervision task in DeepGate. We then introduce a novel graph neural network that uses strong inductive biases in practical circuits as learning priors for signal probability prediction. Our experimental results show the efficacy and generalization capability of DeepGate.


I. INTRODUCTION
The rise of deep learning (DL) has aroused much interest in applying it to solve various electronic design automation (EDA) problems that otherwise rely on some heuristics or hand-engineered rules, as surveyed in [1]. The most natural representation of circuits and netlists is a graph. With the recent success of graph neural networks (GNNs) [2], [3] in modeling non-structured data, various works have explored its potential on EDA problems such as congestion prediction [4] and testability analysis [5]. These works focus on learning a particular function that takes the circuit graph as input and directly maps it to output for desired EDA tasks, without considering the internal computational process in the circuits.
Recently, a notable trend in the deep learning community is to employ pre-trained models for many downstream tasks rather than learning a specific model for each task from scratch [6]. For example, a series of convolutional neural networks (CNNs) are pre-trained on the ImageNet dataset [7]. They perform well on other computer vision (CV) tasks such as image segmentation [8] and object detection [9] by fine-tuning with a small amount of task-specific data. Similarly, pre-trained Transformer-based language models (e.g., GPT [10] and BERT [11]) have achieved unparalleled performance on various natural language processing (NLP) tasks.
Whereas in the EDA domain, despite all the recent efforts in learning-based solutions [1], obtaining a general and effective circuit representation that serves as the basis for solving various EDA tasks has not been addressed yet. In this work, we take the first step towards this direction by introducing a novel GNN-based solution for the representation learning of logic gates, namely DeepGate, which is aware of the logic computation procedure and the structural information of combinational circuits.
Naturally, logic circuits can be modeled as directed acyclic graphs (DAGs), in which logic gates appear in a specific topological order. Therefore, one could collect many logic circuits and resort to existing DAG-GNN architecture [12], [13] to learn the node embedding for each logic gate with some supervision tasks (e.g., Boolean satisfiability [14]). However, we argue that such straightforward solutions cannot effectively extract information from circuit graphs.
Firstly, logic circuits could follow different design styles and use diverse technology libraries containing various logic gate types, leading to heterogeneous circuit graphs with mixed distributions that are challenging to learn. In DeepGate, we propose to conduct learning on a general intermediate representation of logic circuits, i.e., and-inverter graph (AIG), with the help of logic synthesis tools [15]. The benefits are twofold: (i). Such a unified format constrains the circuit graph distribution without changing circuit functionalities. All the transformed circuits only feature two types of logic gates (i.e., 2-input AND gate and inverter); (ii). The logic synthesis procedure naturally introduces a strong inductive bias of practical circuits for effective learning with GNN models.
Secondly, the effectiveness of representation learning heavily relies on supervision tasks. For example, when pre-training CV models, the image class labels of the ImageNet dataset serve as the cornerstone. In contrast, considering the difficulty in annotating a textual dataset as large as ImageNet, selfsupervised tasks are used instead in NLP pre-trained model development. For effective circuit representation learning, we propose to use the signal probability (i.e., the probability of being logic '1') for every node as rich supervision because it embeds the genuine logic relationship of each node in the circuits. To be specific, we perform logic simulations with a large amount of random patterns to obtain faithful probability values for supervision.
Last but most important, existing GNN models are general solutions designed to extract information from all kinds of graphs, while circuit graphs are a unique type of graph with logic relationships between nodes. In this work, we design a dedicated GNN model for circuit graphs, significantly enhancing the learning effectiveness. We summarize the contributions of this work as follows: • To the best of our knowledge, DeepGate is the first work for the general and effective circuit representation learning problem. Specially, we propose a novel design flow to tackle this problem: (i). circuit transformation in AIG form; (ii). supervision with logic-simulated probabilities; (iii). representation learning with a dedicated GNN model for circuit graphs.
• We propose a novel GNN model for circuit graphs that exploits unique circuit properties, including attention mechanisms that mimic the logic computation procedure and reversed propagation layers that consider logic implication effects.
• Reconvergence structures are inevitable due to logic sharing in multi-level logic networks, and they are the main challenges for logic analysis [16]. We treat them as first-class citizen and introduce novel solutions in our GNN model. We learn the representations of logic gates with many small subcircuits extracted from benchmark circuits. Experimental results performed on large circuits show the efficacy and generalization capability of DeepGate. We organize the remainder of this paper as follows. We review related works in Section II. Section III introduces the DeepGate architecture, while in Section IV, we present the experimental results on various circuits. Finally, Section V concludes this paper.

A. Graph Neural Networks
Graph neural networks [2], [3] have received a lot of attention for their effectiveness in modeling non-structured data. By learning vectorial representations on graphs via feature propagation and aggregation, GNNs show convincing results in various domains [17]- [19]. The most popular GNN model employs a message-passing neural network architecture, which computes representation/hidden states h v for node v in a graph G at every layer and a final graph representation h G , as in [18]: wherein N (v) denotes neighboring nodes of node v and L is the number of layers. The parameterized function AGGREGATE aggregates messages from neighboring nodes N (v), and COMBINE obtains an updated hidden state after aggregation. Finally, the function READOUT retrieves the states of all nodes V and produces the graph neural representation. A notable GNN architecture is the graph attention network (GAT) [20] that considers the importance of different neighbors during aggregation. Directed acyclic graphs (DAGs) are a special type of graphs, yet broadly seen across many domains, including circuit modeling (see Fig. 1). Recently, few studies have been dedicated to DAG-GNN designs [12], [13], which propagate the message following the topological ordering between nodes and only consider the predecessors in the AGGREGATE function, as demonstrated in Equation (3).
The major difference between Eq. (3) and Eq. (1) is that in DAG-GNN, the aggregation function for v will be only executed after all of its predecessors' hidden states have already been computed. Besides stacking L layers to increase the depth of the network, one can also apply the same model for T times in the recurrent fashion to generate the final embedding [14]: Using the taxonomy defined in [21], we name the two variants of DAG-GNNs described in Equations (3)-(4) as DAG-ConvGNNs and DAG-RecGNNs, respectively.

B. GNN-Based Solutions for EDA Problems
Existing GNN-based EDA solutions use an end-to-end flow for specific EDA tasks wherein the labels are usually extracted from commercial EDA tools.
To the best of our knowledge, the first GNN-based EDA technique is applied to the test point insertion (TPI) problem, which is formulated as a node binary classification problem and solved with a graph convolutional network [5]. The ground-truth labels are collected from commercial TPI tools, revealing whether a particular node is "easy to observe" or not. CongestionNet [4] models the circuit as an undirected graph and trains a GAT model to predict the congestion of the final physical design on a per-cell basis. GRANNITE [22] conducts power estimation using a DAG-GNN model. Gate netlists are mapped onto graphs with per-node (gate) and peredge (net) features. They achieved good accuracy (less than 5.5% error across a diverse set of benchmarks) for fast (¡1 second) average power estimation on designs up to 50k gate. Recently, [23] proposes a GAT-based model named N et 2 for pre-placement net length estimation.
To solve a particular EDA problem, the above techniques typically pre-compute many node/edge features (e.g., SCOAP testability measures in [5]) and use existing GNN models to aggregate these features for solution findings. Consequently, the learned node features cannot be transferred among related tasks, despite using the same circuit graphs as inputs. More importantly, an effective representation for circuits should be aware of their logic functions. However, existing solutions ignore it and only consider the structural information in their learning procedure.
Motivated by the above, we propose to learn a general and effective circuit representation without pre-computing any specific features, as detailed in the following section.

III. PROPOSED SOLUTION
A. Overview of DeepGate Figure 2 presents the overview of the proposed DeepGate solution, consisting of two stages for the neural representation learning of logic gates: • Circuit Data Preparation: Given a pool of circuit designs, we use logic synthesis tools to transform them into a unified AIG format. We then perform logic simulations on the circuits with sufficient random patterns to obtain the signal probability (i.e., the probability of node being logic '1') on every node as supervision. We elaborate the details in Section III-B.
• Probabilities Prediction with DeepGate: Given a circuit dataset and the logic-simulated probabilities as the supervision task, we introduce a novel GNN model dedicated for circuit graph analysis to learn the neural representations of logic gates, as detailed in Section III-C.

B. Circuit Data Preparation
Some circuits are at the register-transfer level, while others are gate-level netlists mapped with various libraries. Such heterogeneity across circuits is a challenge for GNN model development. To tackle this problem, we resort to the logic synthesis tool ABC [15] and transform all circuits into the unified AIG format. If the original circuit is too large, we extract small sub-circuits with circuit sizes ranging from 30 to 3k gates. Note that, we test the effectiveness of DeepGate on much larger circuits for its generalization capabilities.
The benefits of such circuit pre-processing flow include: (i). Only two logic gate types (i.e., 2-input AND gate and 1-input Not gate) are considered, which would dramatically reduce representation learning difficulty; (ii). Applying logic synthesis introduces strong relational inductive bias into the resulting circuit graphs; (iii). The constraint on circuit size facilitates efficient GNN training with both reduced sizes of circuit graphs and less time for preparing supervision labels.
There are many possibilities to annotate a circuit, e.g., the satisfiability of the circuit [14]. However, a good supervision task should satisfy the following condition: the labels should be easily obtained while retaining rich information for both the logic function and the structural information of the circuits. In DeepGate, we propose to use the signal probability on every node as supervision, which satisfies the above requirements: (i). It is relatively easy to obtain highly-accurate probability values by running logic simulations on many random input patterns, especially when the circuit size is limited; (ii). A unique yet important property of logic circuits that makes circuit analysis challenging is the reconvergence structures, and logic simulation is arguably the only way to obtain the actual value for such structures; (iii). The logic probability of each gate itself plays an essential role in many EDA tasks.

C. GNN Model in DeepGate
Given circuit graphs in AIG form, the objective of our GNN model is to estimate the probability of every node such that it would be as close to the genuine signal probability as possible. Different from existing DAG-ConvGNNs [12], [13] and DAG-RecGNNs [14] models that focus on learning the topological information in the graph, DeepGate is designed to learn both the circuit structural information and the computational behaviour of logic circuits, and embed them as vectors on every logic gate.
We now elaborate on the detailed GNN model design in DeepGate. Given a circuit graph G, we embed the gate type of each node v with one-hot encoding in x v . To be specific, as only primary inputs (PIs), And gates and Not gates are present in AIGs, we assign a 3-d vector for each node according to its gate type. It should be noted that instead of relying on the probability-based measurements in previous works [5], [22], our model only requires gate type information for the representation learning. We also have hidden states h v for every node, which is initialized randomly. Given these, DeepGate resorts to attention-based aggregation design [13], [20] and the gated recurrent unit (GRU) [12] as the update function.
Aggregation. We use the attention mechanism in the additive form to instantiate the AGGREGATE function in Equation (3), wherein the aggregated message m t v for a node v at t th iteration is computed by: where α t uv is a weighting coefficient that is computed by following the query-key design as in usual attention mechanisms. To be specific, h t−1 v serves as query, and representation of predecessors from current iteration t, h t u , serves as key. The intuition behind using the attention mechanism for aggregation is that when we do the logic computation in digital circuits, the controlling value of a logic gate determines the output of that gate. Therefore, controlling values are far more important than non-controlling values. To mimic this behaviour, the attention mechanism can learn to assign high weights for controlling inputs of gates and give less importance to the rest of the inputs.
Combine. We then use the GRU to instantiate the COM-BINE function for updating the hidden state of target node v: wherein m t v , x v are concatenated together and treated as input, while h t−1 v is the past state of GRU. 8

Fig. 3. Information Propagation at Reconvergence Node using Skip Connection
On the one hand, DeepGate adopts the recursive DAG-GNNs functional defined in Equation (4). The reasons for using the recurrent architecture are two-fold: (i). it is unrealistic for GNNs to capture the circuit's functional and structural information with a single forward propagation; (ii). the recurrent learning procedure facilitates reaching stabilized node embeddings quickly.
On the other hand, our proposed GNN model differs from previous DAG-GNNs [12]- [14] that initialize h 0 v as x v and treat the aggregated message as the state of recurrent function. In contrast, we fix the gate type information of nodes x v as inputs for all iterations. Such employment can avoid the information vanishing of gate properties during the long-term recursive propagation.
Reversed Propagation Layer. In DeepGate, we also consider backward information propagation, i.e., processing the graph in reversed topological order. One of the main reasons to introduce the backward layers in our framework is that logic implication and backtracking in the reversed order can be highly useful for predicting the states of nodes. It also helps stabilize training, as proved in sequence-to-sequence learning tasks [24].
Regressor. After T iterations, we pass the hidden states of nodes h T v into a multi-layer perceptron (MLP), which computes a single scalar for every node to regress the simulated probabilities. The weights of MLP are shared for nodes with the same gate types. We train the network to minimize the L1 loss between the predictionŷ v and the true probability y v .

D. Skip Connection for Reconvergence Structure with Positional Encoding
In the previous section we have described the core components of DeepGate necessary for predicting the logic probabilities of nodes. However, the logic inference on reconvergence nodes is different from normal nodes and such structures are inevitable due to logic sharing in multi-level logic networks. Hence, they are the main challenge for logic probability analysis. To accommodate their impact, we introduce the improvement into DeepGate to enable special processing for reconvergence nodes as shown in Figure 3.
Firstly, we maintain the information of reconvergence nodes during circuit data preparation, including its corresponding source fan-out node, and the logic level difference between the source nodes and reconvergence nodes. Secondly, we add direct edges between the fan-out node and the reconvergence node, named skip connection here. The new edges facilitate the information exchange from fan-out nodes to reconvergence nodes. Last but not least, we leverage the positional encoding technique [25] to differentiate the skip connection and the normal connection. To be specific, the function γ(D) is a mapping of logic level difference D between source fan-out node and reconvergence node into a higher dimensional space R 2L : γ(D) = (sin(2 0 πD), cos(2 0 πD), · · · , sin(2 L−1 πD), cos(2 L−1 πD)) The impact of the fanout node on the reconvergence nodes depends upon the distance between them. Generally speaking, the longer the distance is, the lesser impact it has on the reconvergence node. The above function can induce the knowledge of how much fanout node can impact the result of reconvergence node into the model. We assign the encoded vector as the edge attributes to skip connection and incorporate it into the coefficient calculation described in Equation (5) as the third input.

A. Datasets
We extract many sub-circuits from four circuit benchmark suites: ITC'99 [26], IWLS'05 [27], EPFL [28] and Open-Core [29], and follow the circuit data preparation flow described in Section III-B to transform all circuits into a unified AIG format. We conduct logic simulations with up to 100k random input patterns to obtain an accurate signal probability on every node. Table I presents the statistics of the circuit dataset. #Subcircuits shows the total number of subcircuits extracted from each benchmark. As shown in the table, the constructed circuit dataset covers circuit sizes ranging from tens to thousands of nodes with different logic levels. Finally, there are 10, 824 circuits in total, and we create 90/10 training/test splits for model training and evaluation.

B. Evaluation Metric and Baselines
To evaluate the performance of different GNN models, we calculate the average value of the absolute differences between the simulated probability y v and the predictedŷ v from DeepGate for all nodes V in the circuits, as shown in equation (8). The smaller the value is, the better the model performs.

Avg. P rediction Error
We consider three GNN models: GCN, DAG-ConvGNN, and DAG-RecGNN. GCN model treats the circuit graphs as undirected graphs in representation learning. DAG-ConvGNN model follows the settings defined in Equation (3). For DAG-RecGNN model, we adopt the same COMBINE function and the reversed propagation layer design in DeepGate, as depicted in Section III-C. As for the GNN model in DeepGate, it contains additional attention mechanism and skip connection (SC). Under every setting, we evaluate 4 different aggregator designs, which include representative works for DAG learning, i.e., Convolutional Sum (abbreviated as Conv. Sum) [30], Attention [13], [20], GatedSum [12] and DeepSet [14].
In order to make the comparison fair, we instantiate all models with d = 64 for the node hidden states h v and design the other parameterized functions to have a similar number of tunable parameters. For DAG-RecGNNs and our DeepGate model, a forward layer is followed by a reversed layer, and to poor performance for probability prediction, mainly due to their lack of ability to model the computational behaviours of circuits. For instance, the best GCN model, equipped with Conv. Sum, gives 0.1386 of prediction error, which in turn is even higher than the worst performing model of DAG-RecGNN. Therefore, only by incorporating the logical ordering into the model design and conducting the propagation recurrently, will make the model perform well. It shows the advantage of DAG-RecGNN implementation with dedicated recurrent scheme and reversed layer design discussed in Section III-C over simpler GNN architectures. Second, among all models, DeepGate with attention alone achieves significant prediction error reduction. It brings 22.76% relative improvement compared with the best baseline solution, which is the DAG-RecGNN model equipped with DeepSet aggregator. Hence, using the dedicated attention mechanism benefits logic representation learning. Third, equipped with skip connection design, DeepGate can further reduce the prediction error from 0.0234 to 0.0204, which reveals the efficacy of introducing the reconvergence knowledge into the model design. To summarize, with only the gate type information and the connectivity between gates, DeepGate learns to predict highly-accurate probabilities for logic gates.
As we observe that DAG-RecRNN with DeepSet aggregator (abbreviated as DeepSet for the following discussion) performs better than the other baselines, in later results, we only compare DeepGate (w/ skip connection) with it. 2) Results on Large Circuits: Furthermore, we evaluate DeepGate on five circuit designs that are substantially larger than the circuits it saw during training. The circuit statistics and the prediction error of both DeepGate and DeepSet are shown in Table III. The number of gates in these designs is two orders of magnitude more than that of the training circuits.
We can observe that DeepGate achieves similar prediction accuracy as that on small circuits, and it outperforms DeepSet in these large circuits by a large margin. Such results clearly demonstrate the generalization capability of DeepGate. In particular, DeepGate achieves 73.56% prediction error reduction on Arbiter. This is because, the Arbiter circuit is designed to accommodate access from multiple requests, and it contains repetitive logic units with many reconvergence structures. As DeepGate treats such structures as a first-class citizen in the GNN model, it can generate much more accurate predictions.
D. Discussion 1) Effectiveness of Circuit Transformation: DeepGate uses the logic synthesis tool to transform the circuits from different sources into unified AIG forms. One may wonder the performance of DeepGate if the network is directly trained on the original circuits, wherein other gate types (e.g., XOR, NAND, NOR, and OR) are also included. To investigate the effectiveness of the circuit transformation in DeepGate, we conduct the controlled experiments on EPFL and IWLS benchmarks, as shown in Table IV.
Take EPFL as an example, we extract 375 sub-circuits from the original designs, and develop two versions: the ones with the original 6 gates types and the other with AIG transformation. For each version, we train the DeepGate model from scratch. The only difference is that for the former version of the dataset, we assign 7-d one-hot encoding for the node feature x v . As can be observed from Table IV, DeepGate trained on AIGs performs better than the one trained on the original circuits by a large margin (33.94% relative prediction error reduction on EPFL). The same observation can be obtained from the results on IWLS circuits.
Such improvements originate from the benefit of circuit transformation because when only two logic gate types are considered, representation learning difficulty is reduced dramatically without any impact on circuit functionalities. Also, we manually check the usage frequency of different gate types in the original formats, and observe that some gates types (e.g., XOR and NAND) are used much less frequently. Such in-balanced gate distributions may lead to insufficient training, causing higher prediction errors. Additionally, we directly apply the pre-trained DeepGate model on the merged AIG dataset, as shown in Section IV-A for comparison. As can be observed, DeepGate trained on the dataset consisting of different benchmarks can further reduce the prediction errors by 51.37%. It supports the claim that unifying different circuit designs into a common intermediate representation can help the model learn a better representation of logic gates.
2) Impact of Recurrence Iterations: During the inference phase, the number of iterations T can be set as different values. The higher the value, the higher the computational cost.
We enumerate different values for T , ranging from 1 to 50. We observe that our GNN model is able to decrease the prediction loss as T increases. However, the prediction error converges quickly at around T = 10, despite the circuit size. Such experimental results further demonstrate the scalability of the proposed DeepGate solution.

V. CONCLUSION AND FUTURE WORK
This paper proposes DeepGate, a novel representation learning solution that effectively embeds both logic functions and structural information of a circuit as vectors on each gate. In DeepGate, we construct easy-to-learn circuit graphs by transforming circuits into unified AIG format and introduce a novel GNN model with circuit knowledge as priors for effective representation learning. Using informative signal probability as supervision tasks on small sub-circuits, we show DeepGate can generalize to large circuits with accurate predictions without any pre-computed features.
While showing promising results, the current implementation of DeepGate can still be significantly improved. For example, we could introduce other informative supervision tasks (e.g., logic inference and Boolean satisfiability) to achieve better representations for logic gates. We could also add more circuits for training to build a large-scale foundation model for logic circuits [31]. Moreover, in our future work, we plan to apply the representations learned in DeepGate onto many downstream EDA tasks (e.g., power estimation, logic reduction, and equivalence checking). These tasks are directly related to signal probability analysis, and we believe DeepGate can achieve satisfactory results without much effort in finetuning the model.