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Harmonic Distortion in Switched Current Cells Due to Settling Error

An analysis of the harmonic distortion in switched-current cells produced by the non-linear settling error is presented. Two approaches for computing the harmonic components are addressed: discrete-time Fourier series and power series expansion. They are based on the large signal behavior of the SI cell. A compact and flexible expression is obtained with series expansion. An alternative expression is presented for cases where only the settling error magnitude is required. The effect of charge redistribution between the input and the sampling nodes is analyzed. It is shown that including that effect, the harmonic distortion is increased, and the DC gain of the SI integrator is reduced. An analysis of the total harmonic distortion when clock-feed-through and non-linear settling error are both taken into account is presented. It is demonstrated that minimum distortion is reached for a given capacitive value. For a SI cell designed with 0.8 μm standard CMOS technology working at a sampling frequency of 8 MHz, a minimum THD of −72 dB can be obtained with a Cgs ≈ 2.4 pF.