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Analyzing the behavior of FinFET SRAMs with resistive defects

The miniaturization of CMOS technology is likely to reach its limit due to short-channel effects. New transistor technologies, including FinFET technology, were developed to deal with this effect and enable the continuous scaling-down of technological nodes. Alongside the constant scale-down of integrated circuits technology, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy great part of Systems-on-Chip (SoCs). The manufacturing process variation has introduced different types of defects that directly affect the SRAM's reliability. Thus, it remains unknown if fault models used to characterize faults in CMOS memory circuits are sufficiently accurate to represent the behavior of FinFET-based memories. In this context, a study of functional implications of manufacturing resistive defects in FinFET-based SRAMs is presented. In more detail, a fault model for FinFET-based SRAMs as well as a complete analysis of the static and dynamic fault behavior are presented. The proposed analysis has been performed by means of SPICE simulations, adopting a 20nm technology library. The faults were categorized in single and coupling, static and dynamic faults.