{'fraction_non_alphanumeric': 0.016730038022813688, 'fraction_numerical': 0.001520912547528517, 'mean_word_length': 5.23696682464455, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Performance analysis of CNTFET based digital logic circuits

Silicon technology continues to scale down and is a dominant choice for high-performance digital circuits. For enhancement of digital circuit performance researchers are further investigating other novel materials to introduce into future technology generations. Carbon nanotubes (CNTs) have been explored as a promising candidate for the same due to their excellent carrier mobility. The effect of CNTFET parametric variation for chirality (or diameter) with threshold voltage on performance metrics namely delay, power and power_delay_product (PDP) has been analyzed in the present paper. It is found that with decrease in diameter of CNTFET, power reduces but with delay penalty. A comparative study of CMOS and CNTFET logic circuits is carried out. An overview of ternary logic is presented. Dependence of threshold voltage on the geometry of carbon nanotube makes it feasible to be used for ternary logic design. Subsequently, circuits in voltage mode ternary logic are implemented using CNTFETs. It is analyzed that CNTFET based circuits are energy efficient. It is also concluded that novel ternary logic is a moderately fast and low power solution to digital circuit design. The circuits have been simulated using HSPICE for 32nm technology node.