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A refined four-dimensional parity based EDAC and performance analysis using FPGA

With the immense intensification of data storage, communication and hence sources of noise and interference, challenges for reliable storage and communication of data have been even more vital. A number of EDAC schemes are in use having their own merits and demerits and choice of any particular technique is basically a tradeoff between area, cost, performance, power and error correction capability. In this paper, we present a novel idea for improvement in the four-dimensional parity scheme by adding parity bits in another direction i.e. diagonal in opposite direction. This new scheme is intended not only to cope with the limitation of the existing scheme to correct triple bit scattered errors in various patterns but also correct adjacent four bit errors.