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Comprehensive methodology for the design and assessment of crossbar memory array with nonlinear and asymmetric selector devices

Technology and design tradeoffs are important for crossbar memory array optimization. A comprehensive model is presented in this paper to assess array functionality with different nonlinear and asymmetric selector parameters, bias schemes, and array designs. Array Vdd should be maximized within power and efficiency constraints. Partial bias schemes can be chosen based on selector types and design targets. Different dependence of array selectivity and power efficiency on selector parameters presents technology tradeoffs. Impact of line resistance, contact resistance, and memory variability is analyzed. Parallel access and self-selecting design may improve array performance.