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A Code Generation Framework for VLIW Architectures with Partitioned Register Banks

Modern computers are taking increasing advantage of the instruction-level parallelism (ILP) available in programs with advances in both machine and compiler design. Unfortunately, large amounts of ILP hardware and aggressive instruction scheduling techniques put large demands on a machine’s register resources. With large amounts of ILP, it becomes difficult to maintain a single monolithic register bank and a high clock rate. The number of ports required for such a register bank severely hampers access time [2, 8]. To provide support for large amounts of ILP while retaining a high clock rate, registers can be partitioned among several different register banks. Each bank is directly accessible by only a subset of the functional units with explicit inter-bank copies required to move data between banks. Therefore, a compiler must deal not only with achieving maximal parallelism via aggressive scheduling, but also with data placement to limit inter-bank copies. This paper describes our approach to partitioning values among available register banks. Our method provides flexibility for our retargetable compiler by representing machine dependent features as node and edge weights and by remaining independent of scheduling and register allocation methods. Preliminary experimentation with our framework has shown a degradation in execution performance of 33% on average when compared to an unrealizable monolithicregister-bank VLIW architecture with the same level of ILP. This compares very favorably with other approaches to the same problem. This research was supported by a grant from Texas Instruments.