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A Chip MultiProcessor Accelerator for Video Decoding

In this paper we propose architectural enhancements to specialize the Cell SPU for video decoding. Through thorough analysis of the H.264 video decoding kernels we identify the execution bottlenecks among which are matrix transposition, scalar operations, and lack of saturating arithmetic. Based on these bottlenecks we propose ISA extensions that speed up the execution. The speedup achieved on the IDCT8, IDCT4, and deblocking filter kernel are between 1.69 and 2.01.