{'fraction_non_alphanumeric': 0.01647875108412836, 'fraction_numerical': 0.0, 'mean_word_length': 5.594285714285714, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
HIGH SPEED POINT ARITHMETIC ARCHITECTURE FOR ECC ON FPGA

Elliptic curve cryptography plays a crucial role in networking and communication security. ECC have evolved in the recent past as an important alternative to established systems like RSA. This paper describes the implementation of an elliptic curve coprocessor based on the FPGA , which can provide a significant speedup for these cryptosystems. The FPGA configuration file is synthesized from VHDL code applying different hardware synthesis products. The implementation of ECC lies in three levels: scalar multiplication, point addition/doubling and finite field modular arithmetic. In this paper, we present a novel fast architecture for the point addition/doubling level in the projective coordinate. The proposed Architecture is based on Binary Field. The Design performs multiplication using Polynomial Basis. Analysis shows that, with reasonable hardware overhead, our architecture can achieve a high speedup for the point addition operation and point Doubling operation.Furthermore, the architecture is parameterized for different data widths to evaluate the optimal resource utilization.