{'fraction_non_alphanumeric': 0.029839326702371844, 'fraction_numerical': 0.005355776587605203, 'mean_word_length': 5.258373205741627, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
System-level implementation of output-capacitorless sliding-mode control based-digital LDO regulator

Digital low-dropout regulators (DLDOs) draw great attention because of their low voltage operation and process scalability. Several works done to improve the stability and transient performance of DLDOs are based on using a clock-based comparator as an error amplifier. This paper aims to propose the use of sliding-mode control (SMC), as the controller of DLDO instead of the conventional clock-based comparator. The proposed SMC-based DLDO is designed and its state-space model and sliding coefficients are extracted by considering the hitting and existence conditions. Additionally, the chattering problem of sliding-mode control is compensated here by introducing additional control signal, named freeze control signal; enabling clock in the transient and disabling it in the steady-state condition, which results in reducing the switching losses. To verify the statements, the proposed SMC-based DLDO is implemented using Matlab/Simulink for input and output voltages of 0.8 V and 0.6 V, respectively, and load current of 0–40 mA. The results reveal that the controller detects the load changes rapidly, and eliminates the output limit-cycle oscillation, providing a robust and stable output voltage.