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Taylor Expansion Diagrams : A Compact Canonical Representation for Arithmetic Expressions

This paper presents a new, compact, canonical representation for arithmetic expressions, called Taylor Expansion Diagram. It can be used to facilitate the verification of RTL specifications and hardware implementations of arithmetic designs, and specifically the equivalence checking of complex algebraic and arithmetic expressions that arise in symbolic verification. This new representation is based on an entirely new, non-binary decomposition principle. It treats the expression as a continuous, differentiable function over symbolic (algebraic) variables and applies Taylor series expansion recursively over its variables. The resulting Taylor Expansion Diagram (TED), is canonical for a fixed ordering of variables. We present a theory of TED, and show how to obtain the reduced, normalized representation. We demonstrate that it has linear space complexity for arbitrarily complex polynomials, while time complexity to generate the representation is comparable to that of *BMD. This is the first representation known to us that allows to represent complex arithmetic functions in linear space. We believe that the proposed representation will have serious impact on symbolic verification methods as it can significantly enhance the verification process for RTL designs containing arithmetic circuits.