{'fraction_non_alphanumeric': 0.018922852983988356, 'fraction_numerical': 0.0, 'mean_word_length': 4.982608695652174, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
An abnormal threshold voltage variation of the p-type thin-film transistors under DC bias stress

The abnormal turnaround phenomenon of threshold voltage for the p-type low temperature poly-silicon thin film transistors (LTPS TFTs) stressed under a specific negative DC bias condition, which the gate voltage is about one half of the drain voltage, is investigated. There are two turnaround points for the TFT stressed with prolonged time. The sampling current of the TFT under the biasing stress is used to confirm the turnaround phenomenon. We propose the three-staged degradation models to explain the abnormal threshold voltage variation of LTPS TFTs under a specific DC bias stress.