{'fraction_non_alphanumeric': 0.029548989113530325, 'fraction_numerical': 0.02177293934681182, 'mean_word_length': 5.505050505050505, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder

This paper describes the implementation of a 256-state, rate 1/2, soft-decision Viterbi decoder. The implementation explores several variables and design considerations of a Viterbi decoder, testing various methods for low power and throughput capability. By designing the Viterbi decoder using three techniques, a progressive active ACS (add-compare-select), prediction matcher, and reduced read traceback, we take the most efficient techniques and apply them, iteratively to the overall design to achieve 12.7 % of dynamic power consumption with 250Mbps of throughput