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Synchronous digital hierarchy byte pointer justification versus VC-12 payload bit justification effects

Four contributors to Synchronous Digital Hierarchy (SDH) network desynchronizer buffer fill variations are the justification bits in the VC-12 payload, the irregular spacing of the data in the VC-12 payload, the irregular spacing of the data in the SDH frame, and the pointer activity which contains byte activity as opposed to the bit activity in the VC-12 itself. These phenomena result in a variation of the rate at which bits arrive at a desynchronizer in a SDH network. Modeling and understanding of these processes is required in order to be able to propose advanced pointer processor algorithms as well as advanced jitter reduction techniques in SDH de-synchronizers. This paper examines the relative effects of bit justifications in VC-12 payloads in conjunction with the corresponding byte justifications in SDH networks in order to determine the dynamics of SDH network plesiochronous desynchronizer buffers.