{'fraction_non_alphanumeric': 0.013293943870014771, 'fraction_numerical': 0.005908419497784343, 'mean_word_length': 5.36150234741784, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Architecture and control of a high energy density buffer for power pulsation decoupling in grid-interfaced applications

In this paper we propose a series-stacked partial power processing architecture and the associated control scheme for double-line-frequency power pulsation decoupling in single phase inverter/rectifier applications. The proposed architecture exploits series stacking of the energy storage capacitors and a buffer converter across the DC bus such that the buffer converter only experiences low voltage stress and processes only a fraction of the total buffer power, while still maintaining a close to ripple free DC bus voltage. Such arrangement results in improved efficiency and higher energy density compared to conventional active decoupling solutions. A control scheme is proposed to exploit the small remaining bus ripple to compensate the power loss in the buffer converter and balance the power cycle of the architecture. A 2 kW hardware prototype has been built to demonstrate the benefit of the proposed solution. The hardware prototype achieves significant volume reduction compared to the conventional passive decoupling solution. An energy density of 611 W/in3 (by component volume) for the hardware prototype and an efficiency above 97.9% across a wide range of power and voltage levels has been experimentally verified.