{'fraction_non_alphanumeric': 0.031879194630872486, 'fraction_numerical': 0.0050335570469798654, 'mean_word_length': 4.796116504854369, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
The Influence of Gate Bias on the Anneal of Hot-Carrier Degradation

We observe that non-zero gate bias applied during a high temperature anneal following hot-carrier degradation (HCD) impacts degradation recovery in nFETs. The devices are arranged into custom-built arrays and fabricated in a commercial 40 nm bulk CMOS technology and the FET anneal is induced by on-chip poly-Si heaters. The anneal is modeled using Stesmans’ passivation model for Pb-defects in hydrogen gas (H2). Negative gate bias improves the anneal, in line with studies on biased passivation of process-induced Pb-defects.