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Across-wafer CD uniformity control through lithography and etch process: experimental verification

Process variation on lot-to-lot and wafer-to-wafer level has been well addressed using R2R control in advanced process control, however, to tackle the ever increasing die-to-die (i.e. across-wafer) level process variation at the 65nm technology node and beyond, the process control must be extended into finer domain: across-wafer level. A novel model based process control approach [2] was proposed to reduce the critical dimension (CD) variation on across-wafer level. The central idea of the proposed approach is to compensate for upstream and downstream systematic CD variation by adjusting the across-wafer Post-Exposure Bake (PEB) temperature profile of a multi-zone bake plate. A temperature-to-offset model relating the PEB temperature profile of multi-zone bake plate to its heater zone offsets was constructed experimentally using wireless temperature sensors from OnWafer Technologies. The baseline post-etch CD signature and plasma etch bias signature were extracted to characterize the lithography and etch processes. And a post-etch CD variation reduction of 40% was realized in the verification experiment, which validated the efficacy of the proposed approach.