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Methods of optimized via design for higher channel bandwidth

This paper analyzes the ability of an optimized via design to achieve higher channel bandwidth by minimizing the impedance discontinuity of a high speed serial link above 5Gbps owing to the parasitic capacitive effect of vias on a single Printed Circuit Board (PCB). The methods of optimized via design are back-drilling plated through hole, removing unused pads and increasing anti-pad clearance [1]. Different via features and their impact are studied in 3D model extraction using EMPro software from Agilent, and simulations are done using Advanced Design System (ADS) where the measurement of insertion loss, time domain reflectometry (TDR) and eye diagrams are used. Subsequently, the simulation results are correlated with measurement results from a prototype PCB.