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1 A comprehensive approach to scalable framework for both vertical and horizontal reuse in UVM verification

The complexity of today’s multi-core SoCs can be addressed only if the main challenges in verification are handled successfully. With increasing adoption of UVM, each IP could be well verified in a block level UVM testbench and environment. SoC functional verification involves integrated IP blocks, and there will be more challenges such as integration checking, multiple complex scenarios and use case driven verification in different SoC design stage. The key points are to improve the verification quality at SoC level in early phases of design integration. To do this, the IP level's testbench, including sequences must be highly reused properly during SoC level complex tests, especially the use case driven verification. To reduce cycle time and effort, both vertical (from IP to sub-system to SoC level) and horizontal (from project to project) reuse need to be ensured. In this paper, we will show a comprehensive approach from an architecture point of view to create a scalable framework to address those key challenges with very little effort across multiple aspects of today’s SoC functional verification process. UVM Shared Physical Memory Dynamic Memory Allocation Manager "SDMAM" techniques are also used for this framework. This paper assume you are adopting Cadence VIP, UVM methodology, and AMBA protocol for both fabric and main bus.