{'fraction_non_alphanumeric': 0.020802377414561663, 'fraction_numerical': 0.0029717682020802376, 'mean_word_length': 4.964601769911504, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A new architecture for the fast Viterbi algorithm

A novel architecture design to speed up the Viterbi algorithm is proposed. By doubling the number of states in the trellis, the serial operation of a traditional add-compare-select (ACS) unit is transformed into a parallel operation, thus achieving a substantial speed increase. The use of the proposed architecture would increase the speed by 33% at the expense of a fairy modest increase in area, thus removing the Viterbi detector/decoder from the worst case speed bottleneck path in most high-speed applications. A simple example is shown to illustrate the proposed algorithm in a maximum likelihood sequence detector.