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An efficient 2-D DWT architecture via resource cycling

Most DWT architectures reuse the filterbank modules for all decomposition levels to improve the hardware utilization but they should be implemented for the worst-case storage and computational precision requirements. We propose a novel reconfigurable 2-D DWT architecture in this paper that dynamically recycles the unused storage for computation resources with increasing precision as the decomposition level goes higher. We have implemented and verified this cost-effective architecture with PDA (Parallel Distributed Arithmetic) filterbank modules on the Xilinx XCV300-PQ230-6 FPGA and shown great improvement on PSNR/area ratio.