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Sensitivity analysis of a superscalar processor model

Superscalar processors obtain their performance by exploiting instruction level parallelism in programs. Their performance is therefore limited by characteristics of programs and the design of the processor. Due to the complexity involved, estimating the performance of any superscalar processor design is a difficult task. Quick prediction of performance improvement arising from architecture modifications is even more difficult. In this paper, a model of superscalar processors using a network of Multiple Class and Multiple Resource Queues is described and studied. In this model, we are able to model and study instruction classes, instruction dependencies, the cache, the branch unit, the decoder unit, the central instruction buffer, the functional units, the retirement buffer, the retirement unit and instruction issue policy in an integrated manner. This model has been verified against measured performance and has shown an average error of 5%. From this starting point, we applied sensitivity analysis on the model and studied qualitatively three important classes of improvements one can make to a superscalar processor's design. The insights we derived show how a good model can be used to accurate pinpoint bottlenecks and assign relative importance to them. This will in turn guide development efforts.