{'fraction_non_alphanumeric': 0.0161892901618929, 'fraction_numerical': 0.0, 'mean_word_length': 5.090909090909091, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Research and Design of Asynchronous FIFO Based on FPGA

In this article, a design method of asynchronous FIFO memory based on FPGA is put forward. With FPGA as the core controller, We adopt Verilog HDL and top-down design method to build a top-level module design and also analyze the mark logic of asynchronous FIFO and the elimination of semi-stable state under Quartus II development platform. Besides, with the application of Gray code conversion technology, not only the reliable transmission of data is guaranteed but also design efficiency is improved. Through contrast experiment analysis and simulation test, the validity and reliability of asynchronous FIFO memory are verified, meeting the basic requirement that FIFO can hold more enough data without spillovers despite the fullness of data.