{'fraction_non_alphanumeric': 0.018599562363238512, 'fraction_numerical': 0.0010940919037199124, 'mean_word_length': 5.1, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A heuristic DSP BIST insertion algorithm with minimum area overhead

In this paper, a new methodology for generating a self-testable data path with minimum area overhead in a minimum number of test sessions is presented. The main contribution is in the register allocation and binding algorithm, which is constructed from two phases. In the first phase, a number of self-adjacent registers configured as concurrent built-in logic block observation registers (CBILBO's) are minimized. As the registers configured as BILBO's that can work as either pattern generator or signature analyzer for the same module add a large cost to the constructed data path, phase 2 of the proposed algorithm tries to minimize occurrence of those registers whenever possible in a minimum number of test sessions. When the algorithm is applied to DSP applications, an improvement is achieved for both area overhead and interconnections.