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A bit-serial floating-point complex multiplier-accumulator for fault-tolerant digital signal processing arrays

This paper presents the extension of bit-serial architectures for next-generation signal processing chips with floating-point and fault-tolerant capabilities. The architecture and design of a novel bit-serial floating-point complex multiplier-accumulator (CMAC) hardware is described. Fault-tolerant features are incorporated by embedding these CMACs into dynamically reconfigurable systolic arrays. The arrays can be utilized for FIR filtering, convolution, correlation and other signal processing applications based upon multiply-accumulate. Furthermore, these computational cores can be incorporated into more complex processors which perform FFT-type computations. With the advent of submicron VLSI technology, the smaller device geometries will afford either the implementation of greater functionality and/or computational capabilities. These increased capabilities will enable the solution of more demanding signal processing problems where there exist broad dynamic range requirements or low signal to noise conditions. But also associated with the increased functionality is the greater need for fault tolerance in high performance applications. Our bit-serial floating-point complex multiplier-accumulator will serve many such signal processing needs.