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FPGA-based accelerator for the verification of leading-edge wireless systems

The design of communication systems becomes increasingly challenging as product complexity and cost pressures increase and as the time-to-market is shortened more than ever before. This paper presents a bit error rate tester (BERT) for the hardware-based verification of the physical layer (PHY) layer of emerging wireless systems. We integrate fundamental modules of a typical PHY layer along with the channel simulator onto a single field-programmable gate array (FPGA). For a proof-of-concept, we present the results of a FPGA-based performance verification exercise for a multiple antenna system. The proposed BERT system significantly decreases the test time compared to conventional software-based verification, hence increasing designer productivity.