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A Low-power Oriented Dynamic Hybrid Cache Partitioning for Chip Multi-processor

As the number of cores on CMP increases, the size of an on-chip cache increases and it consumes more and more power of the whole system. So low-power oriented design has become an inevitable trend. However currently most of the partitioning strategies are aimed at throughput or fairness, ignore the power consumption. In order to reduce system power consumption, a new low-power-oriented hybrid partitioning (LPHP) strategy for shared cache is proposed in this paper. Due to the program locality principle, it uses both private and shared resource-allocation methods to implement the partitioning strategy by combining the two threads whose access appears large difference into one partitioning unit at run-time. Then when running the same application, some of the cache columns can be closed within the performance degradation threshold (PDT).