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Low cost hardware implementation for traffic sign detection system

This paper describes a novel compact hardware oriented algorithm and its conceptual implementation for realtime traffic signs detection system. The speed limit sign area on a grayscale video frame is detected based on a novel, simple and compact rectangle pattern matching and circle detection modules. The speed limit recognition system has two-pipeline stages. Each frame is scanned with multi-scan windows in parallel for each position and each scan windows is also processed in pipeline to increase throughput. It achieves 100% in detection rate, is able to work at 83 full HD fps, and occupies 19% of slice registers and 67% of slice LUTs in a low cost Xilinx Zynq 7020 SoC.