{'fraction_non_alphanumeric': 0.028444898654402997, 'fraction_numerical': 0.01652188724237779, 'mean_word_length': 4.466945996275605, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Design of Ultra-low Power Consumption Low-dropout Regulator

This paper designs a type of ultra-low power consumption LDO with the CSMC 0.5μm technology, which can output the 1.5V voltage. In this LDO, the error amplifier is structed with two-stage operational amplifiers. The input of first stage uses PMOS differential pairs that can decrease the noises and the second stage uses the common-source structure in order to increase the open-loop gain. In addition, the MOS amounts we use are as less as possible over the whole circuit, which decrease the die size to satisfy the trend of product miniaturization. The result of simulator Spectre shows that the LDO proposed can output the 1.5V voltage stably, the PSR is -66dB at 1kHz, and the loop gain is 72.5dB, the lowest dropout voltage is 93mV, the power consumption is only 1mW.


INTRODUCTION
With the reduction of characteristic size of transistors, electronic products and devices show a trend of product miniaturization. So far, with the wide application of miniature electronic products, the demand of portable electronic products is also increasing rapidly. Therefore, it is inevitably accompanied by a large demand for power management IC(PMIC). These typical products generally include: DC/DC, PFM/PWM control IC and linear voltage regulator. Among them, the analog low-dropout(LDO) regulator in voltage regulator IC is the main demand as well as several digital low-dropout regulators have been also proposed [1~6]. For instance, in portable mobile devices, the PMIC unit requires many LDO regulators with different output voltages and load current capacities to support many applications, such as application processor(AP), camera, memory, radio-frequency integrate circuit(RFIC) transceivers, universal serial bus(USB), and so on [7~12]. Besides, the DC/DC switching regulator operates with an internal conversion from DC to AC and then to DC, involving many off-chip capacitors, which makes it difficult to apply it to small electronic devices. In addition, for baseband, antenna and other high-frequency applications that require low input-output dropout voltage and highpower ripple rejection ratio, the low-dropout regulator is the best choice for many occasions. As the main research direction of LDO is no longer to pursue high load and high current, but to improve the accuracy, reduce the dropout voltage, increase the ripple rejection ratio, reduce the power consumption and speed up the transient response as much as possible, this paper designs a basic LDO to meet the above requirements by optimizing the structure of each part.

DESIGN PRINCIPLE OF LDO
The LDO consists of a reference circuit, an error amplifier, a buffer, a PMOS power transistor Mp, compensation capacitors and divided resistors, as shown in Figure 1. The main ports for LDO to interact with the outside world are: input voltage V in (It is also the power supply of bias circuit and error amplifier), output voltage V out and GND. The rest of the peripheral devices are compensation device ESR resistors and capacitors, plus equivalent load R L . LDO works on the principle that a bandgap reference source, which is virtually immune to external influences, generates an ideal constant voltage as the reference voltage V ref , which is used as one of the inputs to the error amplifier to compare voltage. When the input voltage increases and causes the output voltage to increase in a very short time, the voltage increasement at the output end is perceived by sampling the resistor connected through the voltage divider, and then sent to the other end of the error amplifier through the feedback loop and compared with the reference voltage. The positive difference is amplified by the error amplifier and sent to the Gate end of the Mp, which causes the current I D flowing through the Mp to decrease, and then the output voltage V out satisfies the following relationship: Therefore, in this case, the decrease of I D will inevitably lead to the decrease of V out , so as to achieve the purpose of voltage stabilization. Conversely, when the input voltage is reduced, the output voltage is also reduced by it. The feedback network samples the reduced output voltage and transmits it to the other end of the error amplifier through the feedback loop, and then it will be compared with the reference voltage, resulting in a negative difference which is amplified by the error amplifier and transmitted to the Gate end of the Mp, which causes the current I D flowing through the Mp to increase. From formula (1), we can see that V out will increase at this time, so as to achieve the purpose of voltage stabilization.

ERROR AMPLIFIER
The overall error amplifier is designed as two-stage amplification. The first stage uses a PMOS differential pair as the input stage because of its lower noise characteristics compared to NMOS [13]. Although cascode or folded-cascode can achieve higher gain and swing, it is not necessary for LDO used in low-voltage environments.
In order to reduce the noise parameters of devices and structures as much as possible and increase the output swing, the second stage of the error amplifier uses a common-source structure. In this way, the two-stage operational amplifier provides higher open-loop gain but lower power consumption and less noise as much as possible compared with sleeve structure and folding structure [14] [15]. The specific circuit is shown in Figure 2.  Figure 2 and the auxiliary theorem, the following results can be obtained. The differential amplification gain of the first stage is: The common-source amplification gain of the second stage is: The total gain of the two-stage operational amplifier is:

ZERO-POLE ANALYSIS
Suppose there are two poles and one zero of the two-stage operational amplifier, which are respectively located at the EA output (recorded as ω p1 ) and the Buffer output, including the ESR compensation capacitor C L (recorded as ω p2) and of the LDO output, in addition the zero (recorded as ω z ) is at the ESR with the output. the Bode plot of the two-stage operational amplifier is shown in Figure 3: It can be seen that both main poles are close to the origin and the phase is already close to -180°, which is much lower than that of the third pole. In other words, the phase margin is likely to be close to 0 before the third pole produces a phase shift [16]. Therefore, the next thing we need to do is to move the first main pole ω p1 closer to the origin so that the intersection point when the gain is reduced to 0 dB is far lower than the phase intersection point, but since the unit gain bandwidth after compensation is unlikely to exceed the frequency of the second pole of the open-loop system, if the value of ω p1 is reduced, the achievable bandwidth will be limited to a low value of about ω p2 [16]. On the other hand, for the main pole to become a very small value, a very large compensation capacitor is required.
Therefore, in this case, we use Miller compensation, which is equivalent to establishing a lowfrequency pole with a moderate value of capacitor, and significantly increases the input capacitor and decreases the output capacitor. The specific analysis is as follows.
As shown in Fig.4 the LDO system introduces three poles P1, P2 and P3 and one zero Z1, in which the P1 should be the dominant pole, and the P3 is the load pole varies with the load current I LOAD , the P2 is the buffer output pole. Then we can write down these poles and zero to be [17] where the R o1 , R o2 and R p are resistances seen at the output terminals of EA, Buffer, and Mp, respectively. The C m is the Miller capacitor connecting between the input and output of the Buffer.

Gain and phase margin of error amplifier
The error amplifier used in this LDO is tested by simulator Spectre, and its gain and phase curves are shown in Figure 6.

Fig.6 Open-loop gain and phase
The open-loop gain of the op-amp is 83.6dB and the phase margin is 62°.
As mentioned earlier, Miller compensation is used to adjust the zero-pole to make the system run stably, with the gain and phase curves of the loop shown in Figure 7. It can be seen from the curve that the loop gain is 72.5dB and the phase margin is 65°, which can ensure the stability of the system and meet the design requirements.

The lowest dropout voltage
The LDO is designed with a constant output of 1.52V. The input DC voltage is gradually increased from 0V to 10V when scanning. The voltage amplitude is observed at the output end. The lowest inputoutput dropout voltage is defined as the difference between the input voltage and the output voltage that can maintain the LDO in the normal voltage stabilization.
As shown in Figure 8, the input voltage is increased from 0V to 1.613V when it starts to enter the linear regulated operating state. At this time, the output voltage is 1.52V, which means that the lowest input-output dropout voltage of this LDO is 93mV.

Response time
Response time is a very important transient response parameter for LDOs, which reflects how quickly the entire LDO system responds to sudden changes in voltage. This test inputs two transient signals at the LDO and observes the corresponding output amplitude at the LDO. Specifically, when t=0, the input voltage is kept at 0V, then the output voltage will also be 0V; a step signal with an amplitude of 2.5V is suddenly added at t=2μs; when the LDO output voltage returns to 0V, a step signal with an amplitude of 0.5V is suddenly added, which is lower than the normal regulated input range. The transient response of LDO output is shown in Figure 9. It can be seen from Figure 8 that the overshoot response of this LDO is: The undershoot response is: Δt2=13-10μs=3μs

Power supply rejection (PSR)
The power supply rejection (PSR) reflects the ability of LDO to suppress noise. Set the 1V AC small signal as the input and set the load as 2kΩ. The simulator Spectre is used to conduct AC simulation, with the sweep frequency range from 0.01Hz to 100MHz. The 20lg amplitude at the output is observed, as shown in Figure 10. Fig.10 The PSR The figure shows that the PSR at f=1kHz is about -66dB; the PSR at f=10kHz is about -59.5dB.

Linear regulation rate
The linear regulation rate reflects the ability of the output voltage to remain stable when the supply voltage changes [18]. The supply voltage is set to 3V, and then a square wave with an amplitude of ±300mV is connected in series to this supply, causing the supply to undergo a large fluctuation. The voltage amplitude at the output is observed, as shown in Figure 11.

Power consumption
The minimum input voltage for the LDO to enter the regulated state at no load is 1.613V. An input voltage of 1.613V is added to the LDO, then the quiescent current of the LDO is 371.447nA. Therefore, the power consumption of LDO at no load is 371.447nA×1.613V≈0.6μW When the load is 2kΩ, the minimum input voltage for the LDO to enter the regulated state is 2.8V. An input voltage of 2.8V is added to the LDO. Then the quiescent current of the LDO is 760.6μA, the load current is 760μA, and the load voltage is 1.52V. Therefore, the power consumption of LDO at this time is: (2.8-1.52V)×0.76mA≈1mW

CONCLUSION
Based on the CSMC 0.5μm technology, an ultra-low power consumption low-dropout regulator with a constant output voltage of 1.5V has been designed in this paper. The circuit has been simulated and optimized by the simulator Spectre to meet the design requirements. Taking [19][20] [21] as examples, the quiescent current under no-load state in this paper is further reduced compared to some low power consumption designs, which effectively reduces the LDO power consumption. The comparison is shown in the table below.