{'fraction_non_alphanumeric': 0.030379746835443037, 'fraction_numerical': 0.021518987341772152, 'mean_word_length': 4.609929078014185, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
A High-Speed BiCMOS Fully Differential Operational Amplifier with Improved Slew Rate and Phase Margin

A high-gain high-speed fully differential folded-cascade operational amplifier with improved slew rate (SR) is implemented in a 0.6-μm SiGe BiCMOS process. The amplifier can source/sink much larger current than the quiescent current when output voltage is slewing, even with a current reduction in the common-base path. Compared to the CMOS folded-cascode configuration, BiCMOS folded-cascode improves the phase margin. Cadence Spectre simulation shows that the amplifier has an open-loop DC gain of 103 dB, a unit gain bandwidth of 270 MHz and a phase margin of 63° degrees and a slew rate of 1265 V/μs only consuming 1.6 mA in the main amplifier path, all with 4 pF capacitive loading.