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Timing Defect Analysis in Look-Up Tables of SRAM-Based FPGAs

The objective of our article is to demonstrate that some physical defects in a LUT can change its propagation delay. We propose a simplified 'timing' model of the LUT which determines its propagation delay. Such a model is exploited to analyse the effects of a defect on the LUT behaviour, from which we demonstrate that they can cause a timing fault on it. Anywhere in a LUT, a timing defect can increase the propagation delay of the LUT. From this study, we show the significant interest to take timing defects in a LUT into account for a complete delay fault testing of FPGAs. 1 Introduction Field Programmable Gate Arrays (FPGAs) combine the flexibility of mask programmable gate arrays with the convenience of field programmability. There are many FPGA types but one very usual is the Static-RAM based FPGA architecture. In such a SRAM-based FPGA, an array of logic cells and interconnections can be configured many times to implement the desired application. This technology has drastically reduced the cost of hardware manufacturing, making hardware implementation economically feasible for applications which were previously restricted to software. Moreover, the reconfigurable sight of such circuits is taking more significance for System-On Chip (SOC) designers. Actually, adding reconfigurable logic to SOCs will give system designers much greater flexibility. Testing such FPGAs from either a manufacturer or an user point of view has received increasing attention in the test community. Several methods for static voltage testing have been proposed in the last years [1,4,5,10,11,12,13,14,15]. Some methods apply to the logic cell [7,13], some others to the routing architecture [1,4,5,14], or to the configuration layer [10]. Most of them implement BIST architecture by configuring unused parts of the FPGA. Recently, techniques have been proposed to test only programmed resources from an application-user point of view [11,12]. Local and global faults in monolithic circuit processes can be caused by various fault mechanisms which induce either random spot defects or device parameter variations. Although the defects led by local mechanisms often cause static faults, a lot of them can only be detected by delay fault tests, which are also suitable to identify faults coming from global mechanisms. However, testing for delay faults in FPGA is still an immature field. Some methods have been proposed to test path delay faults [2,6,8,9] in which a path is composed of programmed LUTs and interconnections. Most of the techniques use BIST and are applied to test path delay faults in an userapplication context. In [6], the authors concentrate on interconnect and do not account for the LUTs. This is motivated by the fact that interconnection delays can account for over 70% of the FPGA clock cycle [8]. Conversely, the others methods [2,8,9] consider timing defects both in the LUTs and in the interconnect. All these techniques use the reprogrammability of the LUT to improve the delay fault test coverage, because they assume the delay being independent of the implemented function. Nevertheless, testing timing defects only on interconnections is not sufficient. A path can not be considered completely fault-free whether timing defects within LUTs are ignored. Such defects in LUTs can cause a quite large variation in the propagation delay and create a timing fault in the LUT behaviour. Therefore, testing path delay faults in an userapplication should focus on delays both in the interconnect structure and in LUTs. The main objective of this article is to demonstrate that some physical defects in a LUT can change its propagation delay. This significant result will allow to justify the need for a complete and reliable delay fault testing of FPGAs. Before that, we propose a simplified 'timing' model of the LUT that can be used to determine its propagation delay. Such a model does not pretend to be a new model for simulation tools : instead, this new representation will be suitable to analyse the impact of timing defects in the context of FPGA testing. The rest of the paper is organised as follows. Section 2 gives an overview of SRAM-based FPGA architecture. Section 3 analyses the timing behaviour of a LUT and presents a possible simplified timing model. Section 4 focuses on the timing change of the LUT, due to the presence of defects in the structure. Concluding remarks and future work are discussed in Section 5. 2 – SRAM-Based FPGA Architecture We assume an island-style FPGA architecture [3] composed of a two dimensional regular array of identical tiles, as shown in Figure 1. A tile is composed of a cluster-based logic block and surrounding routing channels. A pin of logic block can connect to some of wiring segments in the channel adjacent to it via a Connection Block (CB). At every intersection of a horizontal channel and a vertical channel, there is a Switch Block (SB), which allows some of the wiring segments incident to the SB to be connected to others. SB and CB are simply a set of programmable switches.