{'fraction_non_alphanumeric': 0.04081632653061224, 'fraction_numerical': 0.0022675736961451248, 'mean_word_length': 4.660256410256411, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects

Chip-to-chip interconnects can be traditionally tested for stuck-at faults and hard bridging faults via the boundary scan test standard. However, such a traditional test method may not be adequate for 3D-ICs, in which die-to-die interconnects could operate at a very high speed with an end-to-end delay of only a few hundred of picoseconds. Parametric defects (such as small delay faults, resistive open/bridging faults, leakage faults, etc.) have been identified as new threats to the quality, yield, and reliability of a 3D-IC. In response to this challenge, numerous test methods have been developed. In this chapter, we will first discuss common defect types occurring to die-to-die interconnects, and then review various interconnect test methods applicable during the pre-bond stage and the post-bond stage.