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Development of Receiver Algorithms for Radio Frequency Identification ( RFID )

Radio Frequency Identification (RFID) is a very fast emerging technology for applications demanding identification or tracking purposes. In order to improve RFID technology development, new algorithms on signal processing are needed and new architectures need to be to explored and rated to find the most appropriate implementation. Rapid prototyping provides the flexibility and fast access desired for a wide range of different algorithm evaluations. The communication performance is improved by converting the received signal processing directly to digital processing devices. Newly developed standards are issued offering new opportunities to develop RFID systems that offer better performance. EPC Global has created widely accepted standards for product identification such as the EPC Class 1 Generation 2 standard for UHF domain RFID and is a field for improvements. This diploma thesis proposes several implementations designed and generated on electronic design automation tools that operate on a Xilinx Virtex II FPGA following the specifications of the ECP Global standard for the UHF RFID. These implementations include the entrance, image removal and matched filters in the signal processing receiver chain, as well as a synchronization method and its hardware implementation for the symbol detection of Miller codes. Measurements on board and bit error ratio simulations are used to rate the implemented algorithms.