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Thermal modeling for FinFET NAND gate circuits using a multi-block reduced-order model

An approach to thermal simulation of semiconductor ICs has been developed using a multi-block reduced-order model (ROM). The ROM projects the heat equation onto a functional space to represent the thermal solution using only a few degrees of freedom (DOF). The approach does not require any assumption on the physical geometry, dimensions, BCs or heat flow pathways. The developed approach is applied to a FinFET NAND gate circuit constructed using multiple blocks of a FinFET NAND gate. It is shown that the multi-block ROM approach is able to offer accurate thermal solution for a NAND IC subjected to power pulse excitations with large variations of pulse frequency, width, shape and time shift that substantially deviate from those used in the model construction. The approach offers accurate thermal solution as detailed as the detailed numerical simulation with a reduction in the numerical DOF by 5 to 6 orders of magnitude.