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Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards

In rapid prototyping system application, any large digital circuit can be implemented onto Multi-FPGA Board(MFB). Key MFB architectural feature is its inter-FPGA connections consisting of fixed connections(FC) i.e. FPGA-FPGA connections and programmable connections(PC) i.e. FPGA-programmable switch like FPID-FPGA. MFBs consisting of both the types of connections are known as hybrid MFBs. Since, PC requires two wires as against one wire in FC, MFB must have minimum number of PCs to keep fabrication easy. In partitioned circuit, multi-terminal nets (MTNs) are distributed over one or more circuit parts. When each circuit part is implemented over one FPGA, the MTNs between circuit parts will be routed over PCs and FCs between corresponding FPGAs. Multi-hop routers are used to minimize the use of PCs, but they increase source to sink delay with increasing number of hops. A generic multi-hop router to route two-terminal nets, which obeys the given limit on hops, was presented in our previous work [2002]. In this paper, we extend the same to route multi-terminal nets.