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Analyzing the Impact of SEUs on SRAMs with Resistive-Bridge Defects

The constant evolution and miniaturization of nanotechnology brought many revolutions to semiconductors, making the improvement of the Integrated Circuit manufacturing process necessary. Alongside, the increasing need to store more and more information as well as the device's high density, have resulted in the fact that Static Random Access Memories (SRAMs) occupy great part of Systems-on-Chip (SoCs). However, such evolution has led to the occurrence of manufacturing defects that may affect IC reliability and cause yield loss. Moreover, technology scaling has also brought attention to soft errors, which can be caused by inherent environmental noise. When considering both aspects, memory cells affected by weak resistive manufacturing defects, although not impaired under typical environments, may present peculiar behaviors when exposed to factors that can cause Single-Event Upsets (SEUs). In this context, this paper proposes to analyze the impact of environmental noise, in particular EMI and radiation, in SRAM cells with weak resistive-bridge defects that may escape manufacturing test due to their dynamic behavior. The proposed combined analysis has been performed using SPICE simulations adopting a commercial 65nm CMOS technology library.