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Reliability analysis of tree-based networks and its application to fault-tolerant VLSI systems

A probabilistic model is proposed that allows one to solve stochastic network reliability problems for tree-type networks of N nodes, taking O(log N) time. The considered networks are based on interconnection patterns consisting of complete binary trees in which spare edges are added according to different criteria. We show that the use of this probabilistic model allows one to evaluate, taking O(log N) time, The average connectedness (i.e., The expected number of processing elements still functioning in the presence of random faults) of dynamically reconfigurable fault-tolerant VLSI systems which are based on such tree-based structures. Finally, numerical results obtained from the model are provided that show that, given a fixed chip silicon area, several of the analyzed VLSI architectures have a notably greater expected number of working processing elements w.r.t. complete binary trees, in the presence of a given fault distribution.