{'fraction_non_alphanumeric': 0.026415094339622643, 'fraction_numerical': 0.006603773584905661, 'mean_word_length': 5.430303030303031, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS

In modern CMOS processes there are numerous failure mechanisms, including soft errors and metastability. Cosmic neutron-induced single event upsets, or soft-errors, have become a dominant failure mechanism in sub-100nm CMOS memory and logic circuits. The effects of metastability have also becoming increasingly significant in high-speed applications implemented in nanometric processes. In this paper the design tradeoffs for flip-flops between performance, soft-error robustness and metastability are described. Soft-error robust flip-flops are implemented based on both the DICE cell and the Quatro cell. SPICE simulations are used to characterize the performance and metastability robustness. The flip-flops were fabricated in the TSMC 40nm process and radiation measurements were performed at numerous test facilities. The Quatro flip-flop showed improved soft-error robustness and metastability when compared with both a reference flip-flop and a DICE flip-flop.