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A Case for Lifetime Reliability-Aware Neuromorphic Computing

Neuromorphic computing with non-volatile memory (NVM) can significantly improve performance and lower energy consumption of machine learning tasks implemented using spike-based computations and bio-inspired learning algorithms. High voltages required to operate certain NVMs such as phase-change memory (PCM) can accelerate aging in a neuron's CMOS circuit, thereby reducing the lifetime of neuromorphic hardware. In this work, we evaluate the long-term, i.e., lifetime reliability impact of executing state-of-the-art machine learning tasks on a neuromorphic hardware, considering failure models such as negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB). Based on such formulation, we show the reliability-performance trade-off obtained due to periodic relaxation of neuromorphic circuits, i.e., a stop-and-go style of neuromorphic computing.


I. INTRODUCTION
Spiking neural network (SNN) [1] is a machine learning technique designed using spike-based computation and bioinspired learning algorithms [2]. Neuromorphic hardware such as DYNAP-SE [3], TrueNorth [4], and Loihi [5] can execute SNN-based machine learning tasks in an energy-efficient manner, thanks to low-power neuron circuits [6], distributed implementation of computing and storage as crossbars [7], and the integration of non-volatile memory (NVM) for synaptic storage [8], [9]. Several techniques are recently proposed to map and execute SNNs on to neuromorphic hardware [10]- [15]. These techniques mostly target performance (e.g., accuracy) and energy of neuromorphic computing. Unfortunately, neuromorphic hardware are prone to reliability issues such as limited programming endurance, read disturbance of NVM cells, and aging of CMOS-based neuron circuits [16]- [18]. In this work, we focus on the circuit aging due to negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) failure mechanisms [19]- [21].
Due to the high voltage operating requirement of NVM, CMOS devices in a neuron circuit are exposed to high-voltage induced stress when propagating excitation (i.e., current) through an NVM synapse. This impacts the long-term, i.e., lifetime reliability of neuromorphic hardware. As memory process technology scales down to smaller dimensions, reliability issues are expected to exacerbate due to the following three reasons. First, the electric field and power density increase in scaled nodes, exceeding their corresponding maximum value for reliable operation. Second, increasing power density also leads to higher chip temperatures and consequently, an even faster acceleration of the degradation mechanisms. Third, new materials like high-k dielectrics and novel devices such as multi-gate field-effect transistor (FET) that are commonly used for the neuron circuit in neuromorphic hardware have unknown reliability behavior and they introduce new failure mechanisms at scaled nodes. In our recent work [22], we have analyzed NBTI failure in neuromorphic computing. This work extends our earlier work in the following three directions. First, we consider other failure mechanisms such as TDDB and show the impact of system-level design decisions on the circuit aging in neuromorphic hardware. Second, we consider aging in a neuron circuit, which drives current into a crossbar to read synaptic weights stored in its NVM cells. Third, we show the performance-reliability trade-off in periodic relaxation of neuron excitations in neuromorphic hardware using state-ofthe-art machine learning applications.

II. MODELING RELIABILITY OF CROSSBARS A. NBTI Issues in Neuromorphic Computing
This is a failure mechanism of CMOS devices inside a neuron, when positive charges are trapped at the oxidesemiconductor boundary underneath the gate of a CMOS [23]. NBTI manifests as 1) decrease in drain current and transconductance, and 2) increase in off current and threshold voltage. The lifetime of a CMOS device is measured in terms of its mean time to failure (MTTF) as MTTF NBTI = A V γ e Ea KT , where A and γ are material-related constants, Ea is the activation energy, K is the Boltzmann constant, T is the temperature, and V is the overdrive gate voltage of the CMOS device.
Recent studies suggest that a portion of the threshold voltage can be recovered by annealing at high temperatures if the NBTI stress voltage is removed. Figure 1 illustrates the stress and recovery of threshold voltage of a CMOS device due to NBTI failure mechanism on application of a high (V read = 1.8V) and a low voltage (V idle = 1.2V) to a CMOS device in a neuron circuit. We observe that both stress and recovery depends on the time of exposure to the corresponding voltage [24].

B. TDDB Issues in Neuromorphic Computing
This is a failure mechanism in a CMOS device, when the gate oxide breaks down as a result of long-time application of relatively low electric field (as opposed to immediate breakdown, which is caused by strong electric field) [25]. The TDDB lifetime of a CMOS device is MTTF TDDB = A.e −γ √ V , where A and γ are material-related constants, and V is the overdrive gate voltage of the CMOS device [26].

C. Circuit Aging in Neuromorphic Computing
To illustrate the degradation caused by these failure mechanisms, we take the example of a single neuron of the LeNet convolutional neural network (CNN) [27] used for handwritten digit recognition and illustrate its spike times within the first 100ms in Figure 2a. The voltage required to propagate these spikes through the neuron's fanout synapses are shown in Figure 2b. Figures 2c and 2d show the NBTI and TDDB aging of a CMOS device inside the neuron's circuit, respectively. As can be clearly seen, both aging increases with time as more spikes are generated by the neuron. If CMOS devices in the neuron circuit are not de-stressed regularly, the aging (both NBTI and TDDB) in a neuron continues to increase, eventually leading to transient, intermittent, or permanent faults in the neuromorphic hardware.    To de-stress a neuron, all CMOS devices in the neuron must be programmed with a voltage lower than the threshold voltage V th , which forces them to operate in the sub-threshold region, relieving their stress. Once discharged, a neuron requires several clock cycles to boost its voltage back to the required voltage level, before it can safely be used to generate spikes again. This introduces performance overhead.

III. PERIODIC RELAXATION OF NEUROMORPHIC CIRCUITS
To improve the long-term, i.e., the lifetime reliability of neuromorphic computing, we propose periodic relaxation of a neuromorphic architecture, where we de-stress all neurons in the hardware at fixed intervals. To compute the overhead due to such de-stress operations, we assume that the controller issues a de-stress command to a crossbar once every tDSI, which is known as the de-stress interval. Each de-stress operation completes within a time interval tDSC, known as the destress cycle time. Hence, the performance overhead (i.e., spike throughput loss) due to periodic de-stress is de-stress overhead = tDSC/tDSI.
(1) Figure 3 shows an example where four spikes (S1, S2, S3, & S4) generated by a neuron. These spikes have some idle time between them. The neuron circuits are de-stressed after every tDSI, such that the aging due to NBTI and TDDB (indicated by A TDDB and A NBTI , respectively) are lower than 1000 units. Using this approach, the de-stress operation is initiated upon generating S3, which increases the latency of S4 due to the non-zero latency of the de-stress operation (indicated by tDSC). Increase in spike latency can lead to information loss in SNNs and degrade the quality of response. We introduce two key performance metrics in SNNs that are affected due to periodic de-stressing of neuromorphic architectures -inter-spike interval (ISI) and disorder spike count. These are defined as follows.
• Inter-spike interval distortion: Performance of supervised machine learning is measured in terms of accuracy, which can be assessed from inter-spike intervals (ISIs) [28]. To define ISI, we let {t 1 , t 2 , · · · , t K } be a neuron's firing times in the time interval [0, T ]. The average ISI of this spike train is given by [28]: • Disorder spike count: This is defined for SNNs where information is encoded in terms of spike rate. We formulate spike disorder as follows.
be the expected spike arrival rate at neuron i andF i = {F i 1 , · · · ,F i n i } be the actual spike rate considering de-stress latencies. The spike disorder is computed as IV. EVALUATION We evaluate 10 standard machine learning applications, which are listed in Table I. A. Reliability  Figures 4a and 4b plot respectively, the NBTI and TDDB aging of the 10 machine learning applications when increasing the tDSI from 10ms to 50ms. We make the following three key observations. First, both NBTI and TDDB aging increases with increase in tDSI. This is because, a neuron accrues higher aging when its CMOS devices are kept active for longer duration (i.e., for higher tDSI). Second, the increase in aging is application dependent. For CNN-MNIST, increasing tDSI from 10ms to 50ms leads to 50% increase in NBTI aging, compared to VisualPursuit, where the NBTI aging increase by 5x. This is because, the number of spikes generated in CNN-MNIST is far fewer than in VisualPursuit, which leads to lower aging in neuron circuits. Therefore, the impact of increasing tDSI for CNN-MNIST is less significant compared to VisualPursuit. Third, compared to NBTI, the increase of TDDB agings are consistent across different applications for the same range of tDSI. This is due to the difference in the two mechanisms. NBTI-induced stress (e.g., V th shift) recovers partially when the neuron is idle. On the other hand, a CMOS devices encounters low-voltage TDDB stress even when idle.

B. Performance
Figures 5a and 5b plot respectively, the ISI distortion and disorder spike count (DSC) of the 10 machine learning applications when increasing the tDSI from 10ms to 50ms. We observe that both ISI and DSC reduces with increase in tDSI. This reduction is due to the reduction of the de-stress overhead (Equation 1) with an increase in tDSI.

C. Thermal Impact
The results of Sections IV-A are obtained at nominal temperature of 300K. Prior works such as [32] show the impact of temperature on reliability of conventional multiprocessor system. Figure 6 shows the increase of aging with temperature. Average circuit aging at 325K and 350K is higher than that at 300K by an average of 7% and 26%, respectively.  V. CONCLUSION We evaluate circuit aging in the neurons of neuromorphic architectures considering NBTI and TDDB failure mechanisms. We then propose a simple approach to improve reliability by periodically de-stressing its neurons. This introduces latency, which degrades key performance metrics such as inter-spike interval and disorder spike count, which correlates directly to the performance of machine learning models. We evaluate reliability-performance trade-offs for 10 state-of-the-art machine learning applications. We conclude that the proposed work will enable intelligent reliability optimization strategies in neuromorphic computing.