{'fraction_non_alphanumeric': 0.02321724709784411, 'fraction_numerical': 0.004975124378109453, 'mean_word_length': 5.3578947368421055, 'pattern_counts': {'":': 0, '<': 0, '<?xml version=': 0, '>': 0, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification

On-chip ESD (electrostatic discharging) protection is a challenging IC design problem New CAD tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification, which has been used to develop the first intelligent CAD tool of such kind. Design examples in 0.35μm BiCMOS are presented.