Take the 2-minute tour ×

I have to run these 4 commands on the terminal each time I want to execute the program using libraries.

The lines are

cc -m32 -c mylib.c
ar -rcs libmylib.a mylib.o
cc -m32 -c prog.c
cc -m32 prog.o -L. -lmylib

How do I make a makefile for the above commands and run it? A detailed procedure would be appreciated. Thanks.

Edit: Here is the solution:

a.out: prog.o libmylib.a
      cc prog.o -L. -lmylib

prog.o: prog.c mylib.h

libprint_int.a: mylib.o
      ar -rcs libmylib.a mylib.o

print_int.o: mylib.c mylib.h

      rm a.out prog.o libmylib.a mylib.o

This gave an error on line 2 because I used spaces instead of tab.

share|improve this question
There is a little redundancy here. With static libraries, you'll get the same result if you just link the .o files directly into the application, rather than stuffing them into a .a file first. A static library is little more than a bunch of .o files glued together, after all. –  Dietrich Epp Aug 3 '12 at 7:52
add comment

3 Answers

up vote 4 down vote accepted

Something like:

program_NAME := a.out

SRCS = mylib.c prog.c

.PHONY: all

all: $(program_NAME)

$(program_NAME): $(SRCS) 
    ar -rcs libmylib.a mylib.o
    cc -m32 prog.o -L. -lmylib

might get you started

only just started using makefiles myself and I think they are pretty tricky but once you get them working they make life a lot easier (this ones prob full of bugs but some of the more experienced SO folk will prob be able to help fix them)

As for running, make sure you save the file as 'Makefile' (case is important)

then from the cmd line (ensure you cd to the dir containing the Makefile):

$ make

thats it!


if the intermediate static library is superfluous you could skip it with a Makefile like this:

program_NAME := a.out

SRCS = mylib.c prog.c
OBJS := ${SRCS:.c=.o}

CFLAGS += -m32

program_INCLUDE_DIRS := 
program_LIBRARY_DIRS :=
program_LIBRARIES := mylib

CPPFLAGS += $(foreach includedir,$(program_INCLUDE_DIRS),-I$(includedir))
LDFLAGS += $(foreach librarydir,$(program_LIBRARY_DIRS),-L$(librarydir))
LDFLAGS += $(foreach library,$(program_LIBRARIES),-l$(library))



.PHONY: all

all: $(program_NAME)

$(program_NAME): $(OBJS) 
share|improve this answer
None of the above Makefiles is working. –  Aakash Anuj Aug 3 '12 at 15:26
It gives the error Makefile:25: *** missing separator. Stop. for the second and Makefile:10: *** missing separator. Stop. for the first –  Aakash Anuj Aug 3 '12 at 15:28
Please answer this –  Aakash Anuj Aug 3 '12 at 15:32
@user1506031, in a makefile rule, the blank space to the left of a command is not a string of spaces, it must be a TAB character. –  Beta Aug 3 '12 at 16:46
add comment

The simplest tutorial to understand make files is available in Cprogramming.com. Once you are through with understanding it then you can go though the make file manual.

share|improve this answer
add comment

I think there is no more detailed procedure than the official documentation of the make command: http://www.gnu.org/software/make/manual/make.html#Overview

Basically you will have to create a target and just put your commands in it. The target could be 'all' if you want it to work when you type 'make'. A good makefile will surely use variables etc to keep it flexible over the lib/sources additions.

share|improve this answer
add comment

Your Answer


