Figure 3-9 z14  PU core logical diagram Branch prediction Chapter 3. Central processor complex system design  101 Memory address generation and memory accesses can occur out of (program) order. This  capability can provide a greater use of the z14 superscalar core, and can improve system  performance.  The z14 processor unit core is a superscalar, out-of-order, SMT processor with 10 execution  units. Up to six instructions can be decoded per cycle, and up to 10 instructions or operations  can be started to run per clock cycle (<0.192 ns). The execution of the instructions can occur  out of program order, and memory address generation and memory accesses can also occur  out of program order. Each core has special circuitry to display execution and memory  accesses in order to the software.  The z14 superscalar PU core can have up to 10 instructions or operations that are running  per cycle. This technology results in shorter workload runtime. If the branch prediction logic of the microprocessor makes the wrong prediction, all  instructions in the parallel pipelines are removed. The wrong branch prediction is expensive in  a high-frequency processor design. Therefore, the branch prediction techniques that are used  are important to prevent as many wrong branches as possible. 