39 to multi-layer Flash memory.) tion V A. Two other approaches that have been dis- cussed are the implementation of a sublithographic cross- bar memory to go beyond the lithographic dimension, F [244, 245], and 3-D integration of multiple layers of memory, currently implemented commercially for write- once solid-state memory[246]. One example of such a stacked memory is the write- once anti-fuse memory technology developed by Matrix semiconductor (now part of SanDisk), which uses a high- performance polysilicon diode[246]. However, it is dif- ficult to obtain the high currents and current densi- ties needed for PCM from such diodes. This is the case even after accounting for the consideration that the lithographically-defined polysilicon diode can be 10 × larger in area than the sub-lithographic PCM device without increasing the 4 F 2 footprint. Thus the advent of 3D-in-the-BEOL PCM technology depends on either dramatic improvements in the current- carrying capability of polysilicon diodes, or on the devel- opment of a high-performance non-silicon access device. Such a device would need to be BEOL-compatible yet not require any temperatures higher than ∼ 400 $^{◦}$C, would need to readily pass the high currents (50-150 µ A) needed for PCM, yet must provide ultra-low leakage for all non- selected devices. For instance, in a “half-select” scheme implemented across a 1000 × 1000 device array, at the same instant that a selected device is receiving its RE- SET current, there are ∼ 2000 devices that share either the same word-line or bit-line with the selected device. Although these devices are each “seeing” half the voltage across the selected device, the total leakage through all these devices must remain much lower than the RESET current value, implying that the required ON-OFF ratio should be significantly in excess of 2000. However, if such an access device could be developed, since PCM itself has been proven to be BEOL-compatible, the path to 4-8 × increases in effective areal density would be available. In combination with 2-4 bits of MLC, this would provide an extremely attractive density– (and thus cost–) differen- tial over even 4-bit MLC Flash. A sublithographic crossbar memory requires a scheme for connecting the ultra-small memory devices laid out at tight pitch to the “larger” wiring created at the tightest pitch offered by lithography. One scheme that was pro- posed used a Micro-to-Nano Addressing Block, in which current injected into a lithographically-defined via was steered into one of several sublithographic wires using ei- ther precise control over depletion regions[245] or binary gating by overlying control gates[247]. These schemes work because lithography is typically capable of overlay errors that are 5-10 × smaller than the minimum size fea- ture. Thus overlying control gates can be placed to cover two but not three sub-lithographic wires, even though the control gate cannot possibly be made as narrow as the sub-lithographic wire. The weakness of such a sublithographic crossbar scheme is that it requires the creation and careful placement of sublithographic wire arrays of non-trivial complexity. Next-generation techniques such as im- print lithography may soon be capable of delivering small arrays at roughly the same pitch as cutting-edge lithography[247], but unfortunately pitches that are 4 × more dense than cutting-edge lithography is what would be required. Intriguingly, large portions of such sub- lithographic wire arrays would resemble simple grating patterns, suggesting the use of techniques such as in- terferometric lithography. Unfortunately, the addressing schemes require that wires at the edges of such arrays ter- minate precisely yet non-uniformly along the edge, thus complicating the task greatly for an interferometric ex- posure scheme[245, 247]. A more flexible approach is to build layers of PCM memory devices, stacking the memory in 3–D above the silicon wafer. This is not the same as 3–D packag- ing, where devices originally fabricated on separate sili- con wafers are connected together using vias that punch through the upper silicon layers to connect to the under- lying circuitry. Instead, the entire memory is built above a single layer of silicon just as the multiple wiring levels of a conventional semiconductor product are built in the “back end” of a CMOS process. This approach has several constraints, including the need to tolerate a significant BEOL temperature bud- get (an example might be ∼ 400 $^{◦}$C for > 1 hour) and the need to implement an access device for the PCM devices which can be produced in the metal-and-dielectric layers above the original silicon wafer. Given the difficulty of growing single-crystal silicon without a seed layer, this implies that the access device must be implemented with either a polysilicon or non-silicon device. (Note of course that the ability to easily grow multiple layers of high- quality silicon would likely enable a straightforward path However, these continuing worries about ultra-scaled Flash devices have not gone away — and the rapid in- creases in the size of the NAND Flash market, as driven PCM has made great strides over the past decade. Ten or so years ago, PCM was merely a long-dead technol- ogy that had, before expiring, helped point the way to fast-crystallizing materials and the mass-market success of read-write optical storage. At that point, any worries about the future of Flash technology were safely covered by the promise of Ferroelectric and Magnetic RAM. Since that time, both FRAM and MRAM have proved to be less scalable than had been hoped[31], although the origi- nal MRAM concept has since been mostly replaced by the more promising Spin-Transfer Torque (STT-RAM)[248] and Racetrack memory[249] concepts. In addition, as is often the case, the large and talented body of engineers working on Flash technology managed to hold off its “im- pending” demise and successfully scale their technology to smaller and smaller technology nodes. VI. CONCLUSIONS