17 the phase change volume are determined lithographically . However, use of a factor η ∼ 0 . 1, corresponding to a sub- lithographic CD for the phase change element of roughly F/ 3, allows Equation 6 to be satisfied for F ∼ 45nm, precisely where industry has been targeting first PCM products[135]. At this node, the required RESET cur- rent of 61 µ A (not that far from the demonstrated RE- SET current in Ref [134]) could be supplied by the CMOS transistor capable of 67 µ A. Thus there are two parallel routes to ensuring sufficient RESET current for PCM devices: • Use access devices that have higher current drive capability, including either known devices such as BJTs[44] or diodes[43] or novel devices such as surrounding-gate transistor[136] or FinFETs[137]. • Locally increase the current density within the phase change element and decrease the switching volume by creating sub-lithographic features in the current path through the PCM element. Both of these approaches have been pursued aggressively to demonstrate the basic operation of PCM technology. In this section, we will focus on the latter path: opti- mization of the phase change element itself by creation of a sub-lithographic aperture. A typical PCM cell is designed so that the only current path through the device passes through a very small aper- ture. As this aperture shrinks in size, the volume of phase change material that must be melted (and quenched into the amorphous state) to completely block it is reduced. In turn, this decreases the power (and thus the cur- rent) requirements. If this current is low enough, then a minimum-size access device can provide enough power to switch the cell from the SET state to the RESET state. In order to fabricate a PCM cell that will work even with these small currents, an innovative integration scheme is needed which creates a highly sub-lithographic yet controllable feature size. Subtle variations in cell de- sign may have a large impact on critical device character- istics, including endurance, retention, SET and RESET resistance distributions, and SET speed. These consider- ations will be the subject of Section III C. The cell design must be scalable as well as highly manufacturable, since scaling implies not only a shrink in physical dimensions of the memory cell, but also an increase in the number of memory cells per chip. Lastly, to maximize the number of bits per cell, a cell structure which allows multi-bit functionality is highly desirable[60, 138]. Depending on how this sub-lithographic aperture is im- plemented, PCM cell structures tend to fall into one of two general categories: those which control the cross- section by the size of one of the electrical contacts to the phase change material (contact-minimized, Fig- ure 12(a))[41, 139–144], and those which minimize the size of the phase change material itself at some point within the cell (volume-minimized, also known as con- fined, Figure 12(b))[41–43, 77, 103, 124, 138, 145–147]. which implies that transistor current scaling could only hope to catch up with the RESET current of lithographically–defined PCM devices at ultra-small technology nodes. This is especially sobering given that PCM RESET current, as shown in Figure 10, has been empirically observed to scale with CD at a pace some- where between F 1 . 5 and F 1 . $^{0}$, rather than as F $^{2}$. This analysis implies that minimal-width FETs can- not supply the necessary current if the dimensions of I$_{acc}$F > J$_{PCM}$ηF 2 $^{(}$1 . 5 × 10 $^{3}$µ A /µ m $^{)}$F > $^{(}$3 × 10 $^{5}$µ A /µ m 2 $^{)}$ηF 2 5nm > ηF, (6) Given a transistor of width F , the available transistor drive-current, I$_{acc}$F , must exceed the required current for RESET, J$_{PCM}$ηF $^{2}$, where η is an area factor between 0 and 1. Although returning to the SET state does involve exceeding the threshold voltage, the amount of power (and current) in the SET pulse is typically 40-80% that of the RESET pulse. Thus it is almost always the RE- SET pulse that must be considered when determining if the access device will supply sufficient current, while the SET pulse is typically the factor that dictates the write speed of PCM technology. Putting in the numbers above produces access devices in a PCM memory array have limited cur- rent drive capability; most optimized devices can provide only about I$_{acc}$ ∼ 800-1500 µ A/ µ m, where this current capability scales linearly with the effective gate width of the drive transistor. One way to solve this problem is to simply make the access device larger so that it can drive a larger current. However, since this immediately sacri- fices memory density which subsequently drives up the cost per MByte, such a move would be economic suicide for a prospective memory technology. FIG. 11: Back-of-the-envelope estimate for the expected pulse width and associated current density as function of the pitch 2 F of the active volume of the phase change material. Also shown are the empirical current densities for a phase-change bridge device (300 µ A for a H = 10nm, W = 30nm bridge[42], with the equivalent pitch for lithographic definition estimated to be 2 √ 10 ∗ 30 ∼ 35nm pitch), and 160 µ A for a 7.5nm × 65nm dash-type cell (plotted for an equivalent 45nm pitch).