3 progress in a short time, having passed older technolo- gies such as FeRAM and MRAM in terms of sophisti- cated demonstrations of scaling to small device dimen- sions. In addition, integrated large-array demonstrators with impressive retention, endurance, performance and yield characteristics[31] have been built. The paper is organized into 7 sections, beginning with the current section titled “Motivation for PCM.” Sec- tion I also includes a brief overview of PCM technology, and an assessment of how its characteristics match up with various potential applications across the memory- storage hierarchy. Section II goes into the physics behind PCM in more depth, in terms of the underlying phase change materials and their inherent scalability, and the physical processes affecting the switching speed of PCM devices. The section concludes with a survey of PCM modeling efforts published to date, and a discussion of scalability as revealed by ultra-small prototype PCM de- vices. of Flash devices takes over a millisecond to erase, and if written to continuously, would start to exhibit signifi- cant device failures in mere seconds. Sophisticated algo- rithms have been developed to avoid unnecessary writes, to perform static or dynamic wear-leveling, to pipeline writes, and to maintain pre-erased blocks in order to fi- nesse or hide the poor write/erase performance[28, 29]. Together with simple overprovisioning of extra capacity, these techniques allow impressive system performance. For instance, the Texas Memory Systems RamSan-500 can write at 2GB/sec with an effective Flash endurance of > 15 years[30]. However, it is interesting to note that despite the fact that MLC Flash costs much less than 1-bit/cell Single-Layer Cell (SLC) Flash, for a long time only SLC Flash was used in SSD devices[30]. This is because MLC Flash tends to have 10 × lower endurance and 2 × lower write speed than SLC Flash[30], illustrating the importance of these specifications within SSD appli- cations. Thus there is a need for a new next-generation NVM that might have an easier scaling path than NAND Flash to reach the higher densities offered by future technology nodes. Simultaneously, there is a need for a memory that could offer better write endurance and I/O perfor- mance than Flash, in order to bring down the cost while increasing the performance of NVM-based SSD drives. But the size of the opportunity here is even larger: the emergence of a non-volatile solid-state memory technol- ogy that could combine high performance, high density and low-cost could usher in seminal changes in the mem- ory/storage hierarchy throughout all computing plat- forms, ranging all the way up to high performance com- puting (HPC). If the cost-per-bit could be driven low enough through ultra-high memory density, ultimately such a Storage-Class Memory (SCM) device could po- tentially displace magnetic hard disk drives (HDD) in enterprise storage server systems. Fortunately, new NVM candidate technologies have been under consideration as possible Flash “replace- ments” for more than a decade[31]. These candidates range from technologies that have reached the market- place after successful integration in real CMOS fabs (fer- roelectric and magnetic RAM), to novel ideas that are barely past the proof-of-principle stage (racetrack mem- ory and organic RAM), to technologies that are some- where in-between (PCM, resistance RAM, and solid- electrolyte memory)[31]. Each of these has its strengths and weaknesses. In general, the farther along a tech- nology has progressed towards real integration, the more that is known about it. And as research gives way to de- velopment, it is typically new weaknesses — previously hidden yet all too quickly considered to be obvious in hindsight — that tend to be revealed. In contrast, by avoiding these known pitfalls, fresh new technologies are immediately attractive, at least until their own unique weaknesses are discovered. In this article, we survey the current state of phase change memory (PCM). This technology has made rapid In the RESET operation, a larger electrical current is applied in order to melt the central portion of the cell. To SET the cell into its low-resistance state, an electri- cal pulse is applied to heat a significant portion of the cell above the crystallization temperature of the phase change material. This SET operation tends to dictate the write speed performance of PCM technology, since the required duration of this pulse depends on the crystallization speed of the phase change material (Section II B). SET pulses shorter than 10ns have been demonstrated[33– 36]. Because the crystallization process is many orders of magnitude slower at low temperatures ( < 120 $^{◦}$C), PCM is a NVM technology that can offer years of data lifetime. Phase change memory (PCM) exploits the large re- sistance contrast between the amorphous and crystalline states in so-called phase change materials[32]. The amor- phous phase tends to have high electrical resistivity, while the crystalline phase exhibits a low resistivity, sometimes 3 or 4 orders of magnitude lower. Due to this large resis- tance contrast, the change in read current is quite large, opening up the opportunity for the multiple analog levels needed for MLC operations[32]. B. What is PCM? In Section III, we address factors that affect the de- sign and fabrication of PCM devices, including cell de- sign, variability, changes in the phase change material induced by the fabrication procedure, and the design of surrounding access circuitry. We then turn to issues re- lated to operation of PCM devices in Section IV, includ- ing endurance, retention, and device-to-device crosstalk. Section V addresses several factors that can be expected to enhance PCM in the future, including Multi-Level Cell technology for PCM, the role of coding, and possible routes to an ultra-high density PCM technology. The Conclusion section (Section VI) is followed by a brief Ac- knowledgements section (Section VII).