GLYPH<SM590000> Pipeline optimization: – Improved instruction delivery – Faster branch wakeup – Reduced execution latency – Improved OSC prediction GLYPH<SM590000> Second generation of Simultaneous multithreading (SMT): – Includes SAPs, zIIPs, and IFLs – Improved thread balancing – Multiple outstanding translations – Optimized hang avoidance mechanisms GLYPH<SM590000> Improved Hot Cache Line handling; dynamic throttling GLYPH<SM590000> Cache improvements: – New power efficient logical directory design – L1 I-Cache increased from 96 K to 128 K per Core (33%) – L2 D-Cache increased from 2 MB to 4 MB per Core (2x) – L3 Cache (shared) increased from 64 MB to 128 MB per CP SCM(2x) – New L4 Cache design with 672 MB (shared) per drawer and L4 sequential prefetch  GLYPH<SM590000> Enhanced binary coded decimal architecture (full set of register-to-register BCD  instructions) GLYPH<SM590000> New instructions for Single-instruction multiple-data (SIMD) operations GLYPH<SM590000> One cryptographic/compression co-processor per core, redesigned: – CP Assist for Cryptographic Functions (CPACF) (hardware) runs more operations,  such as SHA-3, SHAKE hashing algorithms, and True Random-number generation  (TRNG) – Improved Galois Counter Mode (GCM) performance – Entropy-Encoding Compression Enhancement with Huffman encoding – Order-Preserving compression  GLYPH<SM590000> Adjusted Hiperdispatch to use new chip configuration GLYPH<SM590000> Increased total number of PUs that are available on the system from 168 to 196, and  number of characterizable cores, from 141 to 170 GLYPH<SM590000> Hardware system area (HSA) increased from 96 GB to 192 GB GLYPH<SM590000> A total of 32 TB of addressable memory (configurable to LPARs) with up to 16 TB of  memory per LPAR GLYPH<SM590000> PR/SM enhancements: – Improved memory affinity – Optimized LPAR placement algorithms GLYPH<SM590000> Dynamic Partition Manager Version 3.2 – FC (with z14 hardware) and FCP storage support – Storage Groups management enhancements GLYPH<SM590000> SMT enablement for system assist processor (SAP) processors GLYPH<SM590000> New Coupling Facility Control Code (CFCC) with improved performance and following  enhancements: – Asynchronous Cross-Invalidate (XI) of CF cache Structures The z14 design features the following enhancements as compared with the z13: 456  IBM z14 (3906) Technical Guide