2.5.1 Memory subsystem topology The z15 memory subsystem uses high-speed, differential-ended communications memory  channels to link a host memory to the main memory storage devices. The CPC drawer memory topology of a z15 server is shown in Figure 2-21. Consider the following points regarding the topology: The z15 server uses the RAIM technology. The RAIM design detects and recovers from  failures of dynamic random access memory (DRAM), sockets, memory channels, or DIMMs. The RAIM design requires the addition of one memory channel that is dedicated for reliability,  availability, and serviceability (RAS). 2.5.2 Redundant array of independent memory Figure 2-21 CPC drawer memory topology at maximum configuration GLYPH<SM590000> One MCU per processor chip with five memory channels, one DIMM per channel (no  DIMM cascading) is used.  GLYPH<SM590000> The fifth channel in each MCU enables memory to be implemented as a Redundant Array  of Independent Memory (RAIM). This technology features significant error detection and  correction capabilities. Bit, lane, DRAM, DIMM, socket, and complete memory channel  failures can be detected and corrected, including many types of multiple failures.  Therefore, RAIM takes 20% of DIMM capacity. (No non-RAIM option is available.) GLYPH<SM590000> DIMM sizes used are 32, 64, 128, 256 and 512 GB with five DIMMs of the same size  included in a memory feature (160, 320, 640, 1280 and 2560 GB RAIM array size,  respectively). GLYPH<SM590000> Three or four features (15 or 20 DIMMs) are plugged in each drawer. GLYPH<SM590000> Features with different DIMMs sizes can be mixed in the same drawer. GLYPH<SM590000> The five DIMMs per MCU must be the same size. GLYPH<SM590000> Addressable memory is required for partitions and HSA. 58  IBM z15 (8561) Technical Guide