4 FIG. 1: Programming of a PCM device involves application of elec- trical power through applied voltage, leading to internal temperature changes that either melt and then rapidly quench a volume of amor- phous material (RESET), or hold this volume at a slightly lower tem- perature for sufficient time for recrystallization (SET). A low voltage is used to sense the device resistance (READ), so that the device state is not perturbed. the resistance states without perturbing them, high en- durance (allowing many switching cycles between SET and RESET), long data retention (usually specified as 10 year data lifetime at some elevated temperature), and fast SET speed (the time required to recrystallize the cell from the RESET state). Data retention usually comes down to the cell’s ability to retain the amorphous RE- SET state by avoiding unintended recrystallization. An additional aspect that can be of significant importance is the ability to store (and retain over time) more than one bit of data per cell, since this allows one to increase ef- fective density much like MLC Flash without decreasing the feature size. A critical property of phase change materials is the so-called threshold switching[45–48]. Without this effect PCM would simply not be a feasible technology, because in the high resistance state extremely high voltages would be required to deliver enough power to the cell to heat it above the crystallization temperature. However, when a voltage above a particular threshold V$_{t}$ is applied to a phase change material in the amorphous phase, the resulting large electrical fields greatly increase the elec- trical conductivity. This effect is still not completely un- derstood, but is attributed to a complex interplay be- tween trapped charge, device current, and local electri- cal fields[45, 49]. With the previously resistive material now suddenly highly conducting, a large current flows — which can then heat the material. However, if this cur- rent pulse is switched off immediately after the thresh- old switching, the material returns to the highly resis- tive amorphous phase after about 30ns[50], with both the original threshold voltage V$_{t}$ and RESET resistance recovering slowly over time[50, 51]. Only when a current sufficient to heat the material above the crystallization temperature, but below the melting point, is sustained for a long enough time does the cell switch to the crys- talline state. The threshold switching effect serves to make this possible with applied voltages of a few volts, despite the high initial resistance of the device in the RESET state. If this pulse is cut off abruptly enough, the molten ma- terial quenches into the amorphous phase, producing a cell in the high-resistance state. The RESET operation tends to be fairly current– and power–hungry, and thus care must be taken to choose an access device capable of delivering high current and power without requiring a significantly larger footprint than the PCM element it- self. The read operation is performed by measuring the device resistance at low voltage, so that the device state is not perturbed. These operations are summarized in Figure 1. Even though the principle of applying phase change materials to electronic memory was demonstrated as long ago as the 1960s[37], interest in PCM was slow to develop compared to other NVM candidates. However, renewed interest in PCM technology was triggered by the dis- covery of fast ( < 100 nanosecond) crystallizing materials such as Ge$_{2}$Sb$_{2}$Te$_{5}$ (GST) or Ag– and In–doped Sb$_{2}$Te (AIST)[38, 39] by optical storage researchers. Over the past few years, a large number of sophisticated inte- gration efforts have been undertaken in PCM technol- ogy, leading to demonstration of high endurance[40], fast speed[41], inherent scaling of the phase change pro- cess out beyond the 22nm node[42], and integration at technology nodes down to 90nm[43]. One impor- tant remaining unknown for the success of PCM tech- nology is whether the memory access device (diode[43], transistor[44], etc.) in a dense memory array will be able to supply sufficient current to RESET the PCM cell. Al- ready, in order to try to minimize the RESET current, it is assumed that the dimension of the phase change mate- rial will be only 30% of the lithographic feature size F [5], mandating the use of sub-lithographic techniques for ac- curate definition of this critical dimension (CD). How- ever, even with this difficult integration task, the success of PCM technology may end up depending on advances in the access device as much as on the PCM cell itself[5]. Important device characteristics for a PCM cell in- clude widely separated SET and RESET resistance dis- tributions (necessary for sufficient noise margin upon fast readout), the ability to switch between these two states with accessible electrical pulses, the ability to read/sense The ultimate goal of researchers and developers study- ing emerging memory technologies is to devise a univer- sal memory that could work across multiple layers of the existing memory hierarchy for modern computers. This memory hierarchy, shown in Figure 2, is designed to bridge the performance gap between the fast central processing units and the slower (sometimes much slower) memory and storage technologies, while keeping overall system costs down. Figure 3 shows how PCM is expected to compare to the four major incumbent memory and storage technologies in terms of cost and performance. The enormous range of cost and performance spanned by these technologies makes a single universal memory — one capable of replacing all of these well-established C. Potential applications of PCM