3.3.1 Cache levels and memory structure The z14 memory subsystem focuses on keeping data “closer” to the PU core. With the  current processor configuration, all on chip cache levels increased. The z14 cache levels and memory hierarchy are shown in Figure 3-1. While L1, L2, and L3 caches are implemented on the CP SCM, the fourth cache level (L4) is  implemented within the system controller (SC) SCM. One L4 cache is present in each CPC  drawer, which is shared by all CP SCMs. The cache structure of the z14 has the following  characteristics: GLYPH<SM590000> Larger L1, L2, and L3 caches (more data closer to the core). GLYPH<SM590000> L1 and L2 caches use eDRAM, and are private for each PU core. GLYPH<SM590000> L2-L3 interface has a new Fetch cancel protocol, a revised L2 Least Recent Used (LRU)  Demote handling. GLYPH<SM590000> L3 cache also uses eDRAM and is shared by all 10 cores within the PU chip. Each CPC  drawer has five (M01 - M04) or six L3 caches (M05). Therefore, a four-CPC drawer system  Model M05 has 24 caches, which results in 3072 MB (24 x 128 MB) of this shared PU  chip-level cache. For availability and reliability, L3 cache now implements symbol ECC.  GLYPH<SM590000> L4 cache also uses eDRAM, and is shared by all PU chips on the CPC drawer. Each L4  cache has 672 MB inclusive of L3’s, 42w Set Associative and 256 bytes cache line size. A  four-CPC drawer system has 2688 MB (4 x 672 MB) of shared L4 cache.  Figure 3-1 z14  cache levels and memory hierarchy Up to 8TB addressable (Protected by RAIM) Chapter 3. Central processor complex system design  91