among the possible SiC facets, analogous to the dramatic differences in growth speed and layer orientation observed on the (0001) and (000 ¯ 1) faces, 8,18 and the (1 ¯ 10 n ) facet chosen here is possibly not the most desirable in terms of selectivity and quality of graphene produced. This is particularly true of facets prepared on the (000 ¯ 1) surface, where there is apparently more freedom in facet choice. This is a topic of ongoing research, but the directions are clear. These results show that graphene growth on non-traditional crystal faces is viable and incredibly useful in device fabrication, particularly for production of nanoribbons on a large scale, and fabrication of graphene transistors at a density greater than 40,000 per cm 2 rep- resents a milestone in the development of graphene electronics. Refinement of this approach appears imminent, as ribbon width is reduced, facet selection and selective graphene growth is optimized, and damage to ribbon edges by violent cutting processes is therefore elimi- nated. Pre-patterning of the SiC substrate is, in general, a new and promising direction in the development of epitaxial graphene electronics, as more complex structures and appli- cations are readily envisaged. It is furthermore an important coalescence of top-down and bottom-up lithographies. Substrates were nominally on-axis research-grade semi-insulating 4 H -SiC from Cree, Inc. Arrays of Ni lines were defined on the (0001) or (000 ¯ 1) SiC crystal face by a standard photolithographic lift-off process, and transferred into the SiC by a 43% SF$_{6}$/23% O$_{2}$/33% Ar RIE operating at 30 mTorr. RF power was tuned to give a SiC etch rate of 8 ˚ A / s, allowing precisely controllable etching. Ultrasonic treatment in nitric acid removed Ni from the SiC surface, and further cleaning and graphene growth proceeded as described previously. 6,7,18 O$_{2}$ RIE operating at 100 mTorr was tuned to give a graphene etch rate of ∼ 1 ˚ A / s, and etch time was several to a maximum of ten seconds. Samples were mounted with (1 ¯ 10 n ) facet parallel to ion flux. Pd/Au contacts were defined by e-beam or photo-lithographic lift-off. Atomic layer deposition (ALD) of Al$_{2}$O$_{3}$ was performed as described by Williams et al. 30 in a commercial Cambridge Nanosystems Savannah ALD system prior to photolithographic lift-off of an Al top-gate. Inclusion of an NO$_{2}$ functionalization step as specified by Williams was critical for uniform Al$_{2}$O$_{3}$ coverage. Raman mapping was performed with excitation wavelength 532 nm, lateral resolution ∼ 1 µ m, and 0 . 25 − 0 . 5 µ m grid spacing. 2D intensity 5 Methods