PR/SM can use dynamic PU reassignment to move processors (CPs, ZIIPs, IFLs, ICFs,  SAPs, and spares) to a different chip, node, and drawer to improve the reuse of shared  caches by processors of the same partition. It can use dynamic memory relocation (DMR) to  move a running partition’s memory to different physical memory to improve the affinity and  reduce the distance between the memory of a partition and the processors of the partition.  For more information about HiperDispatch, see 3.7, “Logical partitioning” on page 125 .  CPC drawers are interconnected in a point-to-point topology at SC level, which allows a CPC  drawer to communicate with every CPC drawer. Data transfer does not always have to go  through another CPC drawer (L4 cache) to address the requested data or control information. The z14 inter-CPC drawer communication structure is shown in Figure 3-4. 3.3.2 CPC drawer interconnect topology Figure 3-4 z14 CPC drawer communication topology 94  IBM z14 (3906) Technical Guide