Draft Document for Review January 13, 2020 5:02 pm 8456ch_RAS.fm Chapter 3. DS8900 reliability, availability, and serviceabilty  67 The POWER9 processor represents an important performance increase which can be as  high as 70% over previous comparable hardware generations. The POWER9 processor  features the following areas of innovation, enhancement, and consolidation: Areas of innovation, enhancement, and consolidation GLYPH<SM590000> Large on-chip low-latency L3 cache that is implemented in embedded dynamic random  access memory (eDRAM). Lower energy consumption and a smaller physical footprint are  benefits. GLYPH<SM590000> Cache hierarchy and component innovation. GLYPH<SM590000> Advances in memory subsystem with 8 memory channels. GLYPH<SM590000> Advances in off-chip signaling. GLYPH<SM590000> The POWER9 processor features intelligent threads that can vary based on the workload  demand. The system automatically selects whether a workload benefits from dedicating  as much capability as possible to a single thread of work, or if the workload benefits more  from spreading the capability across up to 96 threads (eight per core) of work by using  simultaneous multithreading (SMT). With more threads, the POWER9 processor can  deliver more total capacity as more tasks are accomplished in parallel. With fewer threads,  those workloads that need fast individual tasks can get the performance that they need for  maximum benefit. The remainder of this section describes the RAS features of the POWER9 processor. These  features and abilities apply to the DS8900F. You can read more about the POWER9 and  processor configuration, from the DS8900F architecture point of view, in 2.3.1, “IBM  POWER9-based servers” on page 37. The following sections describe the RAS leadership features of IBM POWER9 systems. POWER9 RAS features POWER9 processor instruction retry and recovery (IRR) POWER9 cache protection and cache error handling As with previous generations, the POWER9 processor can run processor instruction retry  and alternative processor recovery for many core-related faults. This ability significantly  reduces exposure to permanent and intermittent errors in the processor core. With the instruction retry function, when an error is encountered in the core in caches and  certain logic functions, the POWER9 processor first automatically retries the instruction. If the  source of the error was truly transient, the instruction succeeds and the system can continue  normal operation. Processor instruction retry protect processor and data caches. L1 cache is divided into sets.  The POWER9 processor can deallocate all but one set before a Processor Instruction Retry  is run. In addition, faults in the Segment Lookaside Buffer (SLB) array are recoverable by the  IBM POWER Hypervisor. The SLB is used in the core to run address translation calculations. The L2 and L3 caches in the POWER9 processor are protected with double-bit detect  single-bit correct error correction code (ECC). Single-bit errors are corrected before they are  forwarded to the processor, and they are then written back to L2 or L3.  In addition, the caches maintain a cache line delete capability. A threshold of correctable  errors that is detected on a cache line can result in purging the data in the cache line and  removing the cache line from further operation without requiring a restart. An ECC  uncorrectable error that is detected in the cache can also trigger a purge and delete of the  cache line. 