21 C. Variability nect can be fabricated under the PCM devices. Different types of variability can affect the operation, performance, endurance, and reliability of PCM devices, ranging from inter-cell variability introduced during pro- cessing, inter-cell variability as resistances change over time after programming, and cycle-to-cycle variation of the SET and RESET resistances of any given cell (intra- cell variability). While the read voltage, the RESET pulse, and the SET pulse can be optimized for the average memory cell, variations between cells must be minimized so that these same choices can successfully operate all the cells in the memory array. The same is true for the performance of the access device. tive Ion Etch, material deposition, chemical mechanical planarization, wet etches, etc.), each with associated vari- ability, before the final processed wafer is ready for the dicing and packaging of the chips. Variability in processes which affect either the structure of the phase change el- ement or the access device (transistor, diode, etc.) can contribute to the overall phase change device variability. These structural variations then translate into variations in electrical (device operation) properties of the device. Most relevant to the operation of PCM are the struc- tural physical properties which affect the temperature profile (how much heat is generated and where), the crit- ical limiting cross-sectional aperture (which must be fully blocked to get high resistance contrast), and the vol- ume where the phase change material undergoes repeated melting and crystallization. Crucial features of the cell are the aperture size and shape, the thickness and uni- formity of the phase change material (in both stoichiom- etry and doping), the resistivity and interface resistance of electrodes, the thermal conductivities of surrounding materials, and the stresses on the active switching volume introduced by surrounding material. As discussed in the previous section, several cell struc- tures have been proposed and developed in order to min- imize the required power (current) for RESET. Each of these structures employs a similar strategy for minimiz- ing the RESET power: at one and only one point within the cell, the electrical current is forced to pass through a small aperture. This aperture increases the current density, maximizing the thermal power which is gener- ated, and reducing the volume of high resistivity mate- rial needed to significantly alter the external device re- sistance. Together with the electrical and thermal prop- erties of the phase change material, electrodes, and sur- rounding materials, the size and shape of this aperture determines the temperature profile obtained within the phase change element for a given SET or RESET pro- gramming current pulse. In order to estimate the impact of small variations of the aperture size on the cell operation, it is instructive to examine the functional dependence of the aperture size on the required RESET programming current. We show the published dependence of the RESET current on the aperture size for the Bridge cell (Figure 10), the Pillar and Mushroom cells (Figure 18(a)), and the Pore cell (Figure 18(b)). In each case, the required current is a steep function of critical dimension. Variability intro- duces a distribution of PCM cells of different sizes and thus different RESET currents. In order to be sure to be able to RESET all of the devices, it is thus the largest di- ameter cell that dictates the required current-driving ca- pability of the access device. Variability directly reduces density by mandating a larger-area access device. At the same time, as we will see in Section IV C, switching cells with more power than is necessary has a strong and negative influence on device endurance. Thus this same variability may also reduce endurance in the smaller-area devices, which are being driven much harder than they Furthermore, this fabrication process must construct a fully integrated set of devices comprising a CMOS tech- nology (CMOS field effect transistors, diodes, resistors, capacitors, wiring levels, and the vias connecting them) in addition to the PCM devices (which usually reside on top of the CMOS devices, at the bottom of the wiring lev- els). Thus a wafer will undergo hundreds of processing steps (including photolithography, atomic implant, Reac- Each step in the process of fabricating a wafer of PCM memory devices is typically associated with one or more physical attributes (e.g., thickness, CD, sidewall-angle, etc.), each with a nominal target value. To illustrate the variability challenge inherent in wafer-level fabrication process, features on the order of nanometers (10 − 9 me- ters) must be accurately controlled across the surface of a wafer which spans nearly a third of a meter (0.3 meters). Exact control over such a large range of dimensions is im- possible. Consequently, each process is associated with an acceptable range around some target value. 1. Structural variability Any fabrication- or process-induced variability in the physical structure of the phase change element can re- sult in devices which react differently to the same stimuli. Thus any large collection of phase change elements, which because of variability are in similar yet non-identical states, may then propagate in time on different resis- tance trajectories. In addition to group behavior caused by inter-cell variability, there is also intra-cell variabil- ity produced by motion and rearrangement of the atoms within the active region of the phase change device dur- ing the programming of the phase change device. Under- standing the variability of PCM devices is particularly important in the context of multi-bit storage capability, due to the reduced margin between resistance levels that must be correctly sensed in order to successfully retrieve data. And finally, variability can be expected to play an increasingly important role in the scaling of PCM tech- nology into future technology nodes.