12.8 Workload performance variation 12.9 Capacity planning consideration for z15 12.9.1 Collect CPU MF counter data As the size of transistors approaches the size of atoms that stand as a fundamental physical  barrier, a processor chip’s performance can no longer double every two years (Moore’s Law $^{6}$  does not apply). A holistic performance approach is required when the performance gains are reduced  because of frequency. Therefore, hardware and software synergy becomes an absolute  requirement. Starting with z13, Instructions Per Cycle (IPC) improvements in core and cache became the  driving factor for performance gains. As these microarchitectural features increase (which  contributes to instruction parallelism), overall workload performance variability also increases  because not all workloads react the same way to these enhancements. Because of the nature of the z15 multi-CPC drawer system and resource management  across those drawers, performance variability from application to application is expected.  Also, the memory and cache designs affect various workloads in many ways. All workloads  are improved, with cache-intensive loads benefiting the most. For example, having more PUs  per CPC drawer, each with higher capacity than z14, more workload can fit on a z15 CPC  drawer. This configuration can result in better performance. For example, z14 two drawer  system model M02 can populate maximum 69 PUs.  In contrast, z15 two drawer system Max71 can populate maximum 71 PUs. Therefore, two  more PUs can share caches and memories within the drawer, so the performance  improvements is expected. The workload variability for moving from z13 and z14 to z15 expected to be stable. Workloads  that are migrating from z10 EC, z196, and zEC12 to z15 can expect to see similar results with  slightly less variability than the migration from z13 and z14. Experience demonstrates that IBM Z servers can be run at up to 100% utilization levels,  sustained. However, most clients prefer to leave some room and run at 90% or slightly under.  In this section, we describe recommended ways conduct capacity planning for z15.  Do not use MIPs or MSUs for capacity planning:  Do  not  use “one number” capacity  comparisons, such as MIPs or MSUs. IBM does not officially announce the processor  performance as “MIPs”. MSU is only a number for software license charge and it does  not represent for performance for the processor.  It is important to recognize the LSPR workload type of your production system. As described  in 12.7, “CPU MF counter data and LSPR workload type” on page 482, the capacity of the  processor is different from the LSPR workload type. By collecting the CPU MF SMF 113  record, you can recognize the workload type in a specific IBM-provided capacity planning  tool. Therefore, collecting CPU MF counter data is a first step to begin the capacity planning. 6 For more information, see the  Moore’s Law website . Chapter 12. Performance  483