Considerations Cache sizes are being limited by ever-diminishing cycle times because they must respond  quickly without creating bottlenecks. Access to large caches costs more cycles. Instruction  and data cache (L1) sizes must be limited because larger distances must be traveled to reach  long cache lines. This L1 access time generally occurs in one cycle, which prevents increased  latency. Also, the distance to remote caches as seen from the microprocessor becomes a significant  factor. An example is an L4 cache that is not on the microprocessor (and might not even be in  the same CPC drawer). Although the L4 cache is rather large, several cycles are needed to  travel the distance to the cache. The node-cache topology of z15 servers is shown in  Figure 3-2. GLYPH<SM590000> L3 cache also uses eDRAM and is shared by all 12 cores within the PU chip. For  availability and reliability, L3 cache implements symbol ECC.  GLYPH<SM590000> L4 cache also uses eDRAM, and is shared by all PU chips on the CPC drawer. Each L4  cache has 960 MB inclusive of L3’s, 60w Set  Associative, and 256-byte cache line size. A  five-CPC drawer system has 4800 MB (5 x 960 MB) of shared L4 cache.  GLYPH<SM590000> Main storage has up to 8 TB addressable memory per CPC drawer, which uses 20  DIMMs. A five-CPC drawer system can have up to 40 TB of main storage. In most real-world situations, a fair number of cache lines exist in multiple L3s underneath  a specific L4. The L4 does not contain the same line multiple times, but rather once with  an indication of all the cores that have a copy of that line. As such, 960 MB of inclusive L4  can easily cover 1024 MB of underlying L3 caches. Figure 3-2 z15 cache topology 94  IBM z15 (8561) Technical Guide