Also, the distance to remote caches as seen from the microprocessor becomes a significant  factor. Although the L4 cache is rather large, several cycles are needed to travel the distance  to the cache. The node-cache topology of z14 ZR1 servers is shown in Figure 3-1. Although large caches mean increased access latency, the new technology of CMOS 14S0  (14 nm chip lithography) and the lower cycle time allows z14 ZR1 servers to increase the size  of cache levels (L1, L2, and L3) within the PU chip by using denser packaging. This design  reduces traffic to and from the shared L4 cache, which is on another chip (SC chip).  Only when a cache miss occurs in L1, L2, or L3 is a request sent to L4. L4 is the coherence  manager, which means that all memory fetches must be in the L4 cache before that data can  be used by the processor. However, in the z14 ZR1 cache design, some lines of the L3 cache  are not included in the L4 cache.  Figure 3-1 z14 ZR1 cache topology 68  IBM 14 Model ZR1 Technical Guide