35 FIG. 33: Two example families of electrical signals that can be used for MLC programming: (a) rectangular pulses and (b) variable slope pulses. FIG. 32: Cycling of a pore-PCM GST device, showing a stuck-SET failure after ∼ 5 × 10 5 cycles, followed by ten pulses of reverse polarity (and of slightly-higher magnitude), which proved sufficient to alow cy- cling to continue for another 10 5 SET-RESET cycles. Reprinted with permission from Reference [228, 229] ( c ○ 2009 IEEE). FIG. 34: Example distribution of the logarithm of the resistance for each of four possible stored levels, implementing 2-bit MLC. The distributions shown here would suggest a non-negligible probability of classification error. necessarily the best approach. V. THE FUTURE OF PCM A. Multi-level cells (MLC) Judging from the recent history of the aggressive non- volatile memory market currently dominated by Flash, it is clear that all available directions for improving effec- tive density (e.g., the average number of information bits that can be stored per unit area) will be exploited. One direction, both promising and challenging, is that of the so-called multilevel cell (MLC) technology, which exploits the intrinsic capability of a memory cell to store analog data in order to encode more than one bit of digital data per cell. The feasibility of MLC for PCM has already been shown[60, 61, 162, 211], including the demonstra- tion of programming into both 4 and 16 sharply distinct analog levels, corresponding to two and four bits per cell, respectively. Such intermediate resistance levels are ob- tained by properly modulating the electrical signals used to program the PCM element. In Figure 33, two exam- ples of such signals are shown: (a) rectangular current pulses of different height h and width w [61, 162] and (b) variable slope pulses, with different duration d of the trailing edge of a trapezoidal pulse[60]. By controlling these parameters carefully, one can control the analog resistance of the PCM element and thus enable MLC op- eration. tions overlap, however, then there is a non-zero probabil- ity of level mis-detection at the receiver, resulting in the retrieval of erroneous data. The use of the logarithm of the resistance is expedient to obtain more uniform shapes of the distributions across all levels. However, it should be pointed out that since these levels are classified using read current, the optimal configuration may not neces- sarily call for spacings between levels that are uniform in either resistance or log(resistance). There are several factors that can limit the number of effective levels that can be reliably stored in a PCM cell. Among them are The degree of success of such an MLC writing scheme can be characterized by the resistance distributions over a large ensemble of PCM devices. Figure 34 illustrates this concept: each of the four levels labeled “00,” “01,” “10,” and “11” is associated with a resistance distribu- tion. In a perfect world, these distributions would be delta functions, simplifying the classification process into a straightforward thresholding operation. If the distribu- Some of these factors, such as short and long term drift, represent a fundamental limitation to the storage capac- ity —the maximum number of bits that can be stored in the average PCM cell. As such, these factors cannot be overcome but only mitigated, as we will discuss later. In contrast, factors such as write noise and, to a cer- tain extent, array variability do not directly limit the • Crystallization of the amorphous phase, which we’ll refer to as long term drift . • Array variability, which includes any variability during the lifetime of the PCM array; • Resistance drift, which we’ll refer to as short term drift ; • The intrinsic randomness associated with each write attempt, or write noise ;