US 20150099364Al  c19)  United States  c12)  Patent Application Publication  Yu et al.  c10)  Pub. No.: US 2015/0099364 Al  (43)  Pub. Date:  Apr. 9, 2015  (54)  METHOD FOR INTEGRATED CIRCUIT  FABRICATION  (71)  Applicant:  Taiwan Semiconductor Manufacturing  Company, Ltd.,  Hsin-Chu (TW)  (72)  Inventors:  Ching-Fang Yu,  Hsin-Chu City (TW);  Ting-Hao Hsu,  Hsin-Chu (TW);  Chia-Ching Huang,  Su-ao Township  (TW)  (73)  Assignee:  Taiwan Semiconductor Manufacturing  Company, Ltd.,  Hsin-Chu (TW)  (21)  Appl. No.:  14/045,963  (22)  Filed:  Oct. 4, 2013  (52)  U.S. Cl.  CPC ..................................  HOJL 2112633  (2013.01)  (51)  Int. Cl.  HOJL21/263  (2006.01)  Publication Classification  (57)  ABSTRACT  Provided is an integrated circuit (IC) fabrication method. The  method includes receiving a mask, the mask having a plural› ity of dies and receiving a wafer, the wafer having a resist  layer. The method further includes exposing the resist layer  using the mask with a fraction radiation dose thereby forming  a first plurality of images; re-positioning the mask relative to  the wafer; and exposing the resist layer using the mask with  another fraction radiation dose. A second plurality of images  is formed, wherein a portion of the second plurality of images  is superimposed over another portion of the first plurality of  images. 