US 10,845,704 B2  1  2  EXTREME ULTRAVIOLET  PHOTOLITHOGRAPHY METHOD WITH  INFILTRATION FOR ENHANCED  SENSITIVITY AND ETCH RESISTANCE  BACKGROUND  DETAILED DESCRIPTION  BRIEF DESCRIPTION OF THE DRAWINGS  This application claims the benefit of U.S. Provisional  Application 62/752,692 entitled "Lithography Process with  Improved Sensitivity and Etch Resistance," filed Oct. 30,  2018, herein incorporated by reference in its entirety.  FIGS.  6A  and  6B  illustrate cross-sectional views of a  semiconductor structure at various fabrication stages, in  accordance with some embodiments.  FIG.  7  illustrates a cross-sectional view of a semiconduc- tor structure at various fabrication stages, in accordance with  some embodiments.  FIG.  8  illustrates a photoresist material of FIG.  SA  in  accordance with some embodiments.  The  following  disclosure  provides  many  different  embodiments, or examples, for implementing different fea- tures of the provided subject matter. Specific examples of  components and arrangements are described below to sim› plify the present disclosure. These are, of course, merely  examples and are not intended to be limiting. For example,  the formation of a first feature over or on a second feature  in the description that follows may include embodiments in  which the first and second features are formed in direct  contact and may also include embodiments in which addi› tional features may be formed between the first and second  features, such that the first and second features may not be  in direct contact. In addition, the present disclosure may  repeat reference numerals and/or letters in the various  examples. This repetition is for the purpose of simplicity and  clarity and does not in itself dictate a relationship between  the various embodiments and/or configurations discussed.  Moreover, the formation of a feature on, connected to,  and/or coupled to another feature in the present disclosure  that follows may include embodiments in which the features  are formed in direct contact, and may also include embodi› ments in which additional features may be formed interpos› ing the features, such that the features may not be in direct  contact. In addition, spatially relative terms, for example,  "lower," "upper," "horizontal," "vertical," "above," "over,"  "below," "beneath," "up," "down," "top," "bottom," etc. as  well as derivatives thereof (e.g., "horizontally," "down› wardly," "upwardly," etc.) are used for ease of the present  disclosure of one features relationship to another feature.  The spatially relative terms are intended to cover different  orientations of the device including the features. Still further,  when a number or a range of numbers is described with  "about," "approximate," and the like, the term is intended to  encompass numbers that are within a reasonable range  including the number described, such as within +/-10% of  the number described or other values as understood by  person skilled in the art. For example, the term "about 5 nm"  encompasses the dimension range from 4.5 nm to 5.5 nm.  The present disclosure is generally related to methods for  semiconductor device fabrication, and more particularly to a  lithography patterning process associated extreme ultravio› let (EUV) radiation. In lithography patterning, after a pho- toresist ( or simply resist) film is exposed to a radiation, such  as a EUV radiation, it is developed in a developer (a  chemical solution). The developer removes portions (such as  exposed portions as in a positive-tone photoresist or unex› posed portions as in a negative-tone photoresist) of the  photoresist film, thereby forming a photoresist pattern which  may include line patterns and/or trench patterns. The pho› toresist pattern is then used as an etch mask in subsequent  etching processes, transferring the pattern to an underlying  material layer. Alternatively, the photoresist pattern is then  used as an ion implantation mask in subsequent ion implan› tation processes applied to the underlying material layer,  such as an epitaxial semiconductor layer.  The semiconductor integrated circuit  (IC) industry has  experienced exponential growth. Technological advances in  IC materials and design have produced generations of ICs  where each generation has smaller and more complex cir› cuits than the previous generation. In the course of IC  evolution, functional density (i.e., the number of intercon› nected devices per chip area) has generally increased while  geometry size (i.e., the smallest component ( or line) that can  be created using a fabrication process) has decreased. This  scaling down process generally provides benefits by increas› ing production efficiency and lowering associated costs.  Such scaling down has also increased the complexity of  processing and manufacturing ICs. For example, as the  semiconductor fabrication continues to shrink pitches below  20 nm nodes, traditional i-ArF were confronted a huge  challenge. The optical restriction leads to resolution and  lithography performance that camiot meet targets. Extreme  ultraviolet (EUV) lithography has been utilized to support  critical dimension (CD) requirements of smaller devices.  EUV lithography employs scamiers using radiation in the  EUV region, having a wavelength of about 1 nm to about  100 nm. Some EUV scamiers provide 4x reduction projec- tion printing onto a resist film coated on a substrate, similar  to some optical scanners, except that the EUV scanners use  reflective rather than refractive optics. EUV lithography has  imposed a complex set of requirements upon the photoresist  film. The photo acid generator (PAG) in ArF resist absorbs  193 nm wave and generates photoacid, and the acid has 1000  times chemical amplifier reaction (CAR) and deprotects acid  labile group. However, the existing photoresist is not sen› sitive to EUV. Due to low source power of EUV tool and  other factors, photoresist is not efficient to generate enough  acid for desired resolution, leading to various patterning  issues, such as line width roughness and CD uniformity.  What are needed are a photoresist and a method of lithog› raphy patterning to have improvements in this area.  The present disclosure is best understood from the fol› lowing detailed description when read with the accompany› ing figures.  It is emphasized that, in accordance with the  standard practice in the industry, various features are not  drawn to scale and are used for illustration purposes only. In  fact, the dimensions of the various features may be arbi› trarily increased or reduced for clarity of discussion.  FIG.  1  illustrates a flowchart of a lithography patterning  method in accordance with some embodiments.  FIGS.  2, 3  and  4  illustrate flowcharts of a lithography  patterning method in accordance with various embodiments.  FIGS.  SA, SB, SC, SD, SE, SF  and  SG  illustrate cross› sectional views of a semiconductor structure at various  fabrication stages, in accordance with some embodiments. 