The vector register file overlays the floating-point registers (FPRs), as shown in Figure 3-8.  The FPRs use the first 64 bits of the first 16 vector registers, which saves hardware area and  power, and makes it easier to mix scalar and SIMD codes. Effectively, the core gets 64 FPRs,  which can further improve FP code efficiency. SIMD instructions include the following examples: For most operations, the condition code is not set. A summary condition code is used only for  a few instructions. z15 SIMD features the following enhancements: Figure 3-8 Floating point registers overlaid by vector registers GLYPH<SM590000> Integer byte to quadword add, sub, and compare GLYPH<SM590000> Integer byte to doubleword min, max, and average GLYPH<SM590000> Integer byte to word multiply GLYPH<SM590000> String find 8-bit, 16-bit, and 32-bit  GLYPH<SM590000> String range compare GLYPH<SM590000> String find any equal GLYPH<SM590000> String load to block boundaries and load/store with length GLYPH<SM590000> Doubled vector double precision Binary Floating Point (BFP) operations throughput (2x  64b) GLYPH<SM590000> Added vector single precision BFP (4x 32b) GLYPH<SM590000> Added vector quad precision BFP (128b) GLYPH<SM590000> Added binary Fixed Multiply Add (FMA) operations to speed up code GLYPH<SM590000> Vector Single Precision/ Double Precision/ Quad Precision (SP/DP/QP) compare/min/max  with programming language support Chapter 3. Central processor complex design  101