31 that, for most researchers working in the PCM field, ther- mal crosstalk or “proximity disturb” is considered to be a second–order rather than first–order problem. In fact, the small amount of empirical data available on proxim- ity is focussed primarily on the absence of any crosstalk effects[147, 211]. Pirovano et. al. showed with careful thermal simula- tions that, at least out to the 65nm node, the thermal crosstalk between cells should remain low enough that 10-year lifetime will not be significantly reduced by write disturbs from neighboring cells[41]. Figure 27 shows their simulated temperature profiles for the 180nm and 65nm nodes, assuming “micro-trench”-type PCM cells. The expected temperature rise at the position of the neigh- boring cell remains well below 100 $^{◦}$C. Russo et. al. did a similar study extending down to the 16nm node[129]. They found that isotropically-scaled devices, where all cell dimensions scale with the technology node, can be expected to experience no thermal crosstalk problems. However, because their cell designs had been optimized to emphasize low RESET current without any considera- tion to efficiency, RESET power or proximity effects[128], the hottest point in their cells is deep within the highly resistive heater electrode (both for the mushroom cell, which they refer to as a “lance” cell, and to a lesser ex- tent for the micro-trench cell). As a result, the temper- ature at the neighboring cell grows rapidly if only the lateral dimensions are scaled (non-isotropic scaling). De- spite these highly power-inefficient design points, though, Russo et. al. found it straightforward to avoid ther- mal crosstalk simply by choosing a mixed scaling ap- proach that decreased both the lateral and thickness dimensions[129]. One observation made by Russo et. al. is that as the spacing between devices drops, the time dimension be- comes much less effective as an avenue for avoiding prox- imity issues[129]. As the size of the heated volume de- creases, the thermal time-constant τ$_{th}$ decreases, but the characteristic thermal diffusion length L$_{th}$ drops more slowly (scaling as √ τ$_{th}$ ). Thus as the technology node scales down, the neighboring device eventually moves in- side the characteristic thermal diffusion length. This ef- fect is noticeable even in the data of Pirovano et. al. – in Figure 27(a), one can avoid experiencing the max- imum steady-state temperature change by simply using a very short RESET pulse, while in Figure 27(b), the difference between the temperature rise due to a short RESET pulse and the steady-state temperature rise has become much smaller. To a certain extent, knowledge of the temperature to which neighboring cells will be heated during RESET can be combined with retention measurements which re- veal a failure time (curves of t$_{X}$ vs. 1/ k$_{B}$T [201–203]) in order to estimate the effect of proximity disturb. The additive effects of retention and proximity both need to be considered to account for data integrity loss in high density PCM based crosspoint memory arrays. In partic- ular, the presence of even modest proximity effects can However, it is important to keep in mind that the tem- perature distribution during a retention-failure measure- ment is completely homogeneous across the PCM cell. In contrast, in proximity disturb situations, the tem- peratures are strong functions both of position within the neighboring PCM cell and of time, due to the fast thermal transients during RESET pulses and any slow ramp-downs used at the end of long SET pulses. This is particularly relevant when considering that early-to- fail retention problems are attributed to the unpleasantly rapid generation of a percolation path that connects a statistically–rare chain of crystalline nuclei. For proxim- ity disturb, this unlucky combination of closely-set nuclei could only lead to trouble if it were also located at the extreme edge of the amorphous plug, where the maxi- mum temperature excursion generated by the frequently- cycled neighbor could then rapidly drive retention failure. push the temperature for which acceptable retention is required significantly higher than the actual maximum average operating temperature of the memory chip. FIG. 27: Simulated temperature profiles for PCM devices (“micro- trench”-type devices) for the 180nm and 65nm technology nodes. Reprinted with permission from Reference [41] ( c ○ 2003 IEEE). Note that while the transient temperatures become close to the steady-state temperature, the expected temperature rise at the neighboring device remains much lower than 100 $^{◦}$C.