of 24 − 28 ◦ across multiple samples and locations, corresponding to the high-index SiC facet (1 ¯ 10 n ), where n ≈ 8. The precise facet obtained is dependent on processing temperature. 24 Ribbon samples were prepared for electrical measurement by exposure to an extremely short directional O$_{2}$ RIE to remove any graphene fragments from the horizontal (0001) surface. This was verified by Raman mapping, as shown in Fig. 4b. Extensive electrical probing confirmed lack of measurable conductivity on the horizontal surfaces. Note that this processing step will very likely become unnecessary with refinement of preferential growth parameters. Metal contacts were deposited for four-terminal measurements without gate and two-terminal measurements with top gate. In the latter case, an Al$_{2}$O$_{3}$ dielectric was deposited by atomic layer deposition (ALD) followed by deposition of the metal gate [see Fig. 2]. Measurement of four-terminal test structures [see inset, Fig. 4c] yielded sheet resistances of 180-500 Ω/sq., values typically observed in as-grown planar graphene, 8 suggesting that the quality of these ribbons does not differ dramatically from that of the planar material. Fig. 4c shows a series of conductance vs. source-drain voltage curves taken between 77 K and 4 K. The behavior is metallic at high temperatures, but quantum confinement is clearly manifested in the nonlinearity observed at 4 K, indicating presence of a small band gap, as expected of this ∼ 200 nm ribbon and in agreement with previous reports. 7 Photolithographic processing allows fabrication of a large number of devices at higher density. An array of top-gated graphene transistors prepared on the (000 ¯ 1) face of a 4 × 6 mm SiC chip with SiC etch depth ∼ 100 nm is shown in Fig. 5b. A single device (source, drain, channel, and gate, as illustrated in Fig. 2) occupies a 35 × 65 µ m area, so the 0 . 24 cm 2 chip accommodates more than 10,000 transistors. This density was limited primarily by the size of the probe tips used for electrical measurement, but it is, to our knowledge, the highest density of graphene transistors achieved to date. The room temperature gating effect is plotted in Fig. 5b. While transport characteristics of the various devices are reasonably consistent, there is work to be done in improving the selective growth and patterning. Two imminent changes will dramatically enhance this effect: reducing the growth temperature and time to in turn reduce the number of graphene layers on the facet, significantly improving gating efficiency, and reducing the SiC etch depth to narrow the ribbon, inducing a band gap at room temperature. It should be noted that there are likely fundamental differences in the graphene growth 4