28 encapsulation in their 90nm diode-accessed high-density PCM demonstration. the TEC/GST/BEC current path and thus reduce the write current. They also noticed that edge damage in small GST cells could lead to increased initial cell resis- tance. Ahn et al[160] used nitrogen-doped GST so as to increase the dynamic resistance and lower the writing current. However, they found that higher nitrogen dop- ing increased the cell’s contact resistance and broadened its distribution across cells. They suggested that this was due to instability between the BEC and GST caused by the nitrogen doping and exacerbated by interface defects and the subsequent thermal processing. In addition, they observed that smaller cells exhibited a wider SET resis- tance distribution. This was attributed to the effects of contaminants and GST etch-related damage. By appro- priate interface treatment, optimization of the GST etch process, minimization of process damage, and thermal budget reduction, they were able to obtain sharp SET and RESET resistance distributions. As part of ‘product-level reliability verification’ for 64Mb PCM chips, Kim et al[197] reported that the ac- tivation energy for loss of data retention (i.e. due to crystallization of amorphous volume) in fully processed PCM cells (2.1 eV) was lower than that measured on as- deposited films of the phase change material (2.46 eV). They suggested that the lower retention time in the fully processed cells could be attributed to higher nucleation probability resulting from processing damage on the GST or defects at the BEC/GST interface. In addition to de- veloping an optimized etch chemistry for patterning the GST/TE stack, Oh et al[43] used a line-type GST layout (as opposed to an island-type GST layout) thereby max- imizing the size of the patterned GST region and thus reducing the effect of RIE damage on the GST switching volume. There have been multiple reports on the development of confined PCM cell structures[146, 156]. While the most striking advantage of such cells is the reduced RE- SET current, the authors also point out that these cells are also more resilient to sidewall edge damage during BEOL processes since the volume of material undergo- ing phase change is farther away from the damaged edge regions of the cell. In particular, in their ‘on-axis confined cell’ structure, Cho et al[146] confirmed that there was no degradation, such as an increase in SET resistance, as the cell size was reduced. Song et al[143] pointed to the problem of increased SET resistance in devices due to oxygen pene- tration during BEOL processing steps that degraded the BE/GST interface through oxidation. In order to ad- dress this issue, they developed encapsulation processes for the GST cell. Operating under the constraints that the oxygen-blocking encapsulation layers should be scal- able and should not chemically react with GST films or degrade their electrical properties during deposition, they investigated a variety of encapsulation schemes. They found that a ‘double-capping’ technique worked best — resulting in reduced SET resistance while still being able to achieve low RESET currents. Oh et al[43] also used In order for a nonvolatile memory candidate to be con- sidered a viable next-generation memory option, it must demonstrate long term retention of stored data. The typ- ical criterion is 10 years (or 100,000 hours) at 85 $^{◦}$C, with fewer than 1 PPB (part per billion) retention failures at the array level over this entire lifetime, independent of the previous cycling history of the memory array[169, 199]. IV. PCM RELIABILITY A. Retention In summary, addressing yield loss in fully integrated PCM chips requires that adequate care be taken to min- imize process-related damage to the phase change ma- terial and its various interfaces. While the specific de- tails of optimized integration flows are not easily gleaned from the published literature, some of techniques that are usually mentioned include contamination reduction, GST/BEC interface optimization, minimizing the phase change material sidewall etch damage and/or keeping such damage as far away as practical from the active switching volume, and the use of encapsulating layers as protection from oxidation during BEOL processing. Modified PCM cell structures sometimes lead to dis- tinct problems with GST integration and related failure modes. A case in point is the ring-type bottom electrode cell, introduced by Ahn and coworkers[140] in order to re- duce the GST/bottom electrode contact area as well as its dependence on the patterned contact diameter. Sub- sequent researchers[143, 144] pointed out that a failure mechanism in these ring bottom electrode cells involved the formation of a recess in the core dielectric (that is sur- rounded by the ring electrode) due to the wet cleaning solution used in the CMP process. This led to increased effective GST/BE contact area and resulted in reduced RESET resistance. The authors solved this problem by optimizing the CMP process and using a more resilient While studying SET and RESET resistance distribu- tions in 4Mb-level PCM cell arrays, Mantegazza et al[198] found two kinds of anomalous cells that contributed to low resistance tails in the RESET distributions. One of those anomalous cell types showed saturation of RESET resistance at lower-than-desired values even if higher RE- SET currents were applied. These cells also had a dis- tinctly different (higher) slope in the plot of threshold voltage (Vt) vs. cell resistance. The authors found that these cells could be modeled as having a conducting path in parallel with the amorphous plug. They pointed to contamination or impurities in the active PCM volume as likely causes. Solving this problem required a modi- fied GST integration scheme that involved reducing the number of contamination sources, improving cell encap- sulation, and cleaning the heater/PCM interface.