7 FIG. 5: A semiconductor device technology node is commonly de- scribed by the minimum feature size F that is available via lithographic patterning. Thus the smallest device area that can be envisioned which is still accessible by lithographically-defined wiring is 4F 2 . To increase effective bit density beyond this, either sub-lithographic wiring, mul- tiple bits per device (analogous to Multi-Level Cell (MLC) Flash tech- nology), or multiple layers of stacked memory arrays are required, as described in Section V C. nal and ground. Thus, while NAND flash can inher- ently be packed more densely (due to its smaller unit cell size) than NOR flash, NOR flash offers significantly faster random access (since each cell in the array is di- rectly connected to the input lines). However, since NOR memory requires large programming currents (to place charge on the floating gate via channel hot electrons), its programming throughput (measured in MB/s) is much slower than that of the block-based NAND memory archi- tectures (which, by utilizing Fowler-Nordheim tunneling, can utilize lower programming currents that permit many bits to be processed in parallel)[58]. As a consequence, NOR memory offers significantly faster random access with low programming throughput and thus is mainly used for applications such as embedded logic that require fast access to data that is modified only occasionally. In contrast, NAND memory is a high-density, block-based architecture with slower random access which is mainly used for mass storage applications. NOR Flash memory cells occupy about 10F $^{2}$, with an access time upon read of a few tens of nanosec- onds or more. However, the access time upon write for NOR Flash is typically around 10 microseconds, and the write/erase endurance (for both NOR as well as NAND) is only 100k cycles. These characteristics are well within the capabilities of current PCMs. NOR Flash with its floating gate technology has difficulties scaling below 45nm, mainly due to difficulties in scaling the thickness of the tunnel oxide. It is thus no surprise that NOR Flash is the popular target for first replacement by most PCM developers. NAND Flash, on the other hand, is a much harder target despite PCM’s superiority in both endurance and read performance. Cost is the biggest challenge. A NAND Flash memory cell occupies only 4F 2 of chip area, and as discussed earlier, NAND will be able to maintain this through at least 22nm using trap storage technology[13] and possibly 3-dimensional integration[26]. Furthermore, MLC NAND has been shipping 2 bits per physical memory cell for years, and is promising to increase this to 4 bits per cell[59]. NAND Flash is mainly used in consumer electronic devices, where cost is the paramount concern, and in the emerging Solid State Drive (SSD) market to replace magnetic Hard Disk Drives (HDD), where both cost and reliability are important. The prerequisites for PCM to replace NAND Flash are 4F 2 memory cell size, at least 2-bit MLC capability, and 3-dimensional integration to further increase the effective number of bits per unit area of underlying silicon. A 4F 2 cell dictates a memory el- ement that can be vertically stacked over the select de- vice, as shown in Figure 5. Multi-level storage seems to be within reach of PCM given its inherently wide resis- tance range, and both 2- and 4-bits per cell has already been demonstrated in small-scale demonstrations[60, 61]. Even though write operations are slow for NAND Flash, it tends to achieve an impressive write data-rate because its low write power allows for programming of many bits The opportunity for SCM itself actually breaks into two segments: a slower variant, referred to as S–class SCM[29], which would act much like a Flash–based SSD except with better native endurance and write perfor- mance. Here access times of 1-3 µ sec would be acceptable, but low cost via high density would be of paramount importance. The other variant, referred to as M-class SCM[29], requires access times of 300ns or less, with both cost and power as considerations. This threshold of 300ns is considered to be the point at which an M- class SCM would be fast enough to be synchronous with memory operations, so that it could be connected to the In addition to the established segments of the mem- ory hierarchy we have described (SRAM, DRAM, and Flash), the gap in access times between 1ms and 100ns shown in Figure 4 opens up the possibility of Storage- Class Memory (SCM)[28, 29]. SCM would blur the tradi- tional boundaries between storage and memory by com- bining the benefits of a solid-state memory, such as high performance and robustness, with the archival capabil- ities and low cost of conventional hard-disk magnetic storage. Such a technology would require a solid-state nonvolatile memory that could be manufactured at an extremely high effective areal density, using some com- bination of sublithographic patterning techniques, mul- tiple bits per cell, and multiple layers of devices (Sec- tion V C). The target density probably needs to exceed current MLC NAND Flash densities by a factor of 2-8 × , in order to bring the cost of SCM down close to the cost of reliable enterprise HDD. 4. PCM as Storage-Class Memory in parallel. Thus to deliver equal or better write band- width, PCM developers will need to work on reducing the write power so that the data bus can be as wide as possible.