38 C. Routes to ultra-high density A complementary idea is the concept of adding cells Thus other techniques must be invoked in order to achieve the ultra-high memory densities that PCM will need, both in order to succeed as a successor to Flash and to enable new Storage Class Memory applications. We have already extensively discussed one of these, that is, multiple bits per cell using MLC techniques in Sec- Thus the eventual cost of PCM technology is abso- lutely key. While some of this depends on high-yield pro- cessing of robust PCM memory devices in high-volume manufacturing, a significant component of the cost equa- tion depends on implementation of ultra-high density. In particular, it is already clear that even 1 bit per 4F 2 will not catch up with NAND flash, since MLC Flash is al- ready 2 × better than this and moving towards 4 × higher densities[5]. As discussed earlier (Section I C), the cost of a semi- conductor technology depends strongly on its device den- sity. Even though PCM technology already appears to have a good chance of matching or exceeding Flash tech- nology in terms of performance and endurance, neither of these will matter if the cost of PCM does not (even- tually) match or improve upon Flash. For instance, one possible scenario might find PCM perpetually more ex- pensive than Flash, either because of cost issues related to large cell size or reliability issues that dampen achiev- able yield. Along this path, the future of PCM is dim — few customers will be willing to pay more for the better performance and/or endurance of what is essentially a new, unproven, and low-volume technology. But in the alternative scenario, where PCM can pass Flash in terms of cost, then not only would PCM be able to compete in all the markets that Flash now occupies, but it would be immediately more suitable for Solid-State Disk devices and other not-yet-existing Storage Class Memory appli- cations that may develop. with redundant content, rather than writing more pre- cise signals, which is a paradigm that is much more ac- cepted in the memory community as it matches estab- lished methods for designing reliable memories. The cor- rect balance between these two kinds of redundancies in a memory system design will ultimately depend on the design point for the memory, including expected density, power, bandwidth, latency, etc. One example of the op- tions available here is “endurance” coding, in which effec- tive PCM device endurance can be greatly extended by using full RESET pulses which melt the PCM material only sparingly[233], albeit at the cost of reduced stor- age capacity. Once the design guidelines are established and available technologies for doing iterative program- ming and analog to digital conversion are put forth, it is possible to objectively identify the best method for de- signing the various redundancies that will be necessary for the attainment of an extremely reliable and high den- sity PCM system. write pulse. Instead, write-and-verify techniques will be necessary to sharpen the distribution of the outcome of each write procedure. A write-and-verify procedure is associated with a probability of failure, because even af- ter exhausting the allowed resources (in terms of time, iterations, energy, etc), the resistance of a cell may still not be within the desired range around the target value. This probability of failure generally decreases as more re- sources are devoted to the write procedure, but in general will not be negligible. Error control coding can be pivotal in the management of these iterative write failures, provided that a good up- per estimate can be established for how often they are expected to happen. One possibility for handling these errors is to employ non-binary codes, that is, codes that detect and correct errors in symbols with more than 2 states. For example, a 4-bit/cell PCM may employ BCH codes defined over 4-bit symbols. If reliable information on the shape of the output distribution of an iterative write procedure is available, soft decoding procedures can be employed to improve the likelihood of successful de- coding of data. The change of programmed resistance due to short and long term drift are further exacerbated in the case of multibit PCM, and constitute the fundamental limitation in storage capacity. The effects of both of these phenom- ena are limited whenever the PCM devices have access to a reliable power source that allows them to do reg- ular refreshes (known as “scrubbings”) over time. This is often the case for PCM devices employed in a mem- ory context. In the case of a device intended for storage applications, no such guarantee of refresh power can be assumed. Thus the problem of recovering the stored in- formation is markedly harder. Fortunately, the relatively relaxed bandwidth and latency requirements demanded by storage applications allow for the possibility of more complex processing at a decoder. Such more complex processing can in general include signal processing to re- cover levels that have drifted (for short and long term drift) as well as advanced error control coding techniques that might incorporate soft information from the drift re- covery layer to enhance decoding success. From the perspective of a read operation, after adjust- ments for drift have taken place, a multibit PCM cell appears to be an analog write medium with some noise around a written level, with restrictions on the mini- mum and maximum value we might write on the medium. Many techniques can be borrowed from communication system theory that are relevant to this setting. For exam- ple, a technique that might prove relevant is the notion of trellis coded modulation (TCM). At a very high level, TCM is a method for obtaining highly reliable multi- bit cells that exploits the idea of writing coded levels in the memory at a precision higher than that ultimately intended. The specific manner in which this coding is designed is one of the cornerstone successes of communi- cation theory[243].