2 I. MOTIVATION FOR PCM A. The case for a next-generation memory cell designs were proposed, typically involving replace- ment of the floating polysilicon gate by some type of charge-trapping layer, such as the Silicon Nitride at the center of the Silicon-Oxide-Nitride-Oxide-Semiconductor (SONOS) cell structure[11]. While early SONOS mem- ory devices used extremely thin tunnel and blocking ox- ides for acceptable write/erase performance, and thus suffered from data retention issues[12], recent work seems to have migrated to Tantalum nitride–Alumina– Nitride–Oxide–Semiconductor (TANOS) structures[13– 16]. These structures offer improved immunity to both SILC and parasitic interference between cells[16], while also allowing any defects to gracefully degrade Signal- to-Noise Ratio (SNR) rather than serve as avenues for catastrophic charge leakage[9, 16]. TANOS data reten- tion has improved to acceptable levels[9], and the reduced programming efficiency is now understood[16]. However, TANOS structures cannot help to scale NOR Flash, because the charge injected at one edge of such devices by channel hot-electron injection[17] must be redistributed throughout the floating gate af- ter programming[10]. For NAND Flash, the finite and fairly modest number of discrete traps in each TANOS cell has accelerated the onset of new problems, rang- ing from device-to-device variations in V$_{t}$ [9], stochastic or “shot-noise” effects[9], random telegraph noise[18, 19], and a significant reduction in the number of stored elec- trons that differentiate one stored analog level from the next[20]. These issues are particularly problematic for Multi-Level Cell (MLC) Flash, where multiple analog lev- els allow an increase in the effective number of bits per physical device by a factor of 2, 3, or even 4. Worse yet, such few-electron problems will only increase with fur- ther dimensional scaling, leading Flash researchers to ex- plore even more complicated schemes for FinFET Flash devices[21, 22] or 3-D stacking of Flash memory[23–26]. With these difficulties in scaling to future technol- ogy nodes, Flash researchers are already hard-pressed to maintain specifications such as write endurance, reten- tion of heavily cycled cells, and write/erase performance, let alone improve them. As one indication of these pres- sures, some authors have pointed out that in cases such as digital photography, larger capacity formats can be expected to be tolerant of even more relaxed endurance specifications[20]. However, at the same time that Flash is struggling to maintain current levels of reliability and performance while increasing density, new applications are opening up for which these specifications are just barely adequate. The solid-state drive (SSD) market — long dominated by high-cost, battery-backed DRAM for military and other critical applications — has grown rapidly since the introduction of Flash-based SSD drives, passing $400 mil- lion in revenues in 2007[27]. One reason for the time delay between the widespread use of Flash in consumer applications and its appearance in SSD applications was the need to build system controllers that could hide the weaknesses of Flash. Consider that each underlying block Over the past few years, Flash has been wrestling with unpleasant tradeoffs between the scaling of lateral device dimensions, the need to maintain coupling be- tween the control and floating gates, the stress-induced leakage current (SILC) that is incurred by program- ming with large voltages across ultra-thin oxides, and the cell-to-cell parasitic interference between the stored charge in closely-packed cells[3, 8–10]. Many alternative Beyond the near-future, however, while the planned device sizes may be sketched out, for the first time in many years it is not clear exactly how achievable these goals might be. This uncertainty is present in many por- tions of the semiconductor industry, primarily due to the increasing importance of device-to-device variations, and to the common dependence on continued lithographic in- novation. New patterning techniques will almost cer- tainly be needed to replace the 193nm immersion and “double patterning” techniques now being used to im- plement the 32nm and even 22nm nodes[6, 7]. In addi- tion to such issues common to the larger semiconductor industry, however, the Flash industry faces additional uncertainties specific to its technology. As with many modern technologies, the extent to which non-volatile memory (NVM) has pervaded our day-to-day lives is truly remarkable. From the music on our MP3 players, to the photos on digital cameras, the stored e-mail and text messages on smartphones, the documents we carry on our USB thumb-drives, and the program code that enables everything from our portable electronics to cars, the NVM known as Flash memory is everywhere around us. Both NOR and NAND Flash be- gan humbly enough, as unappreciated side projects of a Toshiba DRAM engineer named Fujio Masuoka[1]. But from his basic patents in 1980 and 1987, respectively[1], Flash has grown in less than three decades to become a $20 billion dollar-per-year titan of the semiconductor industry[2, 3]. This market growth has been made possible by tremen- dous increases in the system functionality (e.g., more GBytes) that can be delivered in the same size package. These improvements are both a byproduct of — and the driving force for — the relentless march to smaller device dimensions known as Moore’s Law[4]. The history of the solid-state memory industry, and of the semiconductor industry as a whole, has been dominated by this concept: higher densities at similar cost lead to more functionality, and thus more applications, which then spur investment for the additional research and development needed to implement the “next size smaller” device. Throughout this extensive history, extrapolation from the recent past has proven to be amazingly reliable for predicting near- future developments. Thus the memory products that will be built in the next several years have long been forecast[5].